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MIPS: Loongson-3: Fast TLB refill handler
[deliverable/linux.git] / arch / mips / include / asm / mipsregs.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/war.h>
20
21 /*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25 #ifndef __STR
26 #define __STR(x) #x
27 #endif
28 #ifndef STR
29 #define STR(x) __STR(x)
30 #endif
31
32 /*
33 * Configure language
34 */
35 #ifdef __ASSEMBLY__
36 #define _ULCAST_
37 #else
38 #define _ULCAST_ (unsigned long)
39 #endif
40
41 /*
42 * Coprocessor 0 register names
43 */
44 #define CP0_INDEX $0
45 #define CP0_RANDOM $1
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
48 #define CP0_CONF $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
51 #define CP0_WIRED $6
52 #define CP0_INFO $7
53 #define CP0_HWRENA $7, 0
54 #define CP0_BADVADDR $8
55 #define CP0_BADINSTR $8, 1
56 #define CP0_COUNT $9
57 #define CP0_ENTRYHI $10
58 #define CP0_COMPARE $11
59 #define CP0_STATUS $12
60 #define CP0_CAUSE $13
61 #define CP0_EPC $14
62 #define CP0_PRID $15
63 #define CP0_EBASE $15, 1
64 #define CP0_CMGCRBASE $15, 3
65 #define CP0_CONFIG $16
66 #define CP0_CONFIG3 $16, 3
67 #define CP0_CONFIG5 $16, 5
68 #define CP0_LLADDR $17
69 #define CP0_WATCHLO $18
70 #define CP0_WATCHHI $19
71 #define CP0_XCONTEXT $20
72 #define CP0_FRAMEMASK $21
73 #define CP0_DIAGNOSTIC $22
74 #define CP0_DEBUG $23
75 #define CP0_DEPC $24
76 #define CP0_PERFORMANCE $25
77 #define CP0_ECC $26
78 #define CP0_CACHEERR $27
79 #define CP0_TAGLO $28
80 #define CP0_TAGHI $29
81 #define CP0_ERROREPC $30
82 #define CP0_DESAVE $31
83
84 /*
85 * R4640/R4650 cp0 register names. These registers are listed
86 * here only for completeness; without MMU these CPUs are not useable
87 * by Linux. A future ELKS port might take make Linux run on them
88 * though ...
89 */
90 #define CP0_IBASE $0
91 #define CP0_IBOUND $1
92 #define CP0_DBASE $2
93 #define CP0_DBOUND $3
94 #define CP0_CALG $17
95 #define CP0_IWATCH $18
96 #define CP0_DWATCH $19
97
98 /*
99 * Coprocessor 0 Set 1 register names
100 */
101 #define CP0_S1_DERRADDR0 $26
102 #define CP0_S1_DERRADDR1 $27
103 #define CP0_S1_INTCONTROL $20
104
105 /*
106 * Coprocessor 0 Set 2 register names
107 */
108 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
109
110 /*
111 * Coprocessor 0 Set 3 register names
112 */
113 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
114
115 /*
116 * TX39 Series
117 */
118 #define CP0_TX39_CACHE $7
119
120
121 /* Generic EntryLo bit definitions */
122 #define ENTRYLO_G (_ULCAST_(1) << 0)
123 #define ENTRYLO_V (_ULCAST_(1) << 1)
124 #define ENTRYLO_D (_ULCAST_(1) << 2)
125 #define ENTRYLO_C_SHIFT 3
126 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
127
128 /* R3000 EntryLo bit definitions */
129 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
130 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
131 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
132 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
133
134 /* MIPS32/64 EntryLo bit definitions */
135 #define MIPS_ENTRYLO_PFN_SHIFT 6
136 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
137 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
138
139 /*
140 * Values for PageMask register
141 */
142 #ifdef CONFIG_CPU_VR41XX
143
144 /* Why doesn't stupidity hurt ... */
145
146 #define PM_1K 0x00000000
147 #define PM_4K 0x00001800
148 #define PM_16K 0x00007800
149 #define PM_64K 0x0001f800
150 #define PM_256K 0x0007f800
151
152 #else
153
154 #define PM_4K 0x00000000
155 #define PM_8K 0x00002000
156 #define PM_16K 0x00006000
157 #define PM_32K 0x0000e000
158 #define PM_64K 0x0001e000
159 #define PM_128K 0x0003e000
160 #define PM_256K 0x0007e000
161 #define PM_512K 0x000fe000
162 #define PM_1M 0x001fe000
163 #define PM_2M 0x003fe000
164 #define PM_4M 0x007fe000
165 #define PM_8M 0x00ffe000
166 #define PM_16M 0x01ffe000
167 #define PM_32M 0x03ffe000
168 #define PM_64M 0x07ffe000
169 #define PM_256M 0x1fffe000
170 #define PM_1G 0x7fffe000
171
172 #endif
173
174 /*
175 * Default page size for a given kernel configuration
176 */
177 #ifdef CONFIG_PAGE_SIZE_4KB
178 #define PM_DEFAULT_MASK PM_4K
179 #elif defined(CONFIG_PAGE_SIZE_8KB)
180 #define PM_DEFAULT_MASK PM_8K
181 #elif defined(CONFIG_PAGE_SIZE_16KB)
182 #define PM_DEFAULT_MASK PM_16K
183 #elif defined(CONFIG_PAGE_SIZE_32KB)
184 #define PM_DEFAULT_MASK PM_32K
185 #elif defined(CONFIG_PAGE_SIZE_64KB)
186 #define PM_DEFAULT_MASK PM_64K
187 #else
188 #error Bad page size configuration!
189 #endif
190
191 /*
192 * Default huge tlb size for a given kernel configuration
193 */
194 #ifdef CONFIG_PAGE_SIZE_4KB
195 #define PM_HUGE_MASK PM_1M
196 #elif defined(CONFIG_PAGE_SIZE_8KB)
197 #define PM_HUGE_MASK PM_4M
198 #elif defined(CONFIG_PAGE_SIZE_16KB)
199 #define PM_HUGE_MASK PM_16M
200 #elif defined(CONFIG_PAGE_SIZE_32KB)
201 #define PM_HUGE_MASK PM_64M
202 #elif defined(CONFIG_PAGE_SIZE_64KB)
203 #define PM_HUGE_MASK PM_256M
204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
205 #error Bad page size configuration for hugetlbfs!
206 #endif
207
208 /*
209 * Values used for computation of new tlb entries
210 */
211 #define PL_4K 12
212 #define PL_16K 14
213 #define PL_64K 16
214 #define PL_256K 18
215 #define PL_1M 20
216 #define PL_4M 22
217 #define PL_16M 24
218 #define PL_64M 26
219 #define PL_256M 28
220
221 /*
222 * PageGrain bits
223 */
224 #define PG_RIE (_ULCAST_(1) << 31)
225 #define PG_XIE (_ULCAST_(1) << 30)
226 #define PG_ELPA (_ULCAST_(1) << 29)
227 #define PG_ESP (_ULCAST_(1) << 28)
228 #define PG_IEC (_ULCAST_(1) << 27)
229
230 /* MIPS32/64 EntryHI bit definitions */
231 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
232
233 /*
234 * R4x00 interrupt enable / cause bits
235 */
236 #define IE_SW0 (_ULCAST_(1) << 8)
237 #define IE_SW1 (_ULCAST_(1) << 9)
238 #define IE_IRQ0 (_ULCAST_(1) << 10)
239 #define IE_IRQ1 (_ULCAST_(1) << 11)
240 #define IE_IRQ2 (_ULCAST_(1) << 12)
241 #define IE_IRQ3 (_ULCAST_(1) << 13)
242 #define IE_IRQ4 (_ULCAST_(1) << 14)
243 #define IE_IRQ5 (_ULCAST_(1) << 15)
244
245 /*
246 * R4x00 interrupt cause bits
247 */
248 #define C_SW0 (_ULCAST_(1) << 8)
249 #define C_SW1 (_ULCAST_(1) << 9)
250 #define C_IRQ0 (_ULCAST_(1) << 10)
251 #define C_IRQ1 (_ULCAST_(1) << 11)
252 #define C_IRQ2 (_ULCAST_(1) << 12)
253 #define C_IRQ3 (_ULCAST_(1) << 13)
254 #define C_IRQ4 (_ULCAST_(1) << 14)
255 #define C_IRQ5 (_ULCAST_(1) << 15)
256
257 /*
258 * Bitfields in the R4xx0 cp0 status register
259 */
260 #define ST0_IE 0x00000001
261 #define ST0_EXL 0x00000002
262 #define ST0_ERL 0x00000004
263 #define ST0_KSU 0x00000018
264 # define KSU_USER 0x00000010
265 # define KSU_SUPERVISOR 0x00000008
266 # define KSU_KERNEL 0x00000000
267 #define ST0_UX 0x00000020
268 #define ST0_SX 0x00000040
269 #define ST0_KX 0x00000080
270 #define ST0_DE 0x00010000
271 #define ST0_CE 0x00020000
272
273 /*
274 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
275 * cacheops in userspace. This bit exists only on RM7000 and RM9000
276 * processors.
277 */
278 #define ST0_CO 0x08000000
279
280 /*
281 * Bitfields in the R[23]000 cp0 status register.
282 */
283 #define ST0_IEC 0x00000001
284 #define ST0_KUC 0x00000002
285 #define ST0_IEP 0x00000004
286 #define ST0_KUP 0x00000008
287 #define ST0_IEO 0x00000010
288 #define ST0_KUO 0x00000020
289 /* bits 6 & 7 are reserved on R[23]000 */
290 #define ST0_ISC 0x00010000
291 #define ST0_SWC 0x00020000
292 #define ST0_CM 0x00080000
293
294 /*
295 * Bits specific to the R4640/R4650
296 */
297 #define ST0_UM (_ULCAST_(1) << 4)
298 #define ST0_IL (_ULCAST_(1) << 23)
299 #define ST0_DL (_ULCAST_(1) << 24)
300
301 /*
302 * Enable the MIPS MDMX and DSP ASEs
303 */
304 #define ST0_MX 0x01000000
305
306 /*
307 * Status register bits available in all MIPS CPUs.
308 */
309 #define ST0_IM 0x0000ff00
310 #define STATUSB_IP0 8
311 #define STATUSF_IP0 (_ULCAST_(1) << 8)
312 #define STATUSB_IP1 9
313 #define STATUSF_IP1 (_ULCAST_(1) << 9)
314 #define STATUSB_IP2 10
315 #define STATUSF_IP2 (_ULCAST_(1) << 10)
316 #define STATUSB_IP3 11
317 #define STATUSF_IP3 (_ULCAST_(1) << 11)
318 #define STATUSB_IP4 12
319 #define STATUSF_IP4 (_ULCAST_(1) << 12)
320 #define STATUSB_IP5 13
321 #define STATUSF_IP5 (_ULCAST_(1) << 13)
322 #define STATUSB_IP6 14
323 #define STATUSF_IP6 (_ULCAST_(1) << 14)
324 #define STATUSB_IP7 15
325 #define STATUSF_IP7 (_ULCAST_(1) << 15)
326 #define STATUSB_IP8 0
327 #define STATUSF_IP8 (_ULCAST_(1) << 0)
328 #define STATUSB_IP9 1
329 #define STATUSF_IP9 (_ULCAST_(1) << 1)
330 #define STATUSB_IP10 2
331 #define STATUSF_IP10 (_ULCAST_(1) << 2)
332 #define STATUSB_IP11 3
333 #define STATUSF_IP11 (_ULCAST_(1) << 3)
334 #define STATUSB_IP12 4
335 #define STATUSF_IP12 (_ULCAST_(1) << 4)
336 #define STATUSB_IP13 5
337 #define STATUSF_IP13 (_ULCAST_(1) << 5)
338 #define STATUSB_IP14 6
339 #define STATUSF_IP14 (_ULCAST_(1) << 6)
340 #define STATUSB_IP15 7
341 #define STATUSF_IP15 (_ULCAST_(1) << 7)
342 #define ST0_CH 0x00040000
343 #define ST0_NMI 0x00080000
344 #define ST0_SR 0x00100000
345 #define ST0_TS 0x00200000
346 #define ST0_BEV 0x00400000
347 #define ST0_RE 0x02000000
348 #define ST0_FR 0x04000000
349 #define ST0_CU 0xf0000000
350 #define ST0_CU0 0x10000000
351 #define ST0_CU1 0x20000000
352 #define ST0_CU2 0x40000000
353 #define ST0_CU3 0x80000000
354 #define ST0_XX 0x80000000 /* MIPS IV naming */
355
356 /*
357 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
358 */
359 #define INTCTLB_IPFDC 23
360 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
361 #define INTCTLB_IPPCI 26
362 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
363 #define INTCTLB_IPTI 29
364 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
365
366 /*
367 * Bitfields and bit numbers in the coprocessor 0 cause register.
368 *
369 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
370 */
371 #define CAUSEB_EXCCODE 2
372 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
373 #define CAUSEB_IP 8
374 #define CAUSEF_IP (_ULCAST_(255) << 8)
375 #define CAUSEB_IP0 8
376 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
377 #define CAUSEB_IP1 9
378 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
379 #define CAUSEB_IP2 10
380 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
381 #define CAUSEB_IP3 11
382 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
383 #define CAUSEB_IP4 12
384 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
385 #define CAUSEB_IP5 13
386 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
387 #define CAUSEB_IP6 14
388 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
389 #define CAUSEB_IP7 15
390 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
391 #define CAUSEB_FDCI 21
392 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
393 #define CAUSEB_WP 22
394 #define CAUSEF_WP (_ULCAST_(1) << 22)
395 #define CAUSEB_IV 23
396 #define CAUSEF_IV (_ULCAST_(1) << 23)
397 #define CAUSEB_PCI 26
398 #define CAUSEF_PCI (_ULCAST_(1) << 26)
399 #define CAUSEB_DC 27
400 #define CAUSEF_DC (_ULCAST_(1) << 27)
401 #define CAUSEB_CE 28
402 #define CAUSEF_CE (_ULCAST_(3) << 28)
403 #define CAUSEB_TI 30
404 #define CAUSEF_TI (_ULCAST_(1) << 30)
405 #define CAUSEB_BD 31
406 #define CAUSEF_BD (_ULCAST_(1) << 31)
407
408 /*
409 * Cause.ExcCode trap codes.
410 */
411 #define EXCCODE_INT 0 /* Interrupt pending */
412 #define EXCCODE_MOD 1 /* TLB modified fault */
413 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
414 #define EXCCODE_TLBS 3 /* TLB miss on a store */
415 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
416 #define EXCCODE_ADES 5 /* Address error on a store */
417 #define EXCCODE_IBE 6 /* Bus error on an ifetch */
418 #define EXCCODE_DBE 7 /* Bus error on a load or store */
419 #define EXCCODE_SYS 8 /* System call */
420 #define EXCCODE_BP 9 /* Breakpoint */
421 #define EXCCODE_RI 10 /* Reserved instruction exception */
422 #define EXCCODE_CPU 11 /* Coprocessor unusable */
423 #define EXCCODE_OV 12 /* Arithmetic overflow */
424 #define EXCCODE_TR 13 /* Trap instruction */
425 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
426 #define EXCCODE_FPE 15 /* Floating point exception */
427 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
428 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
429 #define EXCCODE_MSADIS 21 /* MSA disabled exception */
430 #define EXCCODE_MDMX 22 /* MDMX unusable exception */
431 #define EXCCODE_WATCH 23 /* Watch address reference */
432 #define EXCCODE_MCHECK 24 /* Machine check */
433 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
434 #define EXCCODE_DSPDIS 26 /* DSP disabled exception */
435 #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
436
437 /* Implementation specific trap codes used by MIPS cores */
438 #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
439
440 /*
441 * Bits in the coprocessor 0 config register.
442 */
443 /* Generic bits. */
444 #define CONF_CM_CACHABLE_NO_WA 0
445 #define CONF_CM_CACHABLE_WA 1
446 #define CONF_CM_UNCACHED 2
447 #define CONF_CM_CACHABLE_NONCOHERENT 3
448 #define CONF_CM_CACHABLE_CE 4
449 #define CONF_CM_CACHABLE_COW 5
450 #define CONF_CM_CACHABLE_CUW 6
451 #define CONF_CM_CACHABLE_ACCELERATED 7
452 #define CONF_CM_CMASK 7
453 #define CONF_BE (_ULCAST_(1) << 15)
454
455 /* Bits common to various processors. */
456 #define CONF_CU (_ULCAST_(1) << 3)
457 #define CONF_DB (_ULCAST_(1) << 4)
458 #define CONF_IB (_ULCAST_(1) << 5)
459 #define CONF_DC (_ULCAST_(7) << 6)
460 #define CONF_IC (_ULCAST_(7) << 9)
461 #define CONF_EB (_ULCAST_(1) << 13)
462 #define CONF_EM (_ULCAST_(1) << 14)
463 #define CONF_SM (_ULCAST_(1) << 16)
464 #define CONF_SC (_ULCAST_(1) << 17)
465 #define CONF_EW (_ULCAST_(3) << 18)
466 #define CONF_EP (_ULCAST_(15)<< 24)
467 #define CONF_EC (_ULCAST_(7) << 28)
468 #define CONF_CM (_ULCAST_(1) << 31)
469
470 /* Bits specific to the R4xx0. */
471 #define R4K_CONF_SW (_ULCAST_(1) << 20)
472 #define R4K_CONF_SS (_ULCAST_(1) << 21)
473 #define R4K_CONF_SB (_ULCAST_(3) << 22)
474
475 /* Bits specific to the R5000. */
476 #define R5K_CONF_SE (_ULCAST_(1) << 12)
477 #define R5K_CONF_SS (_ULCAST_(3) << 20)
478
479 /* Bits specific to the RM7000. */
480 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
481 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
482 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
483 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
484 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
485 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
486
487 /* Bits specific to the R10000. */
488 #define R10K_CONF_DN (_ULCAST_(3) << 3)
489 #define R10K_CONF_CT (_ULCAST_(1) << 5)
490 #define R10K_CONF_PE (_ULCAST_(1) << 6)
491 #define R10K_CONF_PM (_ULCAST_(3) << 7)
492 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
493 #define R10K_CONF_SB (_ULCAST_(1) << 13)
494 #define R10K_CONF_SK (_ULCAST_(1) << 14)
495 #define R10K_CONF_SS (_ULCAST_(7) << 16)
496 #define R10K_CONF_SC (_ULCAST_(7) << 19)
497 #define R10K_CONF_DC (_ULCAST_(7) << 26)
498 #define R10K_CONF_IC (_ULCAST_(7) << 29)
499
500 /* Bits specific to the VR41xx. */
501 #define VR41_CONF_CS (_ULCAST_(1) << 12)
502 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
503 #define VR41_CONF_BP (_ULCAST_(1) << 16)
504 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
505 #define VR41_CONF_AD (_ULCAST_(1) << 23)
506
507 /* Bits specific to the R30xx. */
508 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
509 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
510 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
511 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
512 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
513 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
514 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
515 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
516 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
517
518 /* Bits specific to the TX49. */
519 #define TX49_CONF_DC (_ULCAST_(1) << 16)
520 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
521 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
522 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
523
524 /* Bits specific to the MIPS32/64 PRA. */
525 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
526 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
527 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
528 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
529 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
530 #define MIPS_CONF_M (_ULCAST_(1) << 31)
531
532 /*
533 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
534 */
535 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
536 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
537 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
538 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
539 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
540 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
541 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
542 #define MIPS_CONF1_DA_SHF 7
543 #define MIPS_CONF1_DA_SZ 3
544 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
545 #define MIPS_CONF1_DL_SHF 10
546 #define MIPS_CONF1_DL_SZ 3
547 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
548 #define MIPS_CONF1_DS_SHF 13
549 #define MIPS_CONF1_DS_SZ 3
550 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
551 #define MIPS_CONF1_IA_SHF 16
552 #define MIPS_CONF1_IA_SZ 3
553 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
554 #define MIPS_CONF1_IL_SHF 19
555 #define MIPS_CONF1_IL_SZ 3
556 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
557 #define MIPS_CONF1_IS_SHF 22
558 #define MIPS_CONF1_IS_SZ 3
559 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
560 #define MIPS_CONF1_TLBS_SHIFT (25)
561 #define MIPS_CONF1_TLBS_SIZE (6)
562 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
563
564 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
565 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
566 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
567 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
568 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
569 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
570 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
571 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
572
573 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
574 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
575 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
576 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
577 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
578 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
579 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
580 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
581 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
582 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
583 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
584 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
585 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
586 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
587 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
588 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
589 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
590 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
591 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
592 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
593 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
594 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
595 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
596 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
597 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
598 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
599 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
600
601 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
602 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
603 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
604 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
605 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
606 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
607 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
608 /* bits 10:8 in FTLB-only configurations */
609 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
610 /* bits 12:8 in VTLB-FTLB only configurations */
611 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
612 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
613 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
614 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
615 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
616 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
617 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
618 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
619 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
620 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
621 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
622
623 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
624 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
625 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
626 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
627 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
628 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
629 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
630 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
631 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
632 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
633 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
634 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
635
636 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
637 /* proAptiv FTLB on/off bit */
638 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
639 /* Loongson-3 FTLB on/off bit */
640 #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
641 /* FTLB probability bits */
642 #define MIPS_CONF6_FTLBP_SHIFT (16)
643
644 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
645
646 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
647
648 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
649 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
650 /* FTLB probability bits for R6 */
651 #define MIPS_CONF7_FTLBP_SHIFT (18)
652
653 /* WatchLo* register definitions */
654 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
655
656 /* WatchHi* register definitions */
657 #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
658 #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
659 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
660 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
661 #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
662 #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
663 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
664 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
665 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
666 #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
667 #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
668 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
669 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
670
671 /* MAAR bit definitions */
672 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
673 #define MIPS_MAAR_ADDR_SHIFT 12
674 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
675 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
676
677 /* CMGCRBase bit definitions */
678 #define MIPS_CMGCRB_BASE 11
679 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
680
681 /*
682 * Bits in the MIPS32 Memory Segmentation registers.
683 */
684 #define MIPS_SEGCFG_PA_SHIFT 9
685 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
686 #define MIPS_SEGCFG_AM_SHIFT 4
687 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
688 #define MIPS_SEGCFG_EU_SHIFT 3
689 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
690 #define MIPS_SEGCFG_C_SHIFT 0
691 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
692
693 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
694 #define MIPS_SEGCFG_USK _ULCAST_(5)
695 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
696 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
697 #define MIPS_SEGCFG_MSK _ULCAST_(2)
698 #define MIPS_SEGCFG_MK _ULCAST_(1)
699 #define MIPS_SEGCFG_UK _ULCAST_(0)
700
701 #define MIPS_PWFIELD_GDI_SHIFT 24
702 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
703 #define MIPS_PWFIELD_UDI_SHIFT 18
704 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
705 #define MIPS_PWFIELD_MDI_SHIFT 12
706 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
707 #define MIPS_PWFIELD_PTI_SHIFT 6
708 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
709 #define MIPS_PWFIELD_PTEI_SHIFT 0
710 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
711
712 #define MIPS_PWSIZE_GDW_SHIFT 24
713 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
714 #define MIPS_PWSIZE_UDW_SHIFT 18
715 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
716 #define MIPS_PWSIZE_MDW_SHIFT 12
717 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
718 #define MIPS_PWSIZE_PTW_SHIFT 6
719 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
720 #define MIPS_PWSIZE_PTEW_SHIFT 0
721 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
722
723 #define MIPS_PWCTL_PWEN_SHIFT 31
724 #define MIPS_PWCTL_PWEN_MASK 0x80000000
725 #define MIPS_PWCTL_DPH_SHIFT 7
726 #define MIPS_PWCTL_DPH_MASK 0x00000080
727 #define MIPS_PWCTL_HUGEPG_SHIFT 6
728 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
729 #define MIPS_PWCTL_PSN_SHIFT 0
730 #define MIPS_PWCTL_PSN_MASK 0x0000003f
731
732 /* CDMMBase register bit definitions */
733 #define MIPS_CDMMBASE_SIZE_SHIFT 0
734 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
735 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
736 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
737 #define MIPS_CDMMBASE_ADDR_SHIFT 11
738 #define MIPS_CDMMBASE_ADDR_START 15
739
740 /*
741 * Bitfields in the TX39 family CP0 Configuration Register 3
742 */
743 #define TX39_CONF_ICS_SHIFT 19
744 #define TX39_CONF_ICS_MASK 0x00380000
745 #define TX39_CONF_ICS_1KB 0x00000000
746 #define TX39_CONF_ICS_2KB 0x00080000
747 #define TX39_CONF_ICS_4KB 0x00100000
748 #define TX39_CONF_ICS_8KB 0x00180000
749 #define TX39_CONF_ICS_16KB 0x00200000
750
751 #define TX39_CONF_DCS_SHIFT 16
752 #define TX39_CONF_DCS_MASK 0x00070000
753 #define TX39_CONF_DCS_1KB 0x00000000
754 #define TX39_CONF_DCS_2KB 0x00010000
755 #define TX39_CONF_DCS_4KB 0x00020000
756 #define TX39_CONF_DCS_8KB 0x00030000
757 #define TX39_CONF_DCS_16KB 0x00040000
758
759 #define TX39_CONF_CWFON 0x00004000
760 #define TX39_CONF_WBON 0x00002000
761 #define TX39_CONF_RF_SHIFT 10
762 #define TX39_CONF_RF_MASK 0x00000c00
763 #define TX39_CONF_DOZE 0x00000200
764 #define TX39_CONF_HALT 0x00000100
765 #define TX39_CONF_LOCK 0x00000080
766 #define TX39_CONF_ICE 0x00000020
767 #define TX39_CONF_DCE 0x00000010
768 #define TX39_CONF_IRSIZE_SHIFT 2
769 #define TX39_CONF_IRSIZE_MASK 0x0000000c
770 #define TX39_CONF_DRSIZE_SHIFT 0
771 #define TX39_CONF_DRSIZE_MASK 0x00000003
772
773 /*
774 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
775 */
776 /* Disable Branch Target Address Cache */
777 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
778 /* Enable Branch Prediction Global History */
779 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
780 /* Disable Branch Return Cache */
781 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
782
783 /* Flush ITLB */
784 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
785 /* Flush DTLB */
786 #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
787 /* Flush VTLB */
788 #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
789 /* Flush FTLB */
790 #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
791
792 /*
793 * Coprocessor 1 (FPU) register names
794 */
795 #define CP1_REVISION $0
796 #define CP1_UFR $1
797 #define CP1_UNFR $4
798 #define CP1_FCCR $25
799 #define CP1_FEXR $26
800 #define CP1_FENR $28
801 #define CP1_STATUS $31
802
803
804 /*
805 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
806 */
807 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
808 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
809 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
810 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
811 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
812 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
813 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
814 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
815 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
816 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
817
818 /*
819 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
820 */
821 #define MIPS_FCCR_CONDX_S 0
822 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
823 #define MIPS_FCCR_COND0_S 0
824 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
825 #define MIPS_FCCR_COND1_S 1
826 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
827 #define MIPS_FCCR_COND2_S 2
828 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
829 #define MIPS_FCCR_COND3_S 3
830 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
831 #define MIPS_FCCR_COND4_S 4
832 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
833 #define MIPS_FCCR_COND5_S 5
834 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
835 #define MIPS_FCCR_COND6_S 6
836 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
837 #define MIPS_FCCR_COND7_S 7
838 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
839
840 /*
841 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
842 */
843 #define MIPS_FENR_FS_S 2
844 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
845
846 /*
847 * FPU Status Register Values
848 */
849 #define FPU_CSR_COND_S 23 /* $fcc0 */
850 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
851
852 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
853 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
854
855 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
856 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
857 #define FPU_CSR_COND1_S 25 /* $fcc1 */
858 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
859 #define FPU_CSR_COND2_S 26 /* $fcc2 */
860 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
861 #define FPU_CSR_COND3_S 27 /* $fcc3 */
862 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
863 #define FPU_CSR_COND4_S 28 /* $fcc4 */
864 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
865 #define FPU_CSR_COND5_S 29 /* $fcc5 */
866 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
867 #define FPU_CSR_COND6_S 30 /* $fcc6 */
868 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
869 #define FPU_CSR_COND7_S 31 /* $fcc7 */
870 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
871
872 /*
873 * Bits 22:20 of the FPU Status Register will be read as 0,
874 * and should be written as zero.
875 */
876 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
877
878 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
879 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
880
881 /*
882 * X the exception cause indicator
883 * E the exception enable
884 * S the sticky/flag bit
885 */
886 #define FPU_CSR_ALL_X 0x0003f000
887 #define FPU_CSR_UNI_X 0x00020000
888 #define FPU_CSR_INV_X 0x00010000
889 #define FPU_CSR_DIV_X 0x00008000
890 #define FPU_CSR_OVF_X 0x00004000
891 #define FPU_CSR_UDF_X 0x00002000
892 #define FPU_CSR_INE_X 0x00001000
893
894 #define FPU_CSR_ALL_E 0x00000f80
895 #define FPU_CSR_INV_E 0x00000800
896 #define FPU_CSR_DIV_E 0x00000400
897 #define FPU_CSR_OVF_E 0x00000200
898 #define FPU_CSR_UDF_E 0x00000100
899 #define FPU_CSR_INE_E 0x00000080
900
901 #define FPU_CSR_ALL_S 0x0000007c
902 #define FPU_CSR_INV_S 0x00000040
903 #define FPU_CSR_DIV_S 0x00000020
904 #define FPU_CSR_OVF_S 0x00000010
905 #define FPU_CSR_UDF_S 0x00000008
906 #define FPU_CSR_INE_S 0x00000004
907
908 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
909 #define FPU_CSR_RM 0x00000003
910 #define FPU_CSR_RN 0x0 /* nearest */
911 #define FPU_CSR_RZ 0x1 /* towards zero */
912 #define FPU_CSR_RU 0x2 /* towards +Infinity */
913 #define FPU_CSR_RD 0x3 /* towards -Infinity */
914
915
916 #ifndef __ASSEMBLY__
917
918 /*
919 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
920 */
921 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
922 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
923 #define get_isa16_mode(x) ((x) & 0x1)
924 #define msk_isa16_mode(x) ((x) & ~0x1)
925 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
926 #else
927 #define get_isa16_mode(x) 0
928 #define msk_isa16_mode(x) (x)
929 #define set_isa16_mode(x) do { } while(0)
930 #endif
931
932 /*
933 * microMIPS instructions can be 16-bit or 32-bit in length. This
934 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
935 */
936 static inline int mm_insn_16bit(u16 insn)
937 {
938 u16 opcode = (insn >> 10) & 0x7;
939
940 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
941 }
942
943 /*
944 * TLB Invalidate Flush
945 */
946 static inline void tlbinvf(void)
947 {
948 __asm__ __volatile__(
949 ".set push\n\t"
950 ".set noreorder\n\t"
951 ".word 0x42000004\n\t" /* tlbinvf */
952 ".set pop");
953 }
954
955
956 /*
957 * Functions to access the R10000 performance counters. These are basically
958 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
959 * performance counter number encoded into bits 1 ... 5 of the instruction.
960 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
961 * disassembler these will look like an access to sel 0 or 1.
962 */
963 #define read_r10k_perf_cntr(counter) \
964 ({ \
965 unsigned int __res; \
966 __asm__ __volatile__( \
967 "mfpc\t%0, %1" \
968 : "=r" (__res) \
969 : "i" (counter)); \
970 \
971 __res; \
972 })
973
974 #define write_r10k_perf_cntr(counter,val) \
975 do { \
976 __asm__ __volatile__( \
977 "mtpc\t%0, %1" \
978 : \
979 : "r" (val), "i" (counter)); \
980 } while (0)
981
982 #define read_r10k_perf_event(counter) \
983 ({ \
984 unsigned int __res; \
985 __asm__ __volatile__( \
986 "mfps\t%0, %1" \
987 : "=r" (__res) \
988 : "i" (counter)); \
989 \
990 __res; \
991 })
992
993 #define write_r10k_perf_cntl(counter,val) \
994 do { \
995 __asm__ __volatile__( \
996 "mtps\t%0, %1" \
997 : \
998 : "r" (val), "i" (counter)); \
999 } while (0)
1000
1001
1002 /*
1003 * Macros to access the system control coprocessor
1004 */
1005
1006 #define __read_32bit_c0_register(source, sel) \
1007 ({ unsigned int __res; \
1008 if (sel == 0) \
1009 __asm__ __volatile__( \
1010 "mfc0\t%0, " #source "\n\t" \
1011 : "=r" (__res)); \
1012 else \
1013 __asm__ __volatile__( \
1014 ".set\tmips32\n\t" \
1015 "mfc0\t%0, " #source ", " #sel "\n\t" \
1016 ".set\tmips0\n\t" \
1017 : "=r" (__res)); \
1018 __res; \
1019 })
1020
1021 #define __read_64bit_c0_register(source, sel) \
1022 ({ unsigned long long __res; \
1023 if (sizeof(unsigned long) == 4) \
1024 __res = __read_64bit_c0_split(source, sel); \
1025 else if (sel == 0) \
1026 __asm__ __volatile__( \
1027 ".set\tmips3\n\t" \
1028 "dmfc0\t%0, " #source "\n\t" \
1029 ".set\tmips0" \
1030 : "=r" (__res)); \
1031 else \
1032 __asm__ __volatile__( \
1033 ".set\tmips64\n\t" \
1034 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1035 ".set\tmips0" \
1036 : "=r" (__res)); \
1037 __res; \
1038 })
1039
1040 #define __write_32bit_c0_register(register, sel, value) \
1041 do { \
1042 if (sel == 0) \
1043 __asm__ __volatile__( \
1044 "mtc0\t%z0, " #register "\n\t" \
1045 : : "Jr" ((unsigned int)(value))); \
1046 else \
1047 __asm__ __volatile__( \
1048 ".set\tmips32\n\t" \
1049 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1050 ".set\tmips0" \
1051 : : "Jr" ((unsigned int)(value))); \
1052 } while (0)
1053
1054 #define __write_64bit_c0_register(register, sel, value) \
1055 do { \
1056 if (sizeof(unsigned long) == 4) \
1057 __write_64bit_c0_split(register, sel, value); \
1058 else if (sel == 0) \
1059 __asm__ __volatile__( \
1060 ".set\tmips3\n\t" \
1061 "dmtc0\t%z0, " #register "\n\t" \
1062 ".set\tmips0" \
1063 : : "Jr" (value)); \
1064 else \
1065 __asm__ __volatile__( \
1066 ".set\tmips64\n\t" \
1067 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1068 ".set\tmips0" \
1069 : : "Jr" (value)); \
1070 } while (0)
1071
1072 #define __read_ulong_c0_register(reg, sel) \
1073 ((sizeof(unsigned long) == 4) ? \
1074 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1075 (unsigned long) __read_64bit_c0_register(reg, sel))
1076
1077 #define __write_ulong_c0_register(reg, sel, val) \
1078 do { \
1079 if (sizeof(unsigned long) == 4) \
1080 __write_32bit_c0_register(reg, sel, val); \
1081 else \
1082 __write_64bit_c0_register(reg, sel, val); \
1083 } while (0)
1084
1085 /*
1086 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1087 */
1088 #define __read_32bit_c0_ctrl_register(source) \
1089 ({ unsigned int __res; \
1090 __asm__ __volatile__( \
1091 "cfc0\t%0, " #source "\n\t" \
1092 : "=r" (__res)); \
1093 __res; \
1094 })
1095
1096 #define __write_32bit_c0_ctrl_register(register, value) \
1097 do { \
1098 __asm__ __volatile__( \
1099 "ctc0\t%z0, " #register "\n\t" \
1100 : : "Jr" ((unsigned int)(value))); \
1101 } while (0)
1102
1103 /*
1104 * These versions are only needed for systems with more than 38 bits of
1105 * physical address space running the 32-bit kernel. That's none atm :-)
1106 */
1107 #define __read_64bit_c0_split(source, sel) \
1108 ({ \
1109 unsigned long long __val; \
1110 unsigned long __flags; \
1111 \
1112 local_irq_save(__flags); \
1113 if (sel == 0) \
1114 __asm__ __volatile__( \
1115 ".set\tmips64\n\t" \
1116 "dmfc0\t%M0, " #source "\n\t" \
1117 "dsll\t%L0, %M0, 32\n\t" \
1118 "dsra\t%M0, %M0, 32\n\t" \
1119 "dsra\t%L0, %L0, 32\n\t" \
1120 ".set\tmips0" \
1121 : "=r" (__val)); \
1122 else \
1123 __asm__ __volatile__( \
1124 ".set\tmips64\n\t" \
1125 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1126 "dsll\t%L0, %M0, 32\n\t" \
1127 "dsra\t%M0, %M0, 32\n\t" \
1128 "dsra\t%L0, %L0, 32\n\t" \
1129 ".set\tmips0" \
1130 : "=r" (__val)); \
1131 local_irq_restore(__flags); \
1132 \
1133 __val; \
1134 })
1135
1136 #define __write_64bit_c0_split(source, sel, val) \
1137 do { \
1138 unsigned long __flags; \
1139 \
1140 local_irq_save(__flags); \
1141 if (sel == 0) \
1142 __asm__ __volatile__( \
1143 ".set\tmips64\n\t" \
1144 "dsll\t%L0, %L0, 32\n\t" \
1145 "dsrl\t%L0, %L0, 32\n\t" \
1146 "dsll\t%M0, %M0, 32\n\t" \
1147 "or\t%L0, %L0, %M0\n\t" \
1148 "dmtc0\t%L0, " #source "\n\t" \
1149 ".set\tmips0" \
1150 : : "r" (val)); \
1151 else \
1152 __asm__ __volatile__( \
1153 ".set\tmips64\n\t" \
1154 "dsll\t%L0, %L0, 32\n\t" \
1155 "dsrl\t%L0, %L0, 32\n\t" \
1156 "dsll\t%M0, %M0, 32\n\t" \
1157 "or\t%L0, %L0, %M0\n\t" \
1158 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1159 ".set\tmips0" \
1160 : : "r" (val)); \
1161 local_irq_restore(__flags); \
1162 } while (0)
1163
1164 #define __readx_32bit_c0_register(source) \
1165 ({ \
1166 unsigned int __res; \
1167 \
1168 __asm__ __volatile__( \
1169 " .set push \n" \
1170 " .set noat \n" \
1171 " .set mips32r2 \n" \
1172 " .insn \n" \
1173 " # mfhc0 $1, %1 \n" \
1174 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1175 " move %0, $1 \n" \
1176 " .set pop \n" \
1177 : "=r" (__res) \
1178 : "i" (source)); \
1179 __res; \
1180 })
1181
1182 #define __writex_32bit_c0_register(register, value) \
1183 do { \
1184 __asm__ __volatile__( \
1185 " .set push \n" \
1186 " .set noat \n" \
1187 " .set mips32r2 \n" \
1188 " move $1, %0 \n" \
1189 " # mthc0 $1, %1 \n" \
1190 " .insn \n" \
1191 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1192 " .set pop \n" \
1193 : \
1194 : "r" (value), "i" (register)); \
1195 } while (0)
1196
1197 #define read_c0_index() __read_32bit_c0_register($0, 0)
1198 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1199
1200 #define read_c0_random() __read_32bit_c0_register($1, 0)
1201 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1202
1203 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1204 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1205
1206 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1207 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1208
1209 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1210 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1211
1212 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1213 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1214
1215 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1216 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1217
1218 #define read_c0_context() __read_ulong_c0_register($4, 0)
1219 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1220
1221 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1222 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1223
1224 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1225 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1226
1227 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1228 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1229
1230 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1231 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1232
1233 #define read_c0_info() __read_32bit_c0_register($7, 0)
1234
1235 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1236 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1237
1238 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1239 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1240
1241 #define read_c0_count() __read_32bit_c0_register($9, 0)
1242 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1243
1244 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1245 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1246
1247 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1248 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1249
1250 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1251 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1252
1253 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1254 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1255
1256 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1257 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1258
1259 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1260 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1261
1262 #define read_c0_status() __read_32bit_c0_register($12, 0)
1263
1264 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1265
1266 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1267 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1268
1269 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1270 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1271
1272 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1273
1274 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1275
1276 #define read_c0_config() __read_32bit_c0_register($16, 0)
1277 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1278 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1279 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1280 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1281 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1282 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1283 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1284 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1285 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1286 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1287 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1288 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1289 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1290 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1291 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1292
1293 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1294 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1295 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1296 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1297 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1298 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1299
1300 /*
1301 * The WatchLo register. There may be up to 8 of them.
1302 */
1303 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1304 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1305 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1306 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1307 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1308 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1309 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1310 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1311 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1312 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1313 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1314 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1315 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1316 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1317 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1318 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1319
1320 /*
1321 * The WatchHi register. There may be up to 8 of them.
1322 */
1323 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1324 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1325 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1326 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1327 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1328 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1329 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1330 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1331
1332 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1333 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1334 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1335 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1336 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1337 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1338 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1339 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1340
1341 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1342 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1343
1344 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1345 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1346
1347 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1348 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1349
1350 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1351 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1352
1353 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1354 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1355 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1356
1357 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1358 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1359
1360 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1361 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1362
1363 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1364 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1365
1366 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1367 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1368
1369 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1370 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1371
1372 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1373 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1374
1375 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1376 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1377
1378 /*
1379 * MIPS32 / MIPS64 performance counters
1380 */
1381 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1382 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1383 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1384 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1385 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1386 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1387 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1388 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1389 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1390 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1391 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1392 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1393 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1394 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1395 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1396 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1397 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1398 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1399 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1400 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1401 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1402 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1403 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1404 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1405
1406 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1407 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1408
1409 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1410 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1411
1412 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1413
1414 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1415 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1416
1417 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1418 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1419
1420 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1421 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1422
1423 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1424 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1425
1426 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1427 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1428
1429 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1430 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1431
1432 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1433 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1434
1435 /* MIPSR2 */
1436 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1437 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1438
1439 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1440 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1441
1442 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1443 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1444
1445 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1446 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1447
1448 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1449 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1450
1451 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1452 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1453
1454 /* MIPSR3 */
1455 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1456 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1457
1458 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1459 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1460
1461 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1462 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1463
1464 /* Hardware Page Table Walker */
1465 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1466 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1467
1468 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1469 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1470
1471 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1472 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1473
1474 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1475 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1476
1477 #define read_c0_pgd() __read_64bit_c0_register($9, 7)
1478 #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1479
1480 #define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1481 #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1482
1483 /* Cavium OCTEON (cnMIPS) */
1484 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1485 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1486
1487 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1488 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1489
1490 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1491 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1492 /*
1493 * The cacheerr registers are not standardized. On OCTEON, they are
1494 * 64 bits wide.
1495 */
1496 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1497 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1498
1499 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1500 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1501
1502 /* BMIPS3300 */
1503 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1504 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1505
1506 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1507 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1508
1509 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1510 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1511
1512 /* BMIPS43xx */
1513 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1514 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1515
1516 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1517 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1518
1519 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1520 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1521
1522 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1523 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1524
1525 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1526 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1527
1528 /* BMIPS5000 */
1529 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1530 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1531
1532 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1533 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1534
1535 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1536 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1537
1538 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1539 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1540
1541 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1542 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1543
1544 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1545 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1546
1547 /*
1548 * Macros to access the floating point coprocessor control registers
1549 */
1550 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1551 ({ \
1552 unsigned int __res; \
1553 \
1554 __asm__ __volatile__( \
1555 " .set push \n" \
1556 " .set reorder \n" \
1557 " # gas fails to assemble cfc1 for some archs, \n" \
1558 " # like Octeon. \n" \
1559 " .set mips1 \n" \
1560 " "STR(gas_hardfloat)" \n" \
1561 " cfc1 %0,"STR(source)" \n" \
1562 " .set pop \n" \
1563 : "=r" (__res)); \
1564 __res; \
1565 })
1566
1567 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1568 do { \
1569 __asm__ __volatile__( \
1570 " .set push \n" \
1571 " .set reorder \n" \
1572 " "STR(gas_hardfloat)" \n" \
1573 " ctc1 %0,"STR(dest)" \n" \
1574 " .set pop \n" \
1575 : : "r" (val)); \
1576 } while (0)
1577
1578 #ifdef GAS_HAS_SET_HARDFLOAT
1579 #define read_32bit_cp1_register(source) \
1580 _read_32bit_cp1_register(source, .set hardfloat)
1581 #define write_32bit_cp1_register(dest, val) \
1582 _write_32bit_cp1_register(dest, val, .set hardfloat)
1583 #else
1584 #define read_32bit_cp1_register(source) \
1585 _read_32bit_cp1_register(source, )
1586 #define write_32bit_cp1_register(dest, val) \
1587 _write_32bit_cp1_register(dest, val, )
1588 #endif
1589
1590 #ifdef HAVE_AS_DSP
1591 #define rddsp(mask) \
1592 ({ \
1593 unsigned int __dspctl; \
1594 \
1595 __asm__ __volatile__( \
1596 " .set push \n" \
1597 " .set dsp \n" \
1598 " rddsp %0, %x1 \n" \
1599 " .set pop \n" \
1600 : "=r" (__dspctl) \
1601 : "i" (mask)); \
1602 __dspctl; \
1603 })
1604
1605 #define wrdsp(val, mask) \
1606 do { \
1607 __asm__ __volatile__( \
1608 " .set push \n" \
1609 " .set dsp \n" \
1610 " wrdsp %0, %x1 \n" \
1611 " .set pop \n" \
1612 : \
1613 : "r" (val), "i" (mask)); \
1614 } while (0)
1615
1616 #define mflo0() \
1617 ({ \
1618 long mflo0; \
1619 __asm__( \
1620 " .set push \n" \
1621 " .set dsp \n" \
1622 " mflo %0, $ac0 \n" \
1623 " .set pop \n" \
1624 : "=r" (mflo0)); \
1625 mflo0; \
1626 })
1627
1628 #define mflo1() \
1629 ({ \
1630 long mflo1; \
1631 __asm__( \
1632 " .set push \n" \
1633 " .set dsp \n" \
1634 " mflo %0, $ac1 \n" \
1635 " .set pop \n" \
1636 : "=r" (mflo1)); \
1637 mflo1; \
1638 })
1639
1640 #define mflo2() \
1641 ({ \
1642 long mflo2; \
1643 __asm__( \
1644 " .set push \n" \
1645 " .set dsp \n" \
1646 " mflo %0, $ac2 \n" \
1647 " .set pop \n" \
1648 : "=r" (mflo2)); \
1649 mflo2; \
1650 })
1651
1652 #define mflo3() \
1653 ({ \
1654 long mflo3; \
1655 __asm__( \
1656 " .set push \n" \
1657 " .set dsp \n" \
1658 " mflo %0, $ac3 \n" \
1659 " .set pop \n" \
1660 : "=r" (mflo3)); \
1661 mflo3; \
1662 })
1663
1664 #define mfhi0() \
1665 ({ \
1666 long mfhi0; \
1667 __asm__( \
1668 " .set push \n" \
1669 " .set dsp \n" \
1670 " mfhi %0, $ac0 \n" \
1671 " .set pop \n" \
1672 : "=r" (mfhi0)); \
1673 mfhi0; \
1674 })
1675
1676 #define mfhi1() \
1677 ({ \
1678 long mfhi1; \
1679 __asm__( \
1680 " .set push \n" \
1681 " .set dsp \n" \
1682 " mfhi %0, $ac1 \n" \
1683 " .set pop \n" \
1684 : "=r" (mfhi1)); \
1685 mfhi1; \
1686 })
1687
1688 #define mfhi2() \
1689 ({ \
1690 long mfhi2; \
1691 __asm__( \
1692 " .set push \n" \
1693 " .set dsp \n" \
1694 " mfhi %0, $ac2 \n" \
1695 " .set pop \n" \
1696 : "=r" (mfhi2)); \
1697 mfhi2; \
1698 })
1699
1700 #define mfhi3() \
1701 ({ \
1702 long mfhi3; \
1703 __asm__( \
1704 " .set push \n" \
1705 " .set dsp \n" \
1706 " mfhi %0, $ac3 \n" \
1707 " .set pop \n" \
1708 : "=r" (mfhi3)); \
1709 mfhi3; \
1710 })
1711
1712
1713 #define mtlo0(x) \
1714 ({ \
1715 __asm__( \
1716 " .set push \n" \
1717 " .set dsp \n" \
1718 " mtlo %0, $ac0 \n" \
1719 " .set pop \n" \
1720 : \
1721 : "r" (x)); \
1722 })
1723
1724 #define mtlo1(x) \
1725 ({ \
1726 __asm__( \
1727 " .set push \n" \
1728 " .set dsp \n" \
1729 " mtlo %0, $ac1 \n" \
1730 " .set pop \n" \
1731 : \
1732 : "r" (x)); \
1733 })
1734
1735 #define mtlo2(x) \
1736 ({ \
1737 __asm__( \
1738 " .set push \n" \
1739 " .set dsp \n" \
1740 " mtlo %0, $ac2 \n" \
1741 " .set pop \n" \
1742 : \
1743 : "r" (x)); \
1744 })
1745
1746 #define mtlo3(x) \
1747 ({ \
1748 __asm__( \
1749 " .set push \n" \
1750 " .set dsp \n" \
1751 " mtlo %0, $ac3 \n" \
1752 " .set pop \n" \
1753 : \
1754 : "r" (x)); \
1755 })
1756
1757 #define mthi0(x) \
1758 ({ \
1759 __asm__( \
1760 " .set push \n" \
1761 " .set dsp \n" \
1762 " mthi %0, $ac0 \n" \
1763 " .set pop \n" \
1764 : \
1765 : "r" (x)); \
1766 })
1767
1768 #define mthi1(x) \
1769 ({ \
1770 __asm__( \
1771 " .set push \n" \
1772 " .set dsp \n" \
1773 " mthi %0, $ac1 \n" \
1774 " .set pop \n" \
1775 : \
1776 : "r" (x)); \
1777 })
1778
1779 #define mthi2(x) \
1780 ({ \
1781 __asm__( \
1782 " .set push \n" \
1783 " .set dsp \n" \
1784 " mthi %0, $ac2 \n" \
1785 " .set pop \n" \
1786 : \
1787 : "r" (x)); \
1788 })
1789
1790 #define mthi3(x) \
1791 ({ \
1792 __asm__( \
1793 " .set push \n" \
1794 " .set dsp \n" \
1795 " mthi %0, $ac3 \n" \
1796 " .set pop \n" \
1797 : \
1798 : "r" (x)); \
1799 })
1800
1801 #else
1802
1803 #ifdef CONFIG_CPU_MICROMIPS
1804 #define rddsp(mask) \
1805 ({ \
1806 unsigned int __res; \
1807 \
1808 __asm__ __volatile__( \
1809 " .set push \n" \
1810 " .set noat \n" \
1811 " # rddsp $1, %x1 \n" \
1812 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1813 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1814 " move %0, $1 \n" \
1815 " .set pop \n" \
1816 : "=r" (__res) \
1817 : "i" (mask)); \
1818 __res; \
1819 })
1820
1821 #define wrdsp(val, mask) \
1822 do { \
1823 __asm__ __volatile__( \
1824 " .set push \n" \
1825 " .set noat \n" \
1826 " move $1, %0 \n" \
1827 " # wrdsp $1, %x1 \n" \
1828 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1829 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1830 " .set pop \n" \
1831 : \
1832 : "r" (val), "i" (mask)); \
1833 } while (0)
1834
1835 #define _umips_dsp_mfxxx(ins) \
1836 ({ \
1837 unsigned long __treg; \
1838 \
1839 __asm__ __volatile__( \
1840 " .set push \n" \
1841 " .set noat \n" \
1842 " .hword 0x0001 \n" \
1843 " .hword %x1 \n" \
1844 " move %0, $1 \n" \
1845 " .set pop \n" \
1846 : "=r" (__treg) \
1847 : "i" (ins)); \
1848 __treg; \
1849 })
1850
1851 #define _umips_dsp_mtxxx(val, ins) \
1852 do { \
1853 __asm__ __volatile__( \
1854 " .set push \n" \
1855 " .set noat \n" \
1856 " move $1, %0 \n" \
1857 " .hword 0x0001 \n" \
1858 " .hword %x1 \n" \
1859 " .set pop \n" \
1860 : \
1861 : "r" (val), "i" (ins)); \
1862 } while (0)
1863
1864 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1865 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1866
1867 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1868 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1869
1870 #define mflo0() _umips_dsp_mflo(0)
1871 #define mflo1() _umips_dsp_mflo(1)
1872 #define mflo2() _umips_dsp_mflo(2)
1873 #define mflo3() _umips_dsp_mflo(3)
1874
1875 #define mfhi0() _umips_dsp_mfhi(0)
1876 #define mfhi1() _umips_dsp_mfhi(1)
1877 #define mfhi2() _umips_dsp_mfhi(2)
1878 #define mfhi3() _umips_dsp_mfhi(3)
1879
1880 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1881 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1882 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1883 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1884
1885 #define mthi0(x) _umips_dsp_mthi(x, 0)
1886 #define mthi1(x) _umips_dsp_mthi(x, 1)
1887 #define mthi2(x) _umips_dsp_mthi(x, 2)
1888 #define mthi3(x) _umips_dsp_mthi(x, 3)
1889
1890 #else /* !CONFIG_CPU_MICROMIPS */
1891 #define rddsp(mask) \
1892 ({ \
1893 unsigned int __res; \
1894 \
1895 __asm__ __volatile__( \
1896 " .set push \n" \
1897 " .set noat \n" \
1898 " # rddsp $1, %x1 \n" \
1899 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1900 " move %0, $1 \n" \
1901 " .set pop \n" \
1902 : "=r" (__res) \
1903 : "i" (mask)); \
1904 __res; \
1905 })
1906
1907 #define wrdsp(val, mask) \
1908 do { \
1909 __asm__ __volatile__( \
1910 " .set push \n" \
1911 " .set noat \n" \
1912 " move $1, %0 \n" \
1913 " # wrdsp $1, %x1 \n" \
1914 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1915 " .set pop \n" \
1916 : \
1917 : "r" (val), "i" (mask)); \
1918 } while (0)
1919
1920 #define _dsp_mfxxx(ins) \
1921 ({ \
1922 unsigned long __treg; \
1923 \
1924 __asm__ __volatile__( \
1925 " .set push \n" \
1926 " .set noat \n" \
1927 " .word (0x00000810 | %1) \n" \
1928 " move %0, $1 \n" \
1929 " .set pop \n" \
1930 : "=r" (__treg) \
1931 : "i" (ins)); \
1932 __treg; \
1933 })
1934
1935 #define _dsp_mtxxx(val, ins) \
1936 do { \
1937 __asm__ __volatile__( \
1938 " .set push \n" \
1939 " .set noat \n" \
1940 " move $1, %0 \n" \
1941 " .word (0x00200011 | %1) \n" \
1942 " .set pop \n" \
1943 : \
1944 : "r" (val), "i" (ins)); \
1945 } while (0)
1946
1947 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1948 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1949
1950 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1951 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1952
1953 #define mflo0() _dsp_mflo(0)
1954 #define mflo1() _dsp_mflo(1)
1955 #define mflo2() _dsp_mflo(2)
1956 #define mflo3() _dsp_mflo(3)
1957
1958 #define mfhi0() _dsp_mfhi(0)
1959 #define mfhi1() _dsp_mfhi(1)
1960 #define mfhi2() _dsp_mfhi(2)
1961 #define mfhi3() _dsp_mfhi(3)
1962
1963 #define mtlo0(x) _dsp_mtlo(x, 0)
1964 #define mtlo1(x) _dsp_mtlo(x, 1)
1965 #define mtlo2(x) _dsp_mtlo(x, 2)
1966 #define mtlo3(x) _dsp_mtlo(x, 3)
1967
1968 #define mthi0(x) _dsp_mthi(x, 0)
1969 #define mthi1(x) _dsp_mthi(x, 1)
1970 #define mthi2(x) _dsp_mthi(x, 2)
1971 #define mthi3(x) _dsp_mthi(x, 3)
1972
1973 #endif /* CONFIG_CPU_MICROMIPS */
1974 #endif
1975
1976 /*
1977 * TLB operations.
1978 *
1979 * It is responsibility of the caller to take care of any TLB hazards.
1980 */
1981 static inline void tlb_probe(void)
1982 {
1983 __asm__ __volatile__(
1984 ".set noreorder\n\t"
1985 "tlbp\n\t"
1986 ".set reorder");
1987 }
1988
1989 static inline void tlb_read(void)
1990 {
1991 #if MIPS34K_MISSED_ITLB_WAR
1992 int res = 0;
1993
1994 __asm__ __volatile__(
1995 " .set push \n"
1996 " .set noreorder \n"
1997 " .set noat \n"
1998 " .set mips32r2 \n"
1999 " .word 0x41610001 # dvpe $1 \n"
2000 " move %0, $1 \n"
2001 " ehb \n"
2002 " .set pop \n"
2003 : "=r" (res));
2004
2005 instruction_hazard();
2006 #endif
2007
2008 __asm__ __volatile__(
2009 ".set noreorder\n\t"
2010 "tlbr\n\t"
2011 ".set reorder");
2012
2013 #if MIPS34K_MISSED_ITLB_WAR
2014 if ((res & _ULCAST_(1)))
2015 __asm__ __volatile__(
2016 " .set push \n"
2017 " .set noreorder \n"
2018 " .set noat \n"
2019 " .set mips32r2 \n"
2020 " .word 0x41600021 # evpe \n"
2021 " ehb \n"
2022 " .set pop \n");
2023 #endif
2024 }
2025
2026 static inline void tlb_write_indexed(void)
2027 {
2028 __asm__ __volatile__(
2029 ".set noreorder\n\t"
2030 "tlbwi\n\t"
2031 ".set reorder");
2032 }
2033
2034 static inline void tlb_write_random(void)
2035 {
2036 __asm__ __volatile__(
2037 ".set noreorder\n\t"
2038 "tlbwr\n\t"
2039 ".set reorder");
2040 }
2041
2042 /*
2043 * Manipulate bits in a c0 register.
2044 */
2045 #define __BUILD_SET_C0(name) \
2046 static inline unsigned int \
2047 set_c0_##name(unsigned int set) \
2048 { \
2049 unsigned int res, new; \
2050 \
2051 res = read_c0_##name(); \
2052 new = res | set; \
2053 write_c0_##name(new); \
2054 \
2055 return res; \
2056 } \
2057 \
2058 static inline unsigned int \
2059 clear_c0_##name(unsigned int clear) \
2060 { \
2061 unsigned int res, new; \
2062 \
2063 res = read_c0_##name(); \
2064 new = res & ~clear; \
2065 write_c0_##name(new); \
2066 \
2067 return res; \
2068 } \
2069 \
2070 static inline unsigned int \
2071 change_c0_##name(unsigned int change, unsigned int val) \
2072 { \
2073 unsigned int res, new; \
2074 \
2075 res = read_c0_##name(); \
2076 new = res & ~change; \
2077 new |= (val & change); \
2078 write_c0_##name(new); \
2079 \
2080 return res; \
2081 }
2082
2083 __BUILD_SET_C0(status)
2084 __BUILD_SET_C0(cause)
2085 __BUILD_SET_C0(config)
2086 __BUILD_SET_C0(config5)
2087 __BUILD_SET_C0(intcontrol)
2088 __BUILD_SET_C0(intctl)
2089 __BUILD_SET_C0(srsmap)
2090 __BUILD_SET_C0(pagegrain)
2091 __BUILD_SET_C0(brcm_config_0)
2092 __BUILD_SET_C0(brcm_bus_pll)
2093 __BUILD_SET_C0(brcm_reset)
2094 __BUILD_SET_C0(brcm_cmt_intr)
2095 __BUILD_SET_C0(brcm_cmt_ctrl)
2096 __BUILD_SET_C0(brcm_config)
2097 __BUILD_SET_C0(brcm_mode)
2098
2099 /*
2100 * Return low 10 bits of ebase.
2101 * Note that under KVM (MIPSVZ) this returns vcpu id.
2102 */
2103 static inline unsigned int get_ebase_cpunum(void)
2104 {
2105 return read_c0_ebase() & 0x3ff;
2106 }
2107
2108 #endif /* !__ASSEMBLY__ */
2109
2110 #endif /* _ASM_MIPSREGS_H */
Linux kernel - Deliverables
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