120c003c124d4fd14789619862df8f3a67c59999
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _NLM_HAL_XLP_H
36 #define _NLM_HAL_XLP_H
38 #define PIC_UART_0_IRQ 17
39 #define PIC_UART_1_IRQ 18
41 #define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
42 #define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
44 #define PIC_EHCI_0_IRQ 23
45 #define PIC_EHCI_1_IRQ 24
46 #define PIC_OHCI_0_IRQ 25
47 #define PIC_OHCI_1_IRQ 26
48 #define PIC_OHCI_2_IRQ 27
49 #define PIC_OHCI_3_IRQ 28
50 #define PIC_2XX_XHCI_0_IRQ 23
51 #define PIC_2XX_XHCI_1_IRQ 24
52 #define PIC_2XX_XHCI_2_IRQ 25
54 #define PIC_MMC_IRQ 29
55 #define PIC_I2C_0_IRQ 30
56 #define PIC_I2C_1_IRQ 31
57 #define PIC_I2C_2_IRQ 32
58 #define PIC_I2C_3_IRQ 33
60 #define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
61 #define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
63 /* MSI-X with second link-level dispatch */
64 #define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
65 #define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
67 #define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
68 #define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
70 #define NLM_PIC_INDIRECT_VEC_BASE 512
71 #define NLM_GPIO_VEC_BASE 768
73 #define PIC_IRQ_BASE 8
74 #define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
75 #define PIC_IRT_LAST_IRQ 63
79 /* SMP support functions */
80 void xlp_boot_core0_siblings(void);
81 void xlp_wakeup_secondary_cpus(void);
83 void xlp_mmu_init(void);
84 void nlm_hal_init(void);
85 int xlp_get_dram_map(int n
, uint64_t *dram_map
);
88 int xlp_socdev_to_node(const struct pci_dev
*dev
);
90 /* Device tree related */
91 void xlp_early_init_devtree(void);
92 void *xlp_dt_init(void *fdtp
);
94 static inline int cpu_is_xlpii(void)
96 int chip
= read_c0_prid() & 0xff00;
98 return chip
== PRID_IMP_NETLOGIC_XLP2XX
||
99 chip
== PRID_IMP_NETLOGIC_XLP9XX
;
102 static inline int cpu_is_xlp9xx(void)
104 int chip
= read_c0_prid() & 0xff00;
106 return chip
== PRID_IMP_NETLOGIC_XLP9XX
;
108 #endif /* !__ASSEMBLY__ */
109 #endif /* _ASM_NLM_XLP_H */
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