arch/mips/include/asm/pci.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  */
   6 #ifndef _ASM_PCI_H
   7 #define _ASM_PCI_H
   8
   9 #include <linux/mm.h>
  10
  11 #ifdef __KERNEL__
  12
  13 /*
  14  * This file essentially defines the interface between board
  15  * specific PCI code and MIPS common PCI code.  Should potentially put
  16  * into include/asm/pci.h file.
  17  */
  18
  19 #include <linux/ioport.h>
  20 #include <linux/of.h>
  21
  22 /*
  23  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
  24  * multiple PCI channels may have multiple PCI host controllers or a
  25  * single controller supporting multiple channels.
  26  */
  27 struct pci_controller {
  28         struct pci_controller *next;
  29         struct pci_bus *bus;
  30         struct device_node *of_node;
  31
  32         struct pci_ops *pci_ops;
  33         struct resource *mem_resource;
  34         unsigned long mem_offset;
  35         struct resource *io_resource;
  36         unsigned long io_offset;
  37         unsigned long io_map_base;
  38         struct resource *busn_resource;
  39         unsigned long busn_offset;
  40
  41         unsigned int index;
  42         /* For compatibility with current (as of July 2003) pciutils
  43            and XFree86. Eventually will be removed. */
  44         unsigned int need_domain_info;
  45
  46         /* Optional access methods for reading/writing the bus number
  47            of the PCI controller */
  48         int (*get_busno)(void);
  49         void (*set_busno)(int busno);
  50 };
  51
  52 /*
  53  * Used by boards to register their PCI busses before the actual scanning.
  54  */
  55 extern void register_pci_controller(struct pci_controller *hose);
  56
  57 /*
  58  * board supplied pci irq fixup routine
  59  */
  60 extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  61
  62
  63 /* Can be used to override the logic in pci_scan_bus for skipping
  64    already-configured bus numbers - to be used for buggy BIOSes
  65    or architectures with incomplete PCI setup by the loader */
  66
  67 extern unsigned int pcibios_assign_all_busses(void);
  68
  69 extern unsigned long PCIBIOS_MIN_IO;
  70 extern unsigned long PCIBIOS_MIN_MEM;
  71
  72 #define PCIBIOS_MIN_CARDBUS_IO  0x4000
  73
  74 extern void pcibios_set_master(struct pci_dev *dev);
  75
  76 #define HAVE_PCI_MMAP
  77
  78 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  79         enum pci_mmap_state mmap_state, int write_combine);
  80
  81 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
  82
  83 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
  84                 const struct resource *rsrc, resource_size_t *start,
  85                 resource_size_t *end)
  86 {
  87         phys_addr_t size = resource_size(rsrc);
  88
  89         *start = fixup_bigphys_addr(rsrc->start, size);
  90         *end = rsrc->start + size;
  91 }
  92
  93 /*
  94  * Dynamic DMA mapping stuff.
  95  * MIPS has everything mapped statically.
  96  */
  97
  98 #include <linux/types.h>
  99 #include <linux/slab.h>
 100 #include <linux/scatterlist.h>
 101 #include <linux/string.h>
 102 #include <asm/io.h>
 103
 104 struct pci_dev;
 105
 106 /*
 107  * The PCI address space does equal the physical memory address space.
 108  * The networking and block device layers use this boolean for bounce
 109  * buffer decisions.
 110  */
 111 #define PCI_DMA_BUS_IS_PHYS     (1)
 112
 113 #ifdef CONFIG_PCI_DOMAINS
 114 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 115
 116 static inline int pci_proc_domain(struct pci_bus *bus)
 117 {
 118         struct pci_controller *hose = bus->sysdata;
 119         return hose->need_domain_info;
 120 }
 121 #endif /* CONFIG_PCI_DOMAINS */
 122
 123 #endif /* __KERNEL__ */
 124
 125 /* Do platform specific device initialization at pci_enable_device() time */
 126 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 127
 128 /* Chances are this interrupt is wired PC-style ...  */
 129 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 130 {
 131         return channel ? 15 : 14;
 132 }
 133
 134 extern char * (*pcibios_plat_setup)(char *str);
 135
 136 #ifdef CONFIG_OF
 137 /* this function parses memory ranges from a device node */
 138 extern void pci_load_of_ranges(struct pci_controller *hose,
 139                                struct device_node *node);
 140 #else
 141 static inline void pci_load_of_ranges(struct pci_controller *hose,
 142                                       struct device_node *node) {}
 143 #endif
 144
 145 #endif /* _ASM_PCI_H */