arch/mips/include/asm/pgtable-32.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
   7  * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
   8  */
   9 #ifndef _ASM_PGTABLE_32_H
  10 #define _ASM_PGTABLE_32_H
  11
  12 #include <asm/addrspace.h>
  13 #include <asm/page.h>
  14
  15 #include <linux/linkage.h>
  16 #include <asm/cachectl.h>
  17 #include <asm/fixmap.h>
  18
  19 #include <asm-generic/pgtable-nopmd.h>
  20
  21 /*
  22  * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
  23  *      starting at the top and working down. This is for populating the
  24  *      TLB before trap_init() puts the TLB miss handler in place. It
  25  *      should be used only for entries matching the actual page tables,
  26  *      to prevent inconsistencies.
  27  */
  28 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  29                                unsigned long entryhi, unsigned long pagemask);
  30
  31
  32 /* Basically we have the same two-level (which is the logical three level
  33  * Linux page table layout folded) page tables as the i386.  Some day
  34  * when we have proper page coloring support we can have a 1% quicker
  35  * tlb refill handling mechanism, but for now it is a bit slower but
  36  * works even with the cache aliasing problem the R4k and above have.
  37  */
  38
  39 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  40 #define PGDIR_SHIFT     (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
  41 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  42 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  43
  44 /*
  45  * Entries per page directory level: we use two-level, so
  46  * we don't really have any PUD/PMD directory physically.
  47  */
  48 #define __PGD_ORDER     (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
  49 #define PGD_ORDER       (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
  50 #define PUD_ORDER       aieeee_attempt_to_allocate_pud
  51 #define PMD_ORDER       1
  52 #define PTE_ORDER       0
  53
  54 #define PTRS_PER_PGD    (USER_PTRS_PER_PGD * 2)
  55 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
  56
  57 #define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
  58 #define FIRST_USER_ADDRESS      0
  59
  60 #define VMALLOC_START     MAP_BASE
  61
  62 #define PKMAP_BASE              (0xfe000000UL)
  63
  64 #ifdef CONFIG_HIGHMEM
  65 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
  66 #else
  67 # define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
  68 #endif
  69
  70 #ifdef CONFIG_64BIT_PHYS_ADDR
  71 #define pte_ERROR(e) \
  72         printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
  73 #else
  74 #define pte_ERROR(e) \
  75         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
  76 #endif
  77 #define pgd_ERROR(e) \
  78         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
  79
  80 extern void load_pgd(unsigned long pg_dir);
  81
  82 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
  83
  84 /*
  85  * Empty pgd/pmd entries point to the invalid_pte_table.
  86  */
  87 static inline int pmd_none(pmd_t pmd)
  88 {
  89         return pmd_val(pmd) == (unsigned long) invalid_pte_table;
  90 }
  91
  92 #define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
  93
  94 static inline int pmd_present(pmd_t pmd)
  95 {
  96         return pmd_val(pmd) != (unsigned long) invalid_pte_table;
  97 }
  98
  99 static inline void pmd_clear(pmd_t *pmdp)
 100 {
 101         pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 102 }
 103
 104 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 105 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 106 #define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
 107 static inline pte_t
 108 pfn_pte(unsigned long pfn, pgprot_t prot)
 109 {
 110         pte_t pte;
 111         pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
 112         pte.pte_low = pgprot_val(prot);
 113         return pte;
 114 }
 115
 116 #else
 117
 118 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 119
 120 #ifdef CONFIG_CPU_VR41XX
 121 #define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
 122 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 123 #else
 124 #define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
 125 #define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
 126 #endif
 127 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 128
 129 #define __pgd_offset(address)   pgd_index(address)
 130 #define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 131 #define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 132
 133 /* to find an entry in a kernel page-table-directory */
 134 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 135
 136 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 137
 138 /* to find an entry in a page-table-directory */
 139 #define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
 140
 141 /* Find an entry in the third-level page table.. */
 142 #define __pte_offset(address)                                           \
 143         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 144 #define pte_offset(dir, address)                                        \
 145         ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 146 #define pte_offset_kernel(dir, address)                                 \
 147         ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 148
 149 #define pte_offset_map(dir, address)                                    \
 150         ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 151 #define pte_unmap(pte) ((void)(pte))
 152
 153 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 154
 155 /* Swap entries must have VALID bit cleared. */
 156 #define __swp_type(x)           (((x).val >> 10) & 0x1f)
 157 #define __swp_offset(x)         ((x).val >> 15)
 158 #define __swp_entry(type,offset)        \
 159         ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
 160
 161 /*
 162  * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
 163  */
 164 #define PTE_FILE_MAX_BITS       28
 165
 166 #define pte_to_pgoff(_pte)      ((((_pte).pte >> 1 ) & 0x07) | \
 167                                  (((_pte).pte >> 2 ) & 0x38) | \
 168                                  (((_pte).pte >> 10) <<  6 ))
 169
 170 #define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x07) << 1 ) | \
 171                                            (((off) & 0x38) << 2 ) | \
 172                                            (((off) >>  6 ) << 10) | \
 173                                            _PAGE_FILE })
 174
 175 #else
 176
 177 /* Swap entries must have VALID and GLOBAL bits cleared. */
 178 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 179 #define __swp_type(x)           (((x).val >> 2) & 0x1f)
 180 #define __swp_offset(x)          ((x).val >> 7)
 181 #define __swp_entry(type,offset)        \
 182                 ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
 183 #else
 184 #define __swp_type(x)           (((x).val >> 8) & 0x1f)
 185 #define __swp_offset(x)          ((x).val >> 13)
 186 #define __swp_entry(type,offset)        \
 187                 ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
 188 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 189
 190 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 191 /*
 192  * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
 193  */
 194 #define PTE_FILE_MAX_BITS       30
 195
 196 #define pte_to_pgoff(_pte)      ((_pte).pte_high >> 2)
 197 #define pgoff_to_pte(off)       ((pte_t) { _PAGE_FILE, (off) << 2 })
 198
 199 #else
 200 /*
 201  * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
 202  */
 203 #define PTE_FILE_MAX_BITS       28
 204
 205 #define pte_to_pgoff(_pte)      ((((_pte).pte >> 1) & 0x7) | \
 206                                  (((_pte).pte >> 2) & 0x8) | \
 207                                  (((_pte).pte >> 8) <<  4))
 208
 209 #define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x7) << 1) | \
 210                                            (((off) & 0x8) << 2) | \
 211                                            (((off) >>  4) << 8) | \
 212                                            _PAGE_FILE })
 213 #endif
 214
 215 #endif
 216
 217 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 218 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
 219 #define __swp_entry_to_pte(x)   ((pte_t) { 0, (x).val })
 220 #else
 221 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 222 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 223 #endif
 224
 225 #endif /* _ASM_PGTABLE_32_H */