2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqchip/ingenic.h>
25 #include <linux/bitops.h>
27 #include <linux/debugfs.h>
28 #include <linux/seq_file.h>
30 #include <asm/mach-jz4740/base.h>
32 #define JZ4740_GPIO_BASE_A (32*0)
33 #define JZ4740_GPIO_BASE_B (32*1)
34 #define JZ4740_GPIO_BASE_C (32*2)
35 #define JZ4740_GPIO_BASE_D (32*3)
37 #define JZ4740_GPIO_NUM_A 32
38 #define JZ4740_GPIO_NUM_B 32
39 #define JZ4740_GPIO_NUM_C 31
40 #define JZ4740_GPIO_NUM_D 32
42 #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
43 #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
44 #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
45 #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
47 #define JZ_REG_GPIO_PIN 0x00
48 #define JZ_REG_GPIO_DATA 0x10
49 #define JZ_REG_GPIO_DATA_SET 0x14
50 #define JZ_REG_GPIO_DATA_CLEAR 0x18
51 #define JZ_REG_GPIO_MASK 0x20
52 #define JZ_REG_GPIO_MASK_SET 0x24
53 #define JZ_REG_GPIO_MASK_CLEAR 0x28
54 #define JZ_REG_GPIO_PULL 0x30
55 #define JZ_REG_GPIO_PULL_SET 0x34
56 #define JZ_REG_GPIO_PULL_CLEAR 0x38
57 #define JZ_REG_GPIO_FUNC 0x40
58 #define JZ_REG_GPIO_FUNC_SET 0x44
59 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
60 #define JZ_REG_GPIO_SELECT 0x50
61 #define JZ_REG_GPIO_SELECT_SET 0x54
62 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
63 #define JZ_REG_GPIO_DIRECTION 0x60
64 #define JZ_REG_GPIO_DIRECTION_SET 0x64
65 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
66 #define JZ_REG_GPIO_TRIGGER 0x70
67 #define JZ_REG_GPIO_TRIGGER_SET 0x74
68 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
69 #define JZ_REG_GPIO_FLAG 0x80
70 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
72 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
73 #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
74 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
78 unsigned int irq_base
;
79 uint32_t edge_trigger_both
;
83 struct gpio_chip gpio_chip
;
86 static struct jz_gpio_chip jz4740_gpio_chips
[];
88 static inline struct jz_gpio_chip
*gpio_to_jz_gpio_chip(unsigned int gpio
)
90 return &jz4740_gpio_chips
[gpio
>> 5];
93 static inline struct jz_gpio_chip
*gpio_chip_to_jz_gpio_chip(struct gpio_chip
*gpio_chip
)
95 return container_of(gpio_chip
, struct jz_gpio_chip
, gpio_chip
);
98 static inline struct jz_gpio_chip
*irq_to_jz_gpio_chip(struct irq_data
*data
)
100 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(data
);
104 static inline void jz_gpio_write_bit(unsigned int gpio
, unsigned int reg
)
106 writel(GPIO_TO_BIT(gpio
), GPIO_TO_REG(gpio
, reg
));
109 int jz_gpio_set_function(int gpio
, enum jz_gpio_function function
)
111 if (function
== JZ_GPIO_FUNC_NONE
) {
112 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_FUNC_CLEAR
);
113 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_SELECT_CLEAR
);
114 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_TRIGGER_CLEAR
);
116 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_FUNC_SET
);
117 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_TRIGGER_CLEAR
);
120 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_SELECT_CLEAR
);
123 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_TRIGGER_SET
);
124 case JZ_GPIO_FUNC2
: /* Falltrough */
125 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_SELECT_SET
);
135 EXPORT_SYMBOL_GPL(jz_gpio_set_function
);
137 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request
*request
, size_t num
)
142 for (i
= 0; i
< num
; ++i
, ++request
) {
143 ret
= gpio_request(request
->gpio
, request
->name
);
146 jz_gpio_set_function(request
->gpio
, request
->function
);
152 for (--request
; i
> 0; --i
, --request
) {
153 gpio_free(request
->gpio
);
154 jz_gpio_set_function(request
->gpio
, JZ_GPIO_FUNC_NONE
);
159 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request
);
161 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request
*request
, size_t num
)
165 for (i
= 0; i
< num
; ++i
, ++request
) {
166 gpio_free(request
->gpio
);
167 jz_gpio_set_function(request
->gpio
, JZ_GPIO_FUNC_NONE
);
171 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free
);
173 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request
*request
, size_t num
)
177 for (i
= 0; i
< num
; ++i
, ++request
) {
178 jz_gpio_set_function(request
->gpio
, JZ_GPIO_FUNC_NONE
);
179 jz_gpio_write_bit(request
->gpio
, JZ_REG_GPIO_DIRECTION_CLEAR
);
180 jz_gpio_write_bit(request
->gpio
, JZ_REG_GPIO_PULL_SET
);
183 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend
);
185 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request
*request
, size_t num
)
189 for (i
= 0; i
< num
; ++i
, ++request
)
190 jz_gpio_set_function(request
->gpio
, request
->function
);
192 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume
);
194 void jz_gpio_enable_pullup(unsigned gpio
)
196 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_PULL_CLEAR
);
198 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup
);
200 void jz_gpio_disable_pullup(unsigned gpio
)
202 jz_gpio_write_bit(gpio
, JZ_REG_GPIO_PULL_SET
);
204 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup
);
206 static int jz_gpio_get_value(struct gpio_chip
*chip
, unsigned gpio
)
208 return !!(readl(CHIP_TO_REG(chip
, JZ_REG_GPIO_PIN
)) & BIT(gpio
));
211 static void jz_gpio_set_value(struct gpio_chip
*chip
, unsigned gpio
, int value
)
213 uint32_t __iomem
*reg
= CHIP_TO_REG(chip
, JZ_REG_GPIO_DATA_SET
);
215 writel(BIT(gpio
), reg
);
218 static int jz_gpio_direction_output(struct gpio_chip
*chip
, unsigned gpio
,
221 writel(BIT(gpio
), CHIP_TO_REG(chip
, JZ_REG_GPIO_DIRECTION_SET
));
222 jz_gpio_set_value(chip
, gpio
, value
);
227 static int jz_gpio_direction_input(struct gpio_chip
*chip
, unsigned gpio
)
229 writel(BIT(gpio
), CHIP_TO_REG(chip
, JZ_REG_GPIO_DIRECTION_CLEAR
));
234 static int jz_gpio_to_irq(struct gpio_chip
*chip
, unsigned gpio
)
236 struct jz_gpio_chip
*jz_gpio
= gpio_chip_to_jz_gpio_chip(chip
);
238 return jz_gpio
->irq_base
+ gpio
;
241 int jz_gpio_port_direction_input(int port
, uint32_t mask
)
243 writel(mask
, GPIO_TO_REG(port
, JZ_REG_GPIO_DIRECTION_CLEAR
));
247 EXPORT_SYMBOL(jz_gpio_port_direction_input
);
249 int jz_gpio_port_direction_output(int port
, uint32_t mask
)
251 writel(mask
, GPIO_TO_REG(port
, JZ_REG_GPIO_DIRECTION_SET
));
255 EXPORT_SYMBOL(jz_gpio_port_direction_output
);
257 void jz_gpio_port_set_value(int port
, uint32_t value
, uint32_t mask
)
259 writel(~value
& mask
, GPIO_TO_REG(port
, JZ_REG_GPIO_DATA_CLEAR
));
260 writel(value
& mask
, GPIO_TO_REG(port
, JZ_REG_GPIO_DATA_SET
));
262 EXPORT_SYMBOL(jz_gpio_port_set_value
);
264 uint32_t jz_gpio_port_get_value(int port
, uint32_t mask
)
266 uint32_t value
= readl(GPIO_TO_REG(port
, JZ_REG_GPIO_PIN
));
270 EXPORT_SYMBOL(jz_gpio_port_get_value
);
272 #define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
274 static void jz_gpio_check_trigger_both(struct jz_gpio_chip
*chip
, unsigned int irq
)
278 uint32_t mask
= IRQ_TO_BIT(irq
);
280 if (!(chip
->edge_trigger_both
& mask
))
285 value
= readl(chip
->base
+ JZ_REG_GPIO_PIN
);
287 reg
+= JZ_REG_GPIO_DIRECTION_CLEAR
;
289 reg
+= JZ_REG_GPIO_DIRECTION_SET
;
294 static void jz_gpio_irq_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
297 unsigned int gpio_irq
;
298 struct jz_gpio_chip
*chip
= irq_desc_get_handler_data(desc
);
300 flag
= readl(chip
->base
+ JZ_REG_GPIO_FLAG
);
304 gpio_irq
= chip
->irq_base
+ __fls(flag
);
306 jz_gpio_check_trigger_both(chip
, gpio_irq
);
308 generic_handle_irq(gpio_irq
);
311 static inline void jz_gpio_set_irq_bit(struct irq_data
*data
, unsigned int reg
)
313 struct jz_gpio_chip
*chip
= irq_to_jz_gpio_chip(data
);
314 writel(IRQ_TO_BIT(data
->irq
), chip
->base
+ reg
);
317 static void jz_gpio_irq_unmask(struct irq_data
*data
)
319 struct jz_gpio_chip
*chip
= irq_to_jz_gpio_chip(data
);
321 jz_gpio_check_trigger_both(chip
, data
->irq
);
322 irq_gc_unmask_enable_reg(data
);
325 /* TODO: Check if function is gpio */
326 static unsigned int jz_gpio_irq_startup(struct irq_data
*data
)
328 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_SELECT_SET
);
329 jz_gpio_irq_unmask(data
);
333 static void jz_gpio_irq_shutdown(struct irq_data
*data
)
335 irq_gc_mask_disable_reg(data
);
337 /* Set direction to input */
338 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_DIRECTION_CLEAR
);
339 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_SELECT_CLEAR
);
342 static int jz_gpio_irq_set_type(struct irq_data
*data
, unsigned int flow_type
)
344 struct jz_gpio_chip
*chip
= irq_to_jz_gpio_chip(data
);
345 unsigned int irq
= data
->irq
;
347 if (flow_type
== IRQ_TYPE_EDGE_BOTH
) {
348 uint32_t value
= readl(chip
->base
+ JZ_REG_GPIO_PIN
);
349 if (value
& IRQ_TO_BIT(irq
))
350 flow_type
= IRQ_TYPE_EDGE_FALLING
;
352 flow_type
= IRQ_TYPE_EDGE_RISING
;
353 chip
->edge_trigger_both
|= IRQ_TO_BIT(irq
);
355 chip
->edge_trigger_both
&= ~IRQ_TO_BIT(irq
);
359 case IRQ_TYPE_EDGE_RISING
:
360 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_DIRECTION_SET
);
361 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_TRIGGER_SET
);
363 case IRQ_TYPE_EDGE_FALLING
:
364 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_DIRECTION_CLEAR
);
365 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_TRIGGER_SET
);
367 case IRQ_TYPE_LEVEL_HIGH
:
368 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_DIRECTION_SET
);
369 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_TRIGGER_CLEAR
);
371 case IRQ_TYPE_LEVEL_LOW
:
372 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_DIRECTION_CLEAR
);
373 jz_gpio_set_irq_bit(data
, JZ_REG_GPIO_TRIGGER_CLEAR
);
382 static int jz_gpio_irq_set_wake(struct irq_data
*data
, unsigned int on
)
384 struct jz_gpio_chip
*chip
= irq_to_jz_gpio_chip(data
);
386 irq_gc_set_wake(data
, on
);
387 irq_set_irq_wake(chip
->irq
, on
);
392 #define JZ4740_GPIO_CHIP(_bank) { \
393 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
395 .label = "Bank " # _bank, \
396 .owner = THIS_MODULE, \
397 .set = jz_gpio_set_value, \
398 .get = jz_gpio_get_value, \
399 .direction_output = jz_gpio_direction_output, \
400 .direction_input = jz_gpio_direction_input, \
401 .to_irq = jz_gpio_to_irq, \
402 .base = JZ4740_GPIO_BASE_ ## _bank, \
403 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
407 static struct jz_gpio_chip jz4740_gpio_chips
[] = {
414 static void jz4740_gpio_chip_init(struct jz_gpio_chip
*chip
, unsigned int id
)
416 struct irq_chip_generic
*gc
;
417 struct irq_chip_type
*ct
;
419 chip
->base
= ioremap(JZ4740_GPIO_BASE_ADDR
+ (id
* 0x100), 0x100);
421 chip
->irq
= JZ4740_IRQ_INTC_GPIO(id
);
422 irq_set_chained_handler_and_data(chip
->irq
,
423 jz_gpio_irq_demux_handler
, chip
);
425 gc
= irq_alloc_generic_chip(chip
->gpio_chip
.label
, 1, chip
->irq_base
,
426 chip
->base
, handle_level_irq
);
428 gc
->wake_enabled
= IRQ_MSK(chip
->gpio_chip
.ngpio
);
432 ct
->regs
.enable
= JZ_REG_GPIO_MASK_CLEAR
;
433 ct
->regs
.disable
= JZ_REG_GPIO_MASK_SET
;
434 ct
->regs
.ack
= JZ_REG_GPIO_FLAG_CLEAR
;
436 ct
->chip
.name
= "GPIO";
437 ct
->chip
.irq_mask
= irq_gc_mask_disable_reg
;
438 ct
->chip
.irq_unmask
= jz_gpio_irq_unmask
;
439 ct
->chip
.irq_ack
= irq_gc_ack_set_bit
;
440 ct
->chip
.irq_suspend
= ingenic_intc_irq_suspend
;
441 ct
->chip
.irq_resume
= ingenic_intc_irq_resume
;
442 ct
->chip
.irq_startup
= jz_gpio_irq_startup
;
443 ct
->chip
.irq_shutdown
= jz_gpio_irq_shutdown
;
444 ct
->chip
.irq_set_type
= jz_gpio_irq_set_type
;
445 ct
->chip
.irq_set_wake
= jz_gpio_irq_set_wake
;
446 ct
->chip
.flags
= IRQCHIP_SET_TYPE_MASKED
;
448 irq_setup_generic_chip(gc
, IRQ_MSK(chip
->gpio_chip
.ngpio
),
449 IRQ_GC_INIT_NESTED_LOCK
, 0, IRQ_NOPROBE
| IRQ_LEVEL
);
451 gpiochip_add(&chip
->gpio_chip
);
454 static int __init
jz4740_gpio_init(void)
458 for (i
= 0; i
< ARRAY_SIZE(jz4740_gpio_chips
); ++i
)
459 jz4740_gpio_chip_init(&jz4740_gpio_chips
[i
], i
);
461 printk(KERN_INFO
"JZ4740 GPIO initialized\n");
465 arch_initcall(jz4740_gpio_init
);
467 #ifdef CONFIG_DEBUG_FS
469 static inline void gpio_seq_reg(struct seq_file
*s
, struct jz_gpio_chip
*chip
,
470 const char *name
, unsigned int reg
)
472 seq_printf(s
, "\t%s: %08x\n", name
, readl(chip
->base
+ reg
));
475 static int gpio_regs_show(struct seq_file
*s
, void *unused
)
477 struct jz_gpio_chip
*chip
= jz4740_gpio_chips
;
480 for (i
= 0; i
< ARRAY_SIZE(jz4740_gpio_chips
); ++i
, ++chip
) {
481 seq_printf(s
, "==GPIO %d==\n", i
);
482 gpio_seq_reg(s
, chip
, "Pin", JZ_REG_GPIO_PIN
);
483 gpio_seq_reg(s
, chip
, "Data", JZ_REG_GPIO_DATA
);
484 gpio_seq_reg(s
, chip
, "Mask", JZ_REG_GPIO_MASK
);
485 gpio_seq_reg(s
, chip
, "Pull", JZ_REG_GPIO_PULL
);
486 gpio_seq_reg(s
, chip
, "Func", JZ_REG_GPIO_FUNC
);
487 gpio_seq_reg(s
, chip
, "Select", JZ_REG_GPIO_SELECT
);
488 gpio_seq_reg(s
, chip
, "Direction", JZ_REG_GPIO_DIRECTION
);
489 gpio_seq_reg(s
, chip
, "Trigger", JZ_REG_GPIO_TRIGGER
);
490 gpio_seq_reg(s
, chip
, "Flag", JZ_REG_GPIO_FLAG
);
496 static int gpio_regs_open(struct inode
*inode
, struct file
*file
)
498 return single_open(file
, gpio_regs_show
, NULL
);
501 static const struct file_operations gpio_regs_operations
= {
502 .open
= gpio_regs_open
,
505 .release
= single_release
,
508 static int __init
gpio_debugfs_init(void)
510 (void) debugfs_create_file("jz_regs_gpio", S_IFREG
| S_IRUGO
,
511 NULL
, NULL
, &gpio_regs_operations
);
514 subsys_initcall(gpio_debugfs_init
);