2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/signal.h>
12 #include <linux/module.h>
13 #include <asm/branch.h>
15 #include <asm/cpu-features.h>
17 #include <asm/fpu_emulator.h>
19 #include <asm/ptrace.h>
20 #include <asm/uaccess.h>
23 * Calculate and return exception PC in case of branch delay slot
24 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
26 int __isa_exception_epc(struct pt_regs
*regs
)
29 long epc
= regs
->cp0_epc
;
31 /* Calculate exception PC in branch delay slot. */
32 if (__get_user(inst
, (u16 __user
*) msk_isa16_mode(epc
))) {
33 /* This should never happen because delay slot was checked. */
34 force_sig(SIGSEGV
, current
);
38 if (((union mips16e_instruction
)inst
).ri
.opcode
43 } else if (mm_insn_16bit(inst
))
51 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
52 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
54 int __mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
55 unsigned long *contpc
)
57 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
65 switch (insn
.mm_i_format
.opcode
) {
67 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
69 switch (insn
.mm_i_format
.simmediate
>>
70 MM_POOL32A_MINOR_SHIFT
) {
75 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
76 regs
->regs
[insn
.mm_i_format
.rt
] =
80 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
86 switch (insn
.mm_i_format
.rt
) {
89 regs
->regs
[31] = regs
->cp0_epc
+
94 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
95 *contpc
= regs
->cp0_epc
+
97 (insn
.mm_i_format
.simmediate
<< 1);
99 *contpc
= regs
->cp0_epc
+
101 dec_insn
.next_pc_inc
;
105 regs
->regs
[31] = regs
->cp0_epc
+
107 dec_insn
.next_pc_inc
;
110 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
111 *contpc
= regs
->cp0_epc
+
113 (insn
.mm_i_format
.simmediate
<< 1);
115 *contpc
= regs
->cp0_epc
+
117 dec_insn
.next_pc_inc
;
120 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
121 *contpc
= regs
->cp0_epc
+
123 (insn
.mm_i_format
.simmediate
<< 1);
125 *contpc
= regs
->cp0_epc
+
127 dec_insn
.next_pc_inc
;
130 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
131 *contpc
= regs
->cp0_epc
+
133 (insn
.mm_i_format
.simmediate
<< 1);
135 *contpc
= regs
->cp0_epc
+
137 dec_insn
.next_pc_inc
;
147 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
149 fcr31
= current
->thread
.fpu
.fcr31
;
155 bit
= (insn
.mm_i_format
.rs
>> 2);
158 if (fcr31
& (1 << bit
))
159 *contpc
= regs
->cp0_epc
+
161 (insn
.mm_i_format
.simmediate
<< 1);
163 *contpc
= regs
->cp0_epc
+
164 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
169 switch (insn
.mm_i_format
.rt
) {
172 regs
->regs
[31] = regs
->cp0_epc
+
173 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
176 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
181 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
182 *contpc
= regs
->cp0_epc
+
184 (insn
.mm_b1_format
.simmediate
<< 1);
186 *contpc
= regs
->cp0_epc
+
187 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
190 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
191 *contpc
= regs
->cp0_epc
+
193 (insn
.mm_b1_format
.simmediate
<< 1);
195 *contpc
= regs
->cp0_epc
+
196 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
199 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
200 (insn
.mm_b0_format
.simmediate
<< 1);
203 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
204 regs
->regs
[insn
.mm_i_format
.rt
])
205 *contpc
= regs
->cp0_epc
+
207 (insn
.mm_i_format
.simmediate
<< 1);
209 *contpc
= regs
->cp0_epc
+
211 dec_insn
.next_pc_inc
;
214 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
215 regs
->regs
[insn
.mm_i_format
.rt
])
216 *contpc
= regs
->cp0_epc
+
218 (insn
.mm_i_format
.simmediate
<< 1);
220 *contpc
= regs
->cp0_epc
+
221 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
224 regs
->regs
[31] = regs
->cp0_epc
+
225 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
226 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
229 *contpc
|= (insn
.j_format
.target
<< 2);
233 regs
->regs
[31] = regs
->cp0_epc
+
234 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
237 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
240 *contpc
|= (insn
.j_format
.target
<< 1);
241 set_isa16_mode(*contpc
);
248 * Compute return address and emulate branch in microMIPS mode after an
249 * exception only. It does not handle compact branches/jumps and cannot
250 * be used in interrupt context. (Compact branches/jumps do not cause
253 int __microMIPS_compute_return_epc(struct pt_regs
*regs
)
258 unsigned long contpc
;
259 struct mm_decoded_insn mminsn
= { 0 };
261 mminsn
.micro_mips_mode
= 1;
263 /* This load never faults. */
264 pc16
= (unsigned short __user
*)msk_isa16_mode(regs
->cp0_epc
);
265 __get_user(halfword
, pc16
);
267 contpc
= regs
->cp0_epc
+ 2;
268 word
= ((unsigned int)halfword
<< 16);
271 if (!mm_insn_16bit(halfword
)) {
272 __get_user(halfword
, pc16
);
274 contpc
= regs
->cp0_epc
+ 4;
280 if (get_user(halfword
, pc16
))
282 mminsn
.next_pc_inc
= 2;
283 word
= ((unsigned int)halfword
<< 16);
285 if (!mm_insn_16bit(halfword
)) {
287 if (get_user(halfword
, pc16
))
289 mminsn
.next_pc_inc
= 4;
292 mminsn
.next_insn
= word
;
294 mm_isBranchInstr(regs
, mminsn
, &contpc
);
296 regs
->cp0_epc
= contpc
;
301 force_sig(SIGSEGV
, current
);
306 * Compute return address and emulate branch in MIPS16e mode after an
307 * exception only. It does not handle compact branches/jumps and cannot
308 * be used in interrupt context. (Compact branches/jumps do not cause
311 int __MIPS16e_compute_return_epc(struct pt_regs
*regs
)
314 union mips16e_instruction inst
;
321 /* Read the instruction. */
322 addr
= (u16 __user
*)msk_isa16_mode(epc
);
323 if (__get_user(inst
.full
, addr
)) {
324 force_sig(SIGSEGV
, current
);
328 switch (inst
.ri
.opcode
) {
329 case MIPS16e_extend_op
:
334 * JAL and JALX in MIPS16e mode
338 if (__get_user(inst2
, addr
)) {
339 force_sig(SIGSEGV
, current
);
342 fullinst
= ((unsigned)inst
.full
<< 16) | inst2
;
343 regs
->regs
[31] = epc
+ 6;
348 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
350 * ......TARGET[15:0].................TARGET[20:16]...........
351 * ......TARGET[25:21]
354 ((fullinst
& 0xffff) << 2) | ((fullinst
& 0x3e00000) >> 3) |
355 ((fullinst
& 0x1f0000) << 7);
357 set_isa16_mode(epc
); /* Set ISA mode bit. */
365 if (inst
.rr
.func
== MIPS16e_jr_func
) {
368 regs
->cp0_epc
= regs
->regs
[31];
371 regs
->regs
[reg16to32
[inst
.rr
.rx
]];
375 regs
->regs
[31] = epc
+ 2;
377 regs
->regs
[31] = epc
+ 4;
385 * All other cases have no branch delay slot and are 16-bits.
386 * Branches do not cause an exception.
394 * __compute_return_epc_for_insn - Computes the return address and do emulate
395 * branch simulation, if required.
397 * @regs: Pointer to pt_regs
398 * @insn: branch instruction to decode
399 * @returns: -EFAULT on error and forces SIGBUS, and on success
400 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
401 * evaluating the branch.
403 int __compute_return_epc_for_insn(struct pt_regs
*regs
,
404 union mips_instruction insn
)
406 unsigned int bit
, fcr31
, dspcontrol
;
407 long epc
= regs
->cp0_epc
;
410 switch (insn
.i_format
.opcode
) {
412 * jr and jalr are in r_format format.
415 switch (insn
.r_format
.func
) {
417 regs
->regs
[insn
.r_format
.rd
] = epc
+ 8;
420 regs
->cp0_epc
= regs
->regs
[insn
.r_format
.rs
];
426 * This group contains:
427 * bltz_op, bgez_op, bltzl_op, bgezl_op,
428 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
431 switch (insn
.i_format
.rt
) {
434 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
435 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
436 if (insn
.i_format
.rt
== bltzl_op
)
437 ret
= BRANCH_LIKELY_TAKEN
;
445 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
446 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
447 if (insn
.i_format
.rt
== bgezl_op
)
448 ret
= BRANCH_LIKELY_TAKEN
;
456 regs
->regs
[31] = epc
+ 8;
457 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0) {
458 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
459 if (insn
.i_format
.rt
== bltzall_op
)
460 ret
= BRANCH_LIKELY_TAKEN
;
468 regs
->regs
[31] = epc
+ 8;
469 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0) {
470 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
471 if (insn
.i_format
.rt
== bgezall_op
)
472 ret
= BRANCH_LIKELY_TAKEN
;
482 dspcontrol
= rddsp(0x01);
484 if (dspcontrol
>= 32) {
485 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
494 * These are unconditional and in j_format.
497 regs
->regs
[31] = regs
->cp0_epc
+ 8;
502 epc
|= (insn
.j_format
.target
<< 2);
504 if (insn
.i_format
.opcode
== jalx_op
)
505 set_isa16_mode(regs
->cp0_epc
);
509 * These are conditional and in i_format.
513 if (regs
->regs
[insn
.i_format
.rs
] ==
514 regs
->regs
[insn
.i_format
.rt
]) {
515 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
516 if (insn
.i_format
.opcode
== beql_op
)
517 ret
= BRANCH_LIKELY_TAKEN
;
525 if (regs
->regs
[insn
.i_format
.rs
] !=
526 regs
->regs
[insn
.i_format
.rt
]) {
527 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
528 if (insn
.i_format
.opcode
== bnel_op
)
529 ret
= BRANCH_LIKELY_TAKEN
;
535 case blez_op
: /* not really i_format */
537 /* rt field assumed to be zero */
538 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0) {
539 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
540 if (insn
.i_format
.opcode
== blezl_op
)
541 ret
= BRANCH_LIKELY_TAKEN
;
549 /* rt field assumed to be zero */
550 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0) {
551 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
552 if (insn
.i_format
.opcode
== bgtzl_op
)
553 ret
= BRANCH_LIKELY_TAKEN
;
560 * And now the FPA/cp1 branch instructions.
565 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
567 fcr31
= current
->thread
.fpu
.fcr31
;
570 bit
= (insn
.i_format
.rt
>> 2);
573 switch (insn
.i_format
.rt
& 3) {
576 if (~fcr31
& (1 << bit
)) {
577 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
578 if (insn
.i_format
.rt
== 2)
579 ret
= BRANCH_LIKELY_TAKEN
;
587 if (fcr31
& (1 << bit
)) {
588 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
589 if (insn
.i_format
.rt
== 3)
590 ret
= BRANCH_LIKELY_TAKEN
;
597 #ifdef CONFIG_CPU_CAVIUM_OCTEON
598 case lwc2_op
: /* This is bbit0 on Octeon */
599 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
601 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
606 case ldc2_op
: /* This is bbit032 on Octeon */
607 if ((regs
->regs
[insn
.i_format
.rs
] &
608 (1ull<<(insn
.i_format
.rt
+32))) == 0)
609 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
614 case swc2_op
: /* This is bbit1 on Octeon */
615 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
616 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
621 case sdc2_op
: /* This is bbit132 on Octeon */
622 if (regs
->regs
[insn
.i_format
.rs
] &
623 (1ull<<(insn
.i_format
.rt
+32)))
624 epc
= epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
635 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current
->comm
);
636 force_sig(SIGBUS
, current
);
639 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn
);
641 int __compute_return_epc(struct pt_regs
*regs
)
643 unsigned int __user
*addr
;
645 union mips_instruction insn
;
652 * Read the instruction
654 addr
= (unsigned int __user
*) epc
;
655 if (__get_user(insn
.word
, addr
)) {
656 force_sig(SIGSEGV
, current
);
660 return __compute_return_epc_for_insn(regs
, insn
);
663 printk("%s: unaligned epc - sending SIGBUS.\n", current
->comm
);
664 force_sig(SIGBUS
, current
);