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MIPS: Probe the P6600 core
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37
38 /*
39 * Get the FPU Implementation/Revision.
40 */
41 static inline unsigned long cpu_get_fpu_id(void)
42 {
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50 }
51
52 /*
53 * Check if the CPU has an external FPU.
54 */
55 static inline int __cpu_has_fpu(void)
56 {
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58 }
59
60 static inline unsigned long cpu_get_msa_id(void)
61 {
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71 }
72
73 /*
74 * Determine the FCSR mask for FPU hardware.
75 */
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77 {
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99 }
100
101 /*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106 {
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151 }
152
153 /*
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159 /*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
164 */
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166 {
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
194 }
195 }
196
197 /*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202 {
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221 }
222
223 /*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232 static int __init ieee754_setup(char *s)
233 {
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252 }
253
254 early_param("ieee754", ieee754_setup);
255
256 /*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260 {
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
273 c->fpu_id = value;
274 }
275
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31;
278
279 /*
280 * Set options for FPU hardware.
281 */
282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283 {
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
297 cpu_set_fpu_2008(c);
298 cpu_set_nan_2008(c);
299 }
300
301 /*
302 * Set options for the FPU emulator.
303 */
304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305 {
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
309 cpu_set_nofpu_2008(c);
310 cpu_set_nan_2008(c);
311 cpu_set_nofpu_id(c);
312 }
313
314 static int mips_fpu_disabled;
315
316 static int __init fpu_disable(char *s)
317 {
318 cpu_set_nofpu_opts(&boot_cpu_data);
319 mips_fpu_disabled = 1;
320
321 return 1;
322 }
323
324 __setup("nofpu", fpu_disable);
325
326 int mips_dsp_disabled;
327
328 static int __init dsp_disable(char *s)
329 {
330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
331 mips_dsp_disabled = 1;
332
333 return 1;
334 }
335
336 __setup("nodsp", dsp_disable);
337
338 static int mips_htw_disabled;
339
340 static int __init htw_disable(char *s)
341 {
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348 }
349
350 __setup("nohtw", htw_disable);
351
352 static int mips_ftlb_disabled;
353 static int mips_has_ftlb_configured;
354
355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
356
357 static int __init ftlb_disable(char *s)
358 {
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407 }
408
409 __setup("noftlb", ftlb_disable);
410
411
412 static inline void check_errata(void)
413 {
414 struct cpuinfo_mips *c = &current_cpu_data;
415
416 switch (current_cpu_type()) {
417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429 }
430
431 void __init check_bugs32(void)
432 {
433 check_errata();
434 }
435
436 /*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441 static inline int cpu_has_confreg(void)
442 {
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453 #else
454 return 0;
455 #endif
456 }
457
458 static inline void set_elf_platform(int cpu, const char *plat)
459 {
460 if (cpu == 0)
461 __elf_platform = plat;
462 }
463
464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465 {
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL);
468 back_to_back_c0_hazard();
469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
470 #endif
471 }
472
473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
474 {
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
486 break;
487
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
501 break;
502 }
503 }
504
505 static char unknown_isa[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
507
508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509 {
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532 }
533
534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
535 {
536 unsigned int config;
537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
542 case CPU_P6600:
543 /* proAptiv & related cores use Config6 to enable the FTLB */
544 config = read_c0_config6();
545 /* Clear the old probability value */
546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
547 if (enable)
548 /* Enable FTLB */
549 write_c0_config6(config |
550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
553 else
554 /* Disable FTLB */
555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
564 break;
565 default:
566 return 1;
567 }
568
569 return 0;
570 }
571
572 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
573 {
574 unsigned int config0;
575 int isa, mt;
576
577 config0 = read_c0_config();
578
579 /*
580 * Look for Standard TLB or Dual VTLB and FTLB
581 */
582 mt = config0 & MIPS_CONF_MT;
583 if (mt == MIPS_CONF_MT_TLB)
584 c->options |= MIPS_CPU_TLB;
585 else if (mt == MIPS_CONF_MT_FTLB)
586 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
587
588 isa = (config0 & MIPS_CONF_AT) >> 13;
589 switch (isa) {
590 case 0:
591 switch ((config0 & MIPS_CONF_AR) >> 10) {
592 case 0:
593 set_isa(c, MIPS_CPU_ISA_M32R1);
594 break;
595 case 1:
596 set_isa(c, MIPS_CPU_ISA_M32R2);
597 break;
598 case 2:
599 set_isa(c, MIPS_CPU_ISA_M32R6);
600 break;
601 default:
602 goto unknown;
603 }
604 break;
605 case 2:
606 switch ((config0 & MIPS_CONF_AR) >> 10) {
607 case 0:
608 set_isa(c, MIPS_CPU_ISA_M64R1);
609 break;
610 case 1:
611 set_isa(c, MIPS_CPU_ISA_M64R2);
612 break;
613 case 2:
614 set_isa(c, MIPS_CPU_ISA_M64R6);
615 break;
616 default:
617 goto unknown;
618 }
619 break;
620 default:
621 goto unknown;
622 }
623
624 return config0 & MIPS_CONF_M;
625
626 unknown:
627 panic(unknown_isa, config0);
628 }
629
630 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
631 {
632 unsigned int config1;
633
634 config1 = read_c0_config1();
635
636 if (config1 & MIPS_CONF1_MD)
637 c->ases |= MIPS_ASE_MDMX;
638 if (config1 & MIPS_CONF1_WR)
639 c->options |= MIPS_CPU_WATCH;
640 if (config1 & MIPS_CONF1_CA)
641 c->ases |= MIPS_ASE_MIPS16;
642 if (config1 & MIPS_CONF1_EP)
643 c->options |= MIPS_CPU_EJTAG;
644 if (config1 & MIPS_CONF1_FP) {
645 c->options |= MIPS_CPU_FPU;
646 c->options |= MIPS_CPU_32FPR;
647 }
648 if (cpu_has_tlb) {
649 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
650 c->tlbsizevtlb = c->tlbsize;
651 c->tlbsizeftlbsets = 0;
652 }
653
654 return config1 & MIPS_CONF_M;
655 }
656
657 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
658 {
659 unsigned int config2;
660
661 config2 = read_c0_config2();
662
663 if (config2 & MIPS_CONF2_SL)
664 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
665
666 return config2 & MIPS_CONF_M;
667 }
668
669 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
670 {
671 unsigned int config3;
672
673 config3 = read_c0_config3();
674
675 if (config3 & MIPS_CONF3_SM) {
676 c->ases |= MIPS_ASE_SMARTMIPS;
677 c->options |= MIPS_CPU_RIXI;
678 }
679 if (config3 & MIPS_CONF3_RXI)
680 c->options |= MIPS_CPU_RIXI;
681 if (config3 & MIPS_CONF3_DSP)
682 c->ases |= MIPS_ASE_DSP;
683 if (config3 & MIPS_CONF3_DSP2P)
684 c->ases |= MIPS_ASE_DSP2P;
685 if (config3 & MIPS_CONF3_VINT)
686 c->options |= MIPS_CPU_VINT;
687 if (config3 & MIPS_CONF3_VEIC)
688 c->options |= MIPS_CPU_VEIC;
689 if (config3 & MIPS_CONF3_MT)
690 c->ases |= MIPS_ASE_MIPSMT;
691 if (config3 & MIPS_CONF3_ULRI)
692 c->options |= MIPS_CPU_ULRI;
693 if (config3 & MIPS_CONF3_ISA)
694 c->options |= MIPS_CPU_MICROMIPS;
695 if (config3 & MIPS_CONF3_VZ)
696 c->ases |= MIPS_ASE_VZ;
697 if (config3 & MIPS_CONF3_SC)
698 c->options |= MIPS_CPU_SEGMENTS;
699 if (config3 & MIPS_CONF3_MSA)
700 c->ases |= MIPS_ASE_MSA;
701 if (config3 & MIPS_CONF3_PW) {
702 c->htw_seq = 0;
703 c->options |= MIPS_CPU_HTW;
704 }
705 if (config3 & MIPS_CONF3_CDMM)
706 c->options |= MIPS_CPU_CDMM;
707 if (config3 & MIPS_CONF3_SP)
708 c->options |= MIPS_CPU_SP;
709
710 return config3 & MIPS_CONF_M;
711 }
712
713 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
714 {
715 unsigned int config4;
716 unsigned int newcf4;
717 unsigned int mmuextdef;
718 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
719
720 config4 = read_c0_config4();
721
722 if (cpu_has_tlb) {
723 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
724 c->options |= MIPS_CPU_TLBINV;
725
726 /*
727 * R6 has dropped the MMUExtDef field from config4.
728 * On R6 the fields always describe the FTLB, and only if it is
729 * present according to Config.MT.
730 */
731 if (!cpu_has_mips_r6)
732 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
733 else if (cpu_has_ftlb)
734 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
735 else
736 mmuextdef = 0;
737
738 switch (mmuextdef) {
739 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
740 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
741 c->tlbsizevtlb = c->tlbsize;
742 break;
743 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
744 c->tlbsizevtlb +=
745 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
746 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
747 c->tlbsize = c->tlbsizevtlb;
748 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
749 /* fall through */
750 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
751 if (mips_ftlb_disabled)
752 break;
753 newcf4 = (config4 & ~ftlb_page) |
754 (page_size_ftlb(mmuextdef) <<
755 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
756 write_c0_config4(newcf4);
757 back_to_back_c0_hazard();
758 config4 = read_c0_config4();
759 if (config4 != newcf4) {
760 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
761 PAGE_SIZE, config4);
762 /* Switch FTLB off */
763 set_ftlb_enable(c, 0);
764 break;
765 }
766 c->tlbsizeftlbsets = 1 <<
767 ((config4 & MIPS_CONF4_FTLBSETS) >>
768 MIPS_CONF4_FTLBSETS_SHIFT);
769 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
770 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
771 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
772 mips_has_ftlb_configured = 1;
773 break;
774 }
775 }
776
777 c->kscratch_mask = (config4 >> 16) & 0xff;
778
779 return config4 & MIPS_CONF_M;
780 }
781
782 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
783 {
784 unsigned int config5;
785
786 config5 = read_c0_config5();
787 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
788 write_c0_config5(config5);
789
790 if (config5 & MIPS_CONF5_EVA)
791 c->options |= MIPS_CPU_EVA;
792 if (config5 & MIPS_CONF5_MRP)
793 c->options |= MIPS_CPU_MAAR;
794 if (config5 & MIPS_CONF5_LLB)
795 c->options |= MIPS_CPU_RW_LLB;
796 #ifdef CONFIG_XPA
797 if (config5 & MIPS_CONF5_MVH)
798 c->options |= MIPS_CPU_XPA;
799 #endif
800 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
801 c->options |= MIPS_CPU_VP;
802
803 return config5 & MIPS_CONF_M;
804 }
805
806 static void decode_configs(struct cpuinfo_mips *c)
807 {
808 int ok;
809
810 /* MIPS32 or MIPS64 compliant CPU. */
811 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
812 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
813
814 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
815
816 /* Enable FTLB if present and not disabled */
817 set_ftlb_enable(c, !mips_ftlb_disabled);
818
819 ok = decode_config0(c); /* Read Config registers. */
820 BUG_ON(!ok); /* Arch spec violation! */
821 if (ok)
822 ok = decode_config1(c);
823 if (ok)
824 ok = decode_config2(c);
825 if (ok)
826 ok = decode_config3(c);
827 if (ok)
828 ok = decode_config4(c);
829 if (ok)
830 ok = decode_config5(c);
831
832 mips_probe_watch_registers(c);
833
834 if (cpu_has_rixi) {
835 /* Enable the RIXI exceptions */
836 set_c0_pagegrain(PG_IEC);
837 back_to_back_c0_hazard();
838 /* Verify the IEC bit is set */
839 if (read_c0_pagegrain() & PG_IEC)
840 c->options |= MIPS_CPU_RIXIEX;
841 }
842
843 #ifndef CONFIG_MIPS_CPS
844 if (cpu_has_mips_r2_r6) {
845 c->core = get_ebase_cpunum();
846 if (cpu_has_mipsmt)
847 c->core >>= fls(core_nvpes()) - 1;
848 }
849 #endif
850 }
851
852 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
853 | MIPS_CPU_COUNTER)
854
855 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
856 {
857 switch (c->processor_id & PRID_IMP_MASK) {
858 case PRID_IMP_R2000:
859 c->cputype = CPU_R2000;
860 __cpu_name[cpu] = "R2000";
861 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
862 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
863 MIPS_CPU_NOFPUEX;
864 if (__cpu_has_fpu())
865 c->options |= MIPS_CPU_FPU;
866 c->tlbsize = 64;
867 break;
868 case PRID_IMP_R3000:
869 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
870 if (cpu_has_confreg()) {
871 c->cputype = CPU_R3081E;
872 __cpu_name[cpu] = "R3081";
873 } else {
874 c->cputype = CPU_R3000A;
875 __cpu_name[cpu] = "R3000A";
876 }
877 } else {
878 c->cputype = CPU_R3000;
879 __cpu_name[cpu] = "R3000";
880 }
881 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
882 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
883 MIPS_CPU_NOFPUEX;
884 if (__cpu_has_fpu())
885 c->options |= MIPS_CPU_FPU;
886 c->tlbsize = 64;
887 break;
888 case PRID_IMP_R4000:
889 if (read_c0_config() & CONF_SC) {
890 if ((c->processor_id & PRID_REV_MASK) >=
891 PRID_REV_R4400) {
892 c->cputype = CPU_R4400PC;
893 __cpu_name[cpu] = "R4400PC";
894 } else {
895 c->cputype = CPU_R4000PC;
896 __cpu_name[cpu] = "R4000PC";
897 }
898 } else {
899 int cca = read_c0_config() & CONF_CM_CMASK;
900 int mc;
901
902 /*
903 * SC and MC versions can't be reliably told apart,
904 * but only the latter support coherent caching
905 * modes so assume the firmware has set the KSEG0
906 * coherency attribute reasonably (if uncached, we
907 * assume SC).
908 */
909 switch (cca) {
910 case CONF_CM_CACHABLE_CE:
911 case CONF_CM_CACHABLE_COW:
912 case CONF_CM_CACHABLE_CUW:
913 mc = 1;
914 break;
915 default:
916 mc = 0;
917 break;
918 }
919 if ((c->processor_id & PRID_REV_MASK) >=
920 PRID_REV_R4400) {
921 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
922 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
923 } else {
924 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
925 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
926 }
927 }
928
929 set_isa(c, MIPS_CPU_ISA_III);
930 c->fpu_msk31 |= FPU_CSR_CONDX;
931 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
932 MIPS_CPU_WATCH | MIPS_CPU_VCE |
933 MIPS_CPU_LLSC;
934 c->tlbsize = 48;
935 break;
936 case PRID_IMP_VR41XX:
937 set_isa(c, MIPS_CPU_ISA_III);
938 c->fpu_msk31 |= FPU_CSR_CONDX;
939 c->options = R4K_OPTS;
940 c->tlbsize = 32;
941 switch (c->processor_id & 0xf0) {
942 case PRID_REV_VR4111:
943 c->cputype = CPU_VR4111;
944 __cpu_name[cpu] = "NEC VR4111";
945 break;
946 case PRID_REV_VR4121:
947 c->cputype = CPU_VR4121;
948 __cpu_name[cpu] = "NEC VR4121";
949 break;
950 case PRID_REV_VR4122:
951 if ((c->processor_id & 0xf) < 0x3) {
952 c->cputype = CPU_VR4122;
953 __cpu_name[cpu] = "NEC VR4122";
954 } else {
955 c->cputype = CPU_VR4181A;
956 __cpu_name[cpu] = "NEC VR4181A";
957 }
958 break;
959 case PRID_REV_VR4130:
960 if ((c->processor_id & 0xf) < 0x4) {
961 c->cputype = CPU_VR4131;
962 __cpu_name[cpu] = "NEC VR4131";
963 } else {
964 c->cputype = CPU_VR4133;
965 c->options |= MIPS_CPU_LLSC;
966 __cpu_name[cpu] = "NEC VR4133";
967 }
968 break;
969 default:
970 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
971 c->cputype = CPU_VR41XX;
972 __cpu_name[cpu] = "NEC Vr41xx";
973 break;
974 }
975 break;
976 case PRID_IMP_R4300:
977 c->cputype = CPU_R4300;
978 __cpu_name[cpu] = "R4300";
979 set_isa(c, MIPS_CPU_ISA_III);
980 c->fpu_msk31 |= FPU_CSR_CONDX;
981 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
982 MIPS_CPU_LLSC;
983 c->tlbsize = 32;
984 break;
985 case PRID_IMP_R4600:
986 c->cputype = CPU_R4600;
987 __cpu_name[cpu] = "R4600";
988 set_isa(c, MIPS_CPU_ISA_III);
989 c->fpu_msk31 |= FPU_CSR_CONDX;
990 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
991 MIPS_CPU_LLSC;
992 c->tlbsize = 48;
993 break;
994 #if 0
995 case PRID_IMP_R4650:
996 /*
997 * This processor doesn't have an MMU, so it's not
998 * "real easy" to run Linux on it. It is left purely
999 * for documentation. Commented out because it shares
1000 * it's c0_prid id number with the TX3900.
1001 */
1002 c->cputype = CPU_R4650;
1003 __cpu_name[cpu] = "R4650";
1004 set_isa(c, MIPS_CPU_ISA_III);
1005 c->fpu_msk31 |= FPU_CSR_CONDX;
1006 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1007 c->tlbsize = 48;
1008 break;
1009 #endif
1010 case PRID_IMP_TX39:
1011 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1012 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1013
1014 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1015 c->cputype = CPU_TX3927;
1016 __cpu_name[cpu] = "TX3927";
1017 c->tlbsize = 64;
1018 } else {
1019 switch (c->processor_id & PRID_REV_MASK) {
1020 case PRID_REV_TX3912:
1021 c->cputype = CPU_TX3912;
1022 __cpu_name[cpu] = "TX3912";
1023 c->tlbsize = 32;
1024 break;
1025 case PRID_REV_TX3922:
1026 c->cputype = CPU_TX3922;
1027 __cpu_name[cpu] = "TX3922";
1028 c->tlbsize = 64;
1029 break;
1030 }
1031 }
1032 break;
1033 case PRID_IMP_R4700:
1034 c->cputype = CPU_R4700;
1035 __cpu_name[cpu] = "R4700";
1036 set_isa(c, MIPS_CPU_ISA_III);
1037 c->fpu_msk31 |= FPU_CSR_CONDX;
1038 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1039 MIPS_CPU_LLSC;
1040 c->tlbsize = 48;
1041 break;
1042 case PRID_IMP_TX49:
1043 c->cputype = CPU_TX49XX;
1044 __cpu_name[cpu] = "R49XX";
1045 set_isa(c, MIPS_CPU_ISA_III);
1046 c->fpu_msk31 |= FPU_CSR_CONDX;
1047 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1048 if (!(c->processor_id & 0x08))
1049 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1050 c->tlbsize = 48;
1051 break;
1052 case PRID_IMP_R5000:
1053 c->cputype = CPU_R5000;
1054 __cpu_name[cpu] = "R5000";
1055 set_isa(c, MIPS_CPU_ISA_IV);
1056 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1057 MIPS_CPU_LLSC;
1058 c->tlbsize = 48;
1059 break;
1060 case PRID_IMP_R5432:
1061 c->cputype = CPU_R5432;
1062 __cpu_name[cpu] = "R5432";
1063 set_isa(c, MIPS_CPU_ISA_IV);
1064 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1065 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1066 c->tlbsize = 48;
1067 break;
1068 case PRID_IMP_R5500:
1069 c->cputype = CPU_R5500;
1070 __cpu_name[cpu] = "R5500";
1071 set_isa(c, MIPS_CPU_ISA_IV);
1072 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1073 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1074 c->tlbsize = 48;
1075 break;
1076 case PRID_IMP_NEVADA:
1077 c->cputype = CPU_NEVADA;
1078 __cpu_name[cpu] = "Nevada";
1079 set_isa(c, MIPS_CPU_ISA_IV);
1080 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1081 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1082 c->tlbsize = 48;
1083 break;
1084 case PRID_IMP_R6000:
1085 c->cputype = CPU_R6000;
1086 __cpu_name[cpu] = "R6000";
1087 set_isa(c, MIPS_CPU_ISA_II);
1088 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1089 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1090 MIPS_CPU_LLSC;
1091 c->tlbsize = 32;
1092 break;
1093 case PRID_IMP_R6000A:
1094 c->cputype = CPU_R6000A;
1095 __cpu_name[cpu] = "R6000A";
1096 set_isa(c, MIPS_CPU_ISA_II);
1097 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1098 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1099 MIPS_CPU_LLSC;
1100 c->tlbsize = 32;
1101 break;
1102 case PRID_IMP_RM7000:
1103 c->cputype = CPU_RM7000;
1104 __cpu_name[cpu] = "RM7000";
1105 set_isa(c, MIPS_CPU_ISA_IV);
1106 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1107 MIPS_CPU_LLSC;
1108 /*
1109 * Undocumented RM7000: Bit 29 in the info register of
1110 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1111 * entries.
1112 *
1113 * 29 1 => 64 entry JTLB
1114 * 0 => 48 entry JTLB
1115 */
1116 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1117 break;
1118 case PRID_IMP_R8000:
1119 c->cputype = CPU_R8000;
1120 __cpu_name[cpu] = "RM8000";
1121 set_isa(c, MIPS_CPU_ISA_IV);
1122 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1123 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1124 MIPS_CPU_LLSC;
1125 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1126 break;
1127 case PRID_IMP_R10000:
1128 c->cputype = CPU_R10000;
1129 __cpu_name[cpu] = "R10000";
1130 set_isa(c, MIPS_CPU_ISA_IV);
1131 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1132 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1133 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1134 MIPS_CPU_LLSC;
1135 c->tlbsize = 64;
1136 break;
1137 case PRID_IMP_R12000:
1138 c->cputype = CPU_R12000;
1139 __cpu_name[cpu] = "R12000";
1140 set_isa(c, MIPS_CPU_ISA_IV);
1141 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1142 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1143 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1144 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1145 c->tlbsize = 64;
1146 break;
1147 case PRID_IMP_R14000:
1148 if (((c->processor_id >> 4) & 0x0f) > 2) {
1149 c->cputype = CPU_R16000;
1150 __cpu_name[cpu] = "R16000";
1151 } else {
1152 c->cputype = CPU_R14000;
1153 __cpu_name[cpu] = "R14000";
1154 }
1155 set_isa(c, MIPS_CPU_ISA_IV);
1156 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1157 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1158 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1159 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1160 c->tlbsize = 64;
1161 break;
1162 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1163 switch (c->processor_id & PRID_REV_MASK) {
1164 case PRID_REV_LOONGSON2E:
1165 c->cputype = CPU_LOONGSON2;
1166 __cpu_name[cpu] = "ICT Loongson-2";
1167 set_elf_platform(cpu, "loongson2e");
1168 set_isa(c, MIPS_CPU_ISA_III);
1169 c->fpu_msk31 |= FPU_CSR_CONDX;
1170 break;
1171 case PRID_REV_LOONGSON2F:
1172 c->cputype = CPU_LOONGSON2;
1173 __cpu_name[cpu] = "ICT Loongson-2";
1174 set_elf_platform(cpu, "loongson2f");
1175 set_isa(c, MIPS_CPU_ISA_III);
1176 c->fpu_msk31 |= FPU_CSR_CONDX;
1177 break;
1178 case PRID_REV_LOONGSON3A:
1179 c->cputype = CPU_LOONGSON3;
1180 __cpu_name[cpu] = "ICT Loongson-3";
1181 set_elf_platform(cpu, "loongson3a");
1182 set_isa(c, MIPS_CPU_ISA_M64R1);
1183 break;
1184 case PRID_REV_LOONGSON3B_R1:
1185 case PRID_REV_LOONGSON3B_R2:
1186 c->cputype = CPU_LOONGSON3;
1187 __cpu_name[cpu] = "ICT Loongson-3";
1188 set_elf_platform(cpu, "loongson3b");
1189 set_isa(c, MIPS_CPU_ISA_M64R1);
1190 break;
1191 }
1192
1193 c->options = R4K_OPTS |
1194 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1195 MIPS_CPU_32FPR;
1196 c->tlbsize = 64;
1197 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1198 break;
1199 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1200 decode_configs(c);
1201
1202 c->cputype = CPU_LOONGSON1;
1203
1204 switch (c->processor_id & PRID_REV_MASK) {
1205 case PRID_REV_LOONGSON1B:
1206 __cpu_name[cpu] = "Loongson 1B";
1207 break;
1208 }
1209
1210 break;
1211 }
1212 }
1213
1214 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1215 {
1216 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1217 switch (c->processor_id & PRID_IMP_MASK) {
1218 case PRID_IMP_QEMU_GENERIC:
1219 c->writecombine = _CACHE_UNCACHED;
1220 c->cputype = CPU_QEMU_GENERIC;
1221 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1222 break;
1223 case PRID_IMP_4KC:
1224 c->cputype = CPU_4KC;
1225 c->writecombine = _CACHE_UNCACHED;
1226 __cpu_name[cpu] = "MIPS 4Kc";
1227 break;
1228 case PRID_IMP_4KEC:
1229 case PRID_IMP_4KECR2:
1230 c->cputype = CPU_4KEC;
1231 c->writecombine = _CACHE_UNCACHED;
1232 __cpu_name[cpu] = "MIPS 4KEc";
1233 break;
1234 case PRID_IMP_4KSC:
1235 case PRID_IMP_4KSD:
1236 c->cputype = CPU_4KSC;
1237 c->writecombine = _CACHE_UNCACHED;
1238 __cpu_name[cpu] = "MIPS 4KSc";
1239 break;
1240 case PRID_IMP_5KC:
1241 c->cputype = CPU_5KC;
1242 c->writecombine = _CACHE_UNCACHED;
1243 __cpu_name[cpu] = "MIPS 5Kc";
1244 break;
1245 case PRID_IMP_5KE:
1246 c->cputype = CPU_5KE;
1247 c->writecombine = _CACHE_UNCACHED;
1248 __cpu_name[cpu] = "MIPS 5KE";
1249 break;
1250 case PRID_IMP_20KC:
1251 c->cputype = CPU_20KC;
1252 c->writecombine = _CACHE_UNCACHED;
1253 __cpu_name[cpu] = "MIPS 20Kc";
1254 break;
1255 case PRID_IMP_24K:
1256 c->cputype = CPU_24K;
1257 c->writecombine = _CACHE_UNCACHED;
1258 __cpu_name[cpu] = "MIPS 24Kc";
1259 break;
1260 case PRID_IMP_24KE:
1261 c->cputype = CPU_24K;
1262 c->writecombine = _CACHE_UNCACHED;
1263 __cpu_name[cpu] = "MIPS 24KEc";
1264 break;
1265 case PRID_IMP_25KF:
1266 c->cputype = CPU_25KF;
1267 c->writecombine = _CACHE_UNCACHED;
1268 __cpu_name[cpu] = "MIPS 25Kc";
1269 break;
1270 case PRID_IMP_34K:
1271 c->cputype = CPU_34K;
1272 c->writecombine = _CACHE_UNCACHED;
1273 __cpu_name[cpu] = "MIPS 34Kc";
1274 break;
1275 case PRID_IMP_74K:
1276 c->cputype = CPU_74K;
1277 c->writecombine = _CACHE_UNCACHED;
1278 __cpu_name[cpu] = "MIPS 74Kc";
1279 break;
1280 case PRID_IMP_M14KC:
1281 c->cputype = CPU_M14KC;
1282 c->writecombine = _CACHE_UNCACHED;
1283 __cpu_name[cpu] = "MIPS M14Kc";
1284 break;
1285 case PRID_IMP_M14KEC:
1286 c->cputype = CPU_M14KEC;
1287 c->writecombine = _CACHE_UNCACHED;
1288 __cpu_name[cpu] = "MIPS M14KEc";
1289 break;
1290 case PRID_IMP_1004K:
1291 c->cputype = CPU_1004K;
1292 c->writecombine = _CACHE_UNCACHED;
1293 __cpu_name[cpu] = "MIPS 1004Kc";
1294 break;
1295 case PRID_IMP_1074K:
1296 c->cputype = CPU_1074K;
1297 c->writecombine = _CACHE_UNCACHED;
1298 __cpu_name[cpu] = "MIPS 1074Kc";
1299 break;
1300 case PRID_IMP_INTERAPTIV_UP:
1301 c->cputype = CPU_INTERAPTIV;
1302 __cpu_name[cpu] = "MIPS interAptiv";
1303 break;
1304 case PRID_IMP_INTERAPTIV_MP:
1305 c->cputype = CPU_INTERAPTIV;
1306 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1307 break;
1308 case PRID_IMP_PROAPTIV_UP:
1309 c->cputype = CPU_PROAPTIV;
1310 __cpu_name[cpu] = "MIPS proAptiv";
1311 break;
1312 case PRID_IMP_PROAPTIV_MP:
1313 c->cputype = CPU_PROAPTIV;
1314 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1315 break;
1316 case PRID_IMP_P5600:
1317 c->cputype = CPU_P5600;
1318 __cpu_name[cpu] = "MIPS P5600";
1319 break;
1320 case PRID_IMP_P6600:
1321 c->cputype = CPU_P6600;
1322 __cpu_name[cpu] = "MIPS P6600";
1323 break;
1324 case PRID_IMP_I6400:
1325 c->cputype = CPU_I6400;
1326 __cpu_name[cpu] = "MIPS I6400";
1327 break;
1328 case PRID_IMP_M5150:
1329 c->cputype = CPU_M5150;
1330 __cpu_name[cpu] = "MIPS M5150";
1331 break;
1332 }
1333
1334 decode_configs(c);
1335
1336 spram_config();
1337 }
1338
1339 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1340 {
1341 decode_configs(c);
1342 switch (c->processor_id & PRID_IMP_MASK) {
1343 case PRID_IMP_AU1_REV1:
1344 case PRID_IMP_AU1_REV2:
1345 c->cputype = CPU_ALCHEMY;
1346 switch ((c->processor_id >> 24) & 0xff) {
1347 case 0:
1348 __cpu_name[cpu] = "Au1000";
1349 break;
1350 case 1:
1351 __cpu_name[cpu] = "Au1500";
1352 break;
1353 case 2:
1354 __cpu_name[cpu] = "Au1100";
1355 break;
1356 case 3:
1357 __cpu_name[cpu] = "Au1550";
1358 break;
1359 case 4:
1360 __cpu_name[cpu] = "Au1200";
1361 if ((c->processor_id & PRID_REV_MASK) == 2)
1362 __cpu_name[cpu] = "Au1250";
1363 break;
1364 case 5:
1365 __cpu_name[cpu] = "Au1210";
1366 break;
1367 default:
1368 __cpu_name[cpu] = "Au1xxx";
1369 break;
1370 }
1371 break;
1372 }
1373 }
1374
1375 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1376 {
1377 decode_configs(c);
1378
1379 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1380 switch (c->processor_id & PRID_IMP_MASK) {
1381 case PRID_IMP_SB1:
1382 c->cputype = CPU_SB1;
1383 __cpu_name[cpu] = "SiByte SB1";
1384 /* FPU in pass1 is known to have issues. */
1385 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1386 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1387 break;
1388 case PRID_IMP_SB1A:
1389 c->cputype = CPU_SB1A;
1390 __cpu_name[cpu] = "SiByte SB1A";
1391 break;
1392 }
1393 }
1394
1395 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1396 {
1397 decode_configs(c);
1398 switch (c->processor_id & PRID_IMP_MASK) {
1399 case PRID_IMP_SR71000:
1400 c->cputype = CPU_SR71000;
1401 __cpu_name[cpu] = "Sandcraft SR71000";
1402 c->scache.ways = 8;
1403 c->tlbsize = 64;
1404 break;
1405 }
1406 }
1407
1408 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1409 {
1410 decode_configs(c);
1411 switch (c->processor_id & PRID_IMP_MASK) {
1412 case PRID_IMP_PR4450:
1413 c->cputype = CPU_PR4450;
1414 __cpu_name[cpu] = "Philips PR4450";
1415 set_isa(c, MIPS_CPU_ISA_M32R1);
1416 break;
1417 }
1418 }
1419
1420 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1421 {
1422 decode_configs(c);
1423 switch (c->processor_id & PRID_IMP_MASK) {
1424 case PRID_IMP_BMIPS32_REV4:
1425 case PRID_IMP_BMIPS32_REV8:
1426 c->cputype = CPU_BMIPS32;
1427 __cpu_name[cpu] = "Broadcom BMIPS32";
1428 set_elf_platform(cpu, "bmips32");
1429 break;
1430 case PRID_IMP_BMIPS3300:
1431 case PRID_IMP_BMIPS3300_ALT:
1432 case PRID_IMP_BMIPS3300_BUG:
1433 c->cputype = CPU_BMIPS3300;
1434 __cpu_name[cpu] = "Broadcom BMIPS3300";
1435 set_elf_platform(cpu, "bmips3300");
1436 break;
1437 case PRID_IMP_BMIPS43XX: {
1438 int rev = c->processor_id & PRID_REV_MASK;
1439
1440 if (rev >= PRID_REV_BMIPS4380_LO &&
1441 rev <= PRID_REV_BMIPS4380_HI) {
1442 c->cputype = CPU_BMIPS4380;
1443 __cpu_name[cpu] = "Broadcom BMIPS4380";
1444 set_elf_platform(cpu, "bmips4380");
1445 } else {
1446 c->cputype = CPU_BMIPS4350;
1447 __cpu_name[cpu] = "Broadcom BMIPS4350";
1448 set_elf_platform(cpu, "bmips4350");
1449 }
1450 break;
1451 }
1452 case PRID_IMP_BMIPS5000:
1453 case PRID_IMP_BMIPS5200:
1454 c->cputype = CPU_BMIPS5000;
1455 __cpu_name[cpu] = "Broadcom BMIPS5000";
1456 set_elf_platform(cpu, "bmips5000");
1457 c->options |= MIPS_CPU_ULRI;
1458 break;
1459 }
1460 }
1461
1462 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1463 {
1464 decode_configs(c);
1465 switch (c->processor_id & PRID_IMP_MASK) {
1466 case PRID_IMP_CAVIUM_CN38XX:
1467 case PRID_IMP_CAVIUM_CN31XX:
1468 case PRID_IMP_CAVIUM_CN30XX:
1469 c->cputype = CPU_CAVIUM_OCTEON;
1470 __cpu_name[cpu] = "Cavium Octeon";
1471 goto platform;
1472 case PRID_IMP_CAVIUM_CN58XX:
1473 case PRID_IMP_CAVIUM_CN56XX:
1474 case PRID_IMP_CAVIUM_CN50XX:
1475 case PRID_IMP_CAVIUM_CN52XX:
1476 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1477 __cpu_name[cpu] = "Cavium Octeon+";
1478 platform:
1479 set_elf_platform(cpu, "octeon");
1480 break;
1481 case PRID_IMP_CAVIUM_CN61XX:
1482 case PRID_IMP_CAVIUM_CN63XX:
1483 case PRID_IMP_CAVIUM_CN66XX:
1484 case PRID_IMP_CAVIUM_CN68XX:
1485 case PRID_IMP_CAVIUM_CNF71XX:
1486 c->cputype = CPU_CAVIUM_OCTEON2;
1487 __cpu_name[cpu] = "Cavium Octeon II";
1488 set_elf_platform(cpu, "octeon2");
1489 break;
1490 case PRID_IMP_CAVIUM_CN70XX:
1491 case PRID_IMP_CAVIUM_CN73XX:
1492 case PRID_IMP_CAVIUM_CNF75XX:
1493 case PRID_IMP_CAVIUM_CN78XX:
1494 c->cputype = CPU_CAVIUM_OCTEON3;
1495 __cpu_name[cpu] = "Cavium Octeon III";
1496 set_elf_platform(cpu, "octeon3");
1497 break;
1498 default:
1499 printk(KERN_INFO "Unknown Octeon chip!\n");
1500 c->cputype = CPU_UNKNOWN;
1501 break;
1502 }
1503 }
1504
1505 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1506 {
1507 decode_configs(c);
1508 /* JZRISC does not implement the CP0 counter. */
1509 c->options &= ~MIPS_CPU_COUNTER;
1510 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1511 switch (c->processor_id & PRID_IMP_MASK) {
1512 case PRID_IMP_JZRISC:
1513 c->cputype = CPU_JZRISC;
1514 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1515 __cpu_name[cpu] = "Ingenic JZRISC";
1516 break;
1517 default:
1518 panic("Unknown Ingenic Processor ID!");
1519 break;
1520 }
1521 }
1522
1523 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1524 {
1525 decode_configs(c);
1526
1527 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1528 c->cputype = CPU_ALCHEMY;
1529 __cpu_name[cpu] = "Au1300";
1530 /* following stuff is not for Alchemy */
1531 return;
1532 }
1533
1534 c->options = (MIPS_CPU_TLB |
1535 MIPS_CPU_4KEX |
1536 MIPS_CPU_COUNTER |
1537 MIPS_CPU_DIVEC |
1538 MIPS_CPU_WATCH |
1539 MIPS_CPU_EJTAG |
1540 MIPS_CPU_LLSC);
1541
1542 switch (c->processor_id & PRID_IMP_MASK) {
1543 case PRID_IMP_NETLOGIC_XLP2XX:
1544 case PRID_IMP_NETLOGIC_XLP9XX:
1545 case PRID_IMP_NETLOGIC_XLP5XX:
1546 c->cputype = CPU_XLP;
1547 __cpu_name[cpu] = "Broadcom XLPII";
1548 break;
1549
1550 case PRID_IMP_NETLOGIC_XLP8XX:
1551 case PRID_IMP_NETLOGIC_XLP3XX:
1552 c->cputype = CPU_XLP;
1553 __cpu_name[cpu] = "Netlogic XLP";
1554 break;
1555
1556 case PRID_IMP_NETLOGIC_XLR732:
1557 case PRID_IMP_NETLOGIC_XLR716:
1558 case PRID_IMP_NETLOGIC_XLR532:
1559 case PRID_IMP_NETLOGIC_XLR308:
1560 case PRID_IMP_NETLOGIC_XLR532C:
1561 case PRID_IMP_NETLOGIC_XLR516C:
1562 case PRID_IMP_NETLOGIC_XLR508C:
1563 case PRID_IMP_NETLOGIC_XLR308C:
1564 c->cputype = CPU_XLR;
1565 __cpu_name[cpu] = "Netlogic XLR";
1566 break;
1567
1568 case PRID_IMP_NETLOGIC_XLS608:
1569 case PRID_IMP_NETLOGIC_XLS408:
1570 case PRID_IMP_NETLOGIC_XLS404:
1571 case PRID_IMP_NETLOGIC_XLS208:
1572 case PRID_IMP_NETLOGIC_XLS204:
1573 case PRID_IMP_NETLOGIC_XLS108:
1574 case PRID_IMP_NETLOGIC_XLS104:
1575 case PRID_IMP_NETLOGIC_XLS616B:
1576 case PRID_IMP_NETLOGIC_XLS608B:
1577 case PRID_IMP_NETLOGIC_XLS416B:
1578 case PRID_IMP_NETLOGIC_XLS412B:
1579 case PRID_IMP_NETLOGIC_XLS408B:
1580 case PRID_IMP_NETLOGIC_XLS404B:
1581 c->cputype = CPU_XLR;
1582 __cpu_name[cpu] = "Netlogic XLS";
1583 break;
1584
1585 default:
1586 pr_info("Unknown Netlogic chip id [%02x]!\n",
1587 c->processor_id);
1588 c->cputype = CPU_XLR;
1589 break;
1590 }
1591
1592 if (c->cputype == CPU_XLP) {
1593 set_isa(c, MIPS_CPU_ISA_M64R2);
1594 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1595 /* This will be updated again after all threads are woken up */
1596 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1597 } else {
1598 set_isa(c, MIPS_CPU_ISA_M64R1);
1599 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1600 }
1601 c->kscratch_mask = 0xf;
1602 }
1603
1604 #ifdef CONFIG_64BIT
1605 /* For use by uaccess.h */
1606 u64 __ua_limit;
1607 EXPORT_SYMBOL(__ua_limit);
1608 #endif
1609
1610 const char *__cpu_name[NR_CPUS];
1611 const char *__elf_platform;
1612
1613 void cpu_probe(void)
1614 {
1615 struct cpuinfo_mips *c = &current_cpu_data;
1616 unsigned int cpu = smp_processor_id();
1617
1618 c->processor_id = PRID_IMP_UNKNOWN;
1619 c->fpu_id = FPIR_IMP_NONE;
1620 c->cputype = CPU_UNKNOWN;
1621 c->writecombine = _CACHE_UNCACHED;
1622
1623 c->fpu_csr31 = FPU_CSR_RN;
1624 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1625
1626 c->processor_id = read_c0_prid();
1627 switch (c->processor_id & PRID_COMP_MASK) {
1628 case PRID_COMP_LEGACY:
1629 cpu_probe_legacy(c, cpu);
1630 break;
1631 case PRID_COMP_MIPS:
1632 cpu_probe_mips(c, cpu);
1633 break;
1634 case PRID_COMP_ALCHEMY:
1635 cpu_probe_alchemy(c, cpu);
1636 break;
1637 case PRID_COMP_SIBYTE:
1638 cpu_probe_sibyte(c, cpu);
1639 break;
1640 case PRID_COMP_BROADCOM:
1641 cpu_probe_broadcom(c, cpu);
1642 break;
1643 case PRID_COMP_SANDCRAFT:
1644 cpu_probe_sandcraft(c, cpu);
1645 break;
1646 case PRID_COMP_NXP:
1647 cpu_probe_nxp(c, cpu);
1648 break;
1649 case PRID_COMP_CAVIUM:
1650 cpu_probe_cavium(c, cpu);
1651 break;
1652 case PRID_COMP_INGENIC_D0:
1653 case PRID_COMP_INGENIC_D1:
1654 case PRID_COMP_INGENIC_E1:
1655 cpu_probe_ingenic(c, cpu);
1656 break;
1657 case PRID_COMP_NETLOGIC:
1658 cpu_probe_netlogic(c, cpu);
1659 break;
1660 }
1661
1662 BUG_ON(!__cpu_name[cpu]);
1663 BUG_ON(c->cputype == CPU_UNKNOWN);
1664
1665 /*
1666 * Platform code can force the cpu type to optimize code
1667 * generation. In that case be sure the cpu type is correctly
1668 * manually setup otherwise it could trigger some nasty bugs.
1669 */
1670 BUG_ON(current_cpu_type() != c->cputype);
1671
1672 if (mips_fpu_disabled)
1673 c->options &= ~MIPS_CPU_FPU;
1674
1675 if (mips_dsp_disabled)
1676 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1677
1678 if (mips_htw_disabled) {
1679 c->options &= ~MIPS_CPU_HTW;
1680 write_c0_pwctl(read_c0_pwctl() &
1681 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1682 }
1683
1684 if (c->options & MIPS_CPU_FPU)
1685 cpu_set_fpu_opts(c);
1686 else
1687 cpu_set_nofpu_opts(c);
1688
1689 if (cpu_has_bp_ghist)
1690 write_c0_r10k_diag(read_c0_r10k_diag() |
1691 R10K_DIAG_E_GHIST);
1692
1693 if (cpu_has_mips_r2_r6) {
1694 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1695 /* R2 has Performance Counter Interrupt indicator */
1696 c->options |= MIPS_CPU_PCI;
1697 }
1698 else
1699 c->srsets = 1;
1700
1701 if (cpu_has_mips_r6)
1702 elf_hwcap |= HWCAP_MIPS_R6;
1703
1704 if (cpu_has_msa) {
1705 c->msa_id = cpu_get_msa_id();
1706 WARN(c->msa_id & MSA_IR_WRPF,
1707 "Vector register partitioning unimplemented!");
1708 elf_hwcap |= HWCAP_MIPS_MSA;
1709 }
1710
1711 cpu_probe_vmbits(c);
1712
1713 #ifdef CONFIG_64BIT
1714 if (cpu == 0)
1715 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1716 #endif
1717 }
1718
1719 void cpu_report(void)
1720 {
1721 struct cpuinfo_mips *c = &current_cpu_data;
1722
1723 pr_info("CPU%d revision is: %08x (%s)\n",
1724 smp_processor_id(), c->processor_id, cpu_name_string());
1725 if (c->options & MIPS_CPU_FPU)
1726 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1727 if (cpu_has_msa)
1728 pr_info("MSA revision is: %08x\n", c->msa_id);
1729 }
Linux kernel - Deliverables
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