2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
28 #include <asm/watch.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/spram.h>
32 #include <asm/uaccess.h>
34 static int mips_fpu_disabled
;
36 static int __init
fpu_disable(char *s
)
38 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
39 mips_fpu_disabled
= 1;
44 __setup("nofpu", fpu_disable
);
46 int mips_dsp_disabled
;
48 static int __init
dsp_disable(char *s
)
50 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
51 mips_dsp_disabled
= 1;
56 __setup("nodsp", dsp_disable
);
58 static int mips_htw_disabled
;
60 static int __init
htw_disable(char *s
)
62 mips_htw_disabled
= 1;
63 cpu_data
[0].options
&= ~MIPS_CPU_HTW
;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
70 __setup("nohtw", htw_disable
);
72 static int mips_ftlb_disabled
;
73 static int mips_has_ftlb_configured
;
75 static void set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
);
77 static int __init
ftlb_disable(char *s
)
79 unsigned int config4
, mmuextdef
;
82 * If the core hasn't done any FTLB configuration, there is nothing
85 if (!mips_has_ftlb_configured
)
88 /* Disable it in the boot cpu */
89 set_ftlb_enable(&cpu_data
[0], 0);
91 back_to_back_c0_hazard();
93 config4
= read_c0_config4();
95 /* Check that FTLB has been disabled */
96 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
98 if (mmuextdef
== MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
) {
99 /* This should never happen */
100 pr_warn("FTLB could not be disabled!\n");
104 mips_ftlb_disabled
= 1;
105 mips_has_ftlb_configured
= 0;
108 * noftlb is mainly used for debug purposes so print
109 * an informative message instead of using pr_debug()
111 pr_info("FTLB has been disabled\n");
114 * Some of these bits are duplicated in the decode_config4.
115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
116 * once FTLB has been disabled so undo what decode_config4 did.
118 cpu_data
[0].tlbsize
-= cpu_data
[0].tlbsizeftlbways
*
119 cpu_data
[0].tlbsizeftlbsets
;
120 cpu_data
[0].tlbsizeftlbsets
= 0;
121 cpu_data
[0].tlbsizeftlbways
= 0;
126 __setup("noftlb", ftlb_disable
);
129 static inline void check_errata(void)
131 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
133 switch (current_cpu_type()) {
136 * Erratum "RPS May Cause Incorrect Instruction Execution"
137 * This code only handles VPE0, any SMP/RTOS code
138 * making use of VPE1 will be responsable for that VPE.
140 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
148 void __init
check_bugs32(void)
154 * Probe whether cpu has config register by trying to play with
155 * alternate cache bit and see whether it matters.
156 * It's used by cpu_probe to distinguish between R3000A and R3081.
158 static inline int cpu_has_confreg(void)
160 #ifdef CONFIG_CPU_R3000
161 extern unsigned long r3k_cache_size(unsigned long);
162 unsigned long size1
, size2
;
163 unsigned long cfg
= read_c0_conf();
165 size1
= r3k_cache_size(ST0_ISC
);
166 write_c0_conf(cfg
^ R30XX_CONF_AC
);
167 size2
= r3k_cache_size(ST0_ISC
);
169 return size1
!= size2
;
175 static inline void set_elf_platform(int cpu
, const char *plat
)
178 __elf_platform
= plat
;
182 * Get the FPU Implementation/Revision.
184 static inline unsigned long cpu_get_fpu_id(void)
186 unsigned long tmp
, fpu_id
;
188 tmp
= read_c0_status();
189 __enable_fpu(FPU_AS_IS
);
190 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
191 write_c0_status(tmp
);
196 * Check if the CPU has an external FPU.
198 static inline int __cpu_has_fpu(void)
200 return (cpu_get_fpu_id() & FPIR_IMP_MASK
) != FPIR_IMP_NONE
;
203 static inline unsigned long cpu_get_msa_id(void)
205 unsigned long status
, msa_id
;
207 status
= read_c0_status();
208 __enable_fpu(FPU_64BIT
);
210 msa_id
= read_msa_ir();
212 write_c0_status(status
);
216 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
218 #ifdef __NEED_VMBITS_PROBE
219 write_c0_entryhi(0x3fffffffffffe000ULL
);
220 back_to_back_c0_hazard();
221 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
225 static void set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
228 case MIPS_CPU_ISA_M64R2
:
229 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
230 case MIPS_CPU_ISA_M64R1
:
231 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
233 c
->isa_level
|= MIPS_CPU_ISA_V
;
234 case MIPS_CPU_ISA_IV
:
235 c
->isa_level
|= MIPS_CPU_ISA_IV
;
236 case MIPS_CPU_ISA_III
:
237 c
->isa_level
|= MIPS_CPU_ISA_II
| MIPS_CPU_ISA_III
;
240 /* R6 incompatible with everything else */
241 case MIPS_CPU_ISA_M64R6
:
242 c
->isa_level
|= MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
;
243 case MIPS_CPU_ISA_M32R6
:
244 c
->isa_level
|= MIPS_CPU_ISA_M32R6
;
245 /* Break here so we don't add incompatible ISAs */
247 case MIPS_CPU_ISA_M32R2
:
248 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
249 case MIPS_CPU_ISA_M32R1
:
250 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
251 case MIPS_CPU_ISA_II
:
252 c
->isa_level
|= MIPS_CPU_ISA_II
;
257 static char unknown_isa
[] = KERN_ERR \
258 "Unsupported ISA type, c0.config0: %d.";
260 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips
*c
)
263 unsigned int probability
= c
->tlbsize
/ c
->tlbsizevtlb
;
266 * 0 = All TLBWR instructions go to FTLB
267 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
268 * FTLB and 1 goes to the VTLB.
269 * 2 = 7:1: As above with 7:1 ratio.
270 * 3 = 3:1: As above with 3:1 ratio.
272 * Use the linear midpoint as the probability threshold.
274 if (probability
>= 12)
276 else if (probability
>= 6)
280 * So FTLB is less than 4 times bigger than VTLB.
281 * A 3:1 ratio can still be useful though.
286 static void set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
)
288 unsigned int config6
;
290 /* It's implementation dependent how the FTLB can be enabled */
291 switch (c
->cputype
) {
294 /* proAptiv & related cores use Config6 to enable the FTLB */
295 config6
= read_c0_config6();
296 /* Clear the old probability value */
297 config6
&= ~(3 << MIPS_CONF6_FTLBP_SHIFT
);
300 write_c0_config6(config6
|
301 (calculate_ftlb_probability(c
)
302 << MIPS_CONF6_FTLBP_SHIFT
)
303 | MIPS_CONF6_FTLBEN
);
306 write_c0_config6(config6
& ~MIPS_CONF6_FTLBEN
);
307 back_to_back_c0_hazard();
312 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
314 unsigned int config0
;
317 config0
= read_c0_config();
320 * Look for Standard TLB or Dual VTLB and FTLB
322 if ((((config0
& MIPS_CONF_MT
) >> 7) == 1) ||
323 (((config0
& MIPS_CONF_MT
) >> 7) == 4))
324 c
->options
|= MIPS_CPU_TLB
;
326 isa
= (config0
& MIPS_CONF_AT
) >> 13;
329 switch ((config0
& MIPS_CONF_AR
) >> 10) {
331 set_isa(c
, MIPS_CPU_ISA_M32R1
);
334 set_isa(c
, MIPS_CPU_ISA_M32R2
);
337 set_isa(c
, MIPS_CPU_ISA_M32R6
);
344 switch ((config0
& MIPS_CONF_AR
) >> 10) {
346 set_isa(c
, MIPS_CPU_ISA_M64R1
);
349 set_isa(c
, MIPS_CPU_ISA_M64R2
);
352 set_isa(c
, MIPS_CPU_ISA_M64R6
);
362 return config0
& MIPS_CONF_M
;
365 panic(unknown_isa
, config0
);
368 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
370 unsigned int config1
;
372 config1
= read_c0_config1();
374 if (config1
& MIPS_CONF1_MD
)
375 c
->ases
|= MIPS_ASE_MDMX
;
376 if (config1
& MIPS_CONF1_WR
)
377 c
->options
|= MIPS_CPU_WATCH
;
378 if (config1
& MIPS_CONF1_CA
)
379 c
->ases
|= MIPS_ASE_MIPS16
;
380 if (config1
& MIPS_CONF1_EP
)
381 c
->options
|= MIPS_CPU_EJTAG
;
382 if (config1
& MIPS_CONF1_FP
) {
383 c
->options
|= MIPS_CPU_FPU
;
384 c
->options
|= MIPS_CPU_32FPR
;
387 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
388 c
->tlbsizevtlb
= c
->tlbsize
;
389 c
->tlbsizeftlbsets
= 0;
392 return config1
& MIPS_CONF_M
;
395 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
397 unsigned int config2
;
399 config2
= read_c0_config2();
401 if (config2
& MIPS_CONF2_SL
)
402 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
404 return config2
& MIPS_CONF_M
;
407 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
409 unsigned int config3
;
411 config3
= read_c0_config3();
413 if (config3
& MIPS_CONF3_SM
) {
414 c
->ases
|= MIPS_ASE_SMARTMIPS
;
415 c
->options
|= MIPS_CPU_RIXI
;
417 if (config3
& MIPS_CONF3_RXI
)
418 c
->options
|= MIPS_CPU_RIXI
;
419 if (config3
& MIPS_CONF3_DSP
)
420 c
->ases
|= MIPS_ASE_DSP
;
421 if (config3
& MIPS_CONF3_DSP2P
)
422 c
->ases
|= MIPS_ASE_DSP2P
;
423 if (config3
& MIPS_CONF3_VINT
)
424 c
->options
|= MIPS_CPU_VINT
;
425 if (config3
& MIPS_CONF3_VEIC
)
426 c
->options
|= MIPS_CPU_VEIC
;
427 if (config3
& MIPS_CONF3_MT
)
428 c
->ases
|= MIPS_ASE_MIPSMT
;
429 if (config3
& MIPS_CONF3_ULRI
)
430 c
->options
|= MIPS_CPU_ULRI
;
431 if (config3
& MIPS_CONF3_ISA
)
432 c
->options
|= MIPS_CPU_MICROMIPS
;
433 if (config3
& MIPS_CONF3_VZ
)
434 c
->ases
|= MIPS_ASE_VZ
;
435 if (config3
& MIPS_CONF3_SC
)
436 c
->options
|= MIPS_CPU_SEGMENTS
;
437 if (config3
& MIPS_CONF3_MSA
)
438 c
->ases
|= MIPS_ASE_MSA
;
439 /* Only tested on 32-bit cores */
440 if ((config3
& MIPS_CONF3_PW
) && config_enabled(CONFIG_32BIT
)) {
442 c
->options
|= MIPS_CPU_HTW
;
444 if (config3
& MIPS_CONF3_CDMM
)
445 c
->options
|= MIPS_CPU_CDMM
;
447 return config3
& MIPS_CONF_M
;
450 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
452 unsigned int config4
;
454 unsigned int mmuextdef
;
455 unsigned int ftlb_page
= MIPS_CONF4_FTLBPAGESIZE
;
457 config4
= read_c0_config4();
460 if (((config4
& MIPS_CONF4_IE
) >> 29) == 2)
461 c
->options
|= MIPS_CPU_TLBINV
;
462 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
464 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
:
465 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
466 c
->tlbsizevtlb
= c
->tlbsize
;
468 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
:
470 ((config4
& MIPS_CONF4_VTLBSIZEEXT
) >>
471 MIPS_CONF4_VTLBSIZEEXT_SHIFT
) * 0x40;
472 c
->tlbsize
= c
->tlbsizevtlb
;
473 ftlb_page
= MIPS_CONF4_VFTLBPAGESIZE
;
475 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
:
476 if (mips_ftlb_disabled
)
478 newcf4
= (config4
& ~ftlb_page
) |
479 (page_size_ftlb(mmuextdef
) <<
480 MIPS_CONF4_FTLBPAGESIZE_SHIFT
);
481 write_c0_config4(newcf4
);
482 back_to_back_c0_hazard();
483 config4
= read_c0_config4();
484 if (config4
!= newcf4
) {
485 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
487 /* Switch FTLB off */
488 set_ftlb_enable(c
, 0);
491 c
->tlbsizeftlbsets
= 1 <<
492 ((config4
& MIPS_CONF4_FTLBSETS
) >>
493 MIPS_CONF4_FTLBSETS_SHIFT
);
494 c
->tlbsizeftlbways
= ((config4
& MIPS_CONF4_FTLBWAYS
) >>
495 MIPS_CONF4_FTLBWAYS_SHIFT
) + 2;
496 c
->tlbsize
+= c
->tlbsizeftlbways
* c
->tlbsizeftlbsets
;
497 mips_has_ftlb_configured
= 1;
502 c
->kscratch_mask
= (config4
>> 16) & 0xff;
504 return config4
& MIPS_CONF_M
;
507 static inline unsigned int decode_config5(struct cpuinfo_mips
*c
)
509 unsigned int config5
;
511 config5
= read_c0_config5();
512 config5
&= ~(MIPS_CONF5_UFR
| MIPS_CONF5_UFE
);
513 write_c0_config5(config5
);
515 if (config5
& MIPS_CONF5_EVA
)
516 c
->options
|= MIPS_CPU_EVA
;
517 if (config5
& MIPS_CONF5_MRP
)
518 c
->options
|= MIPS_CPU_MAAR
;
519 if (config5
& MIPS_CONF5_LLB
)
520 c
->options
|= MIPS_CPU_RW_LLB
;
522 return config5
& MIPS_CONF_M
;
525 static void decode_configs(struct cpuinfo_mips
*c
)
529 /* MIPS32 or MIPS64 compliant CPU. */
530 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
531 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
533 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
535 /* Enable FTLB if present and not disabled */
536 set_ftlb_enable(c
, !mips_ftlb_disabled
);
538 ok
= decode_config0(c
); /* Read Config registers. */
539 BUG_ON(!ok
); /* Arch spec violation! */
541 ok
= decode_config1(c
);
543 ok
= decode_config2(c
);
545 ok
= decode_config3(c
);
547 ok
= decode_config4(c
);
549 ok
= decode_config5(c
);
551 mips_probe_watch_registers(c
);
554 /* Enable the RIXI exceptions */
555 set_c0_pagegrain(PG_IEC
);
556 back_to_back_c0_hazard();
557 /* Verify the IEC bit is set */
558 if (read_c0_pagegrain() & PG_IEC
)
559 c
->options
|= MIPS_CPU_RIXIEX
;
562 #ifndef CONFIG_MIPS_CPS
563 if (cpu_has_mips_r2_r6
) {
564 c
->core
= get_ebase_cpunum();
566 c
->core
>>= fls(core_nvpes()) - 1;
571 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
574 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
576 switch (c
->processor_id
& PRID_IMP_MASK
) {
578 c
->cputype
= CPU_R2000
;
579 __cpu_name
[cpu
] = "R2000";
580 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
583 c
->options
|= MIPS_CPU_FPU
;
587 if ((c
->processor_id
& PRID_REV_MASK
) == PRID_REV_R3000A
) {
588 if (cpu_has_confreg()) {
589 c
->cputype
= CPU_R3081E
;
590 __cpu_name
[cpu
] = "R3081";
592 c
->cputype
= CPU_R3000A
;
593 __cpu_name
[cpu
] = "R3000A";
596 c
->cputype
= CPU_R3000
;
597 __cpu_name
[cpu
] = "R3000";
599 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
602 c
->options
|= MIPS_CPU_FPU
;
606 if (read_c0_config() & CONF_SC
) {
607 if ((c
->processor_id
& PRID_REV_MASK
) >=
609 c
->cputype
= CPU_R4400PC
;
610 __cpu_name
[cpu
] = "R4400PC";
612 c
->cputype
= CPU_R4000PC
;
613 __cpu_name
[cpu
] = "R4000PC";
616 int cca
= read_c0_config() & CONF_CM_CMASK
;
620 * SC and MC versions can't be reliably told apart,
621 * but only the latter support coherent caching
622 * modes so assume the firmware has set the KSEG0
623 * coherency attribute reasonably (if uncached, we
627 case CONF_CM_CACHABLE_CE
:
628 case CONF_CM_CACHABLE_COW
:
629 case CONF_CM_CACHABLE_CUW
:
636 if ((c
->processor_id
& PRID_REV_MASK
) >=
638 c
->cputype
= mc
? CPU_R4400MC
: CPU_R4400SC
;
639 __cpu_name
[cpu
] = mc
? "R4400MC" : "R4400SC";
641 c
->cputype
= mc
? CPU_R4000MC
: CPU_R4000SC
;
642 __cpu_name
[cpu
] = mc
? "R4000MC" : "R4000SC";
646 set_isa(c
, MIPS_CPU_ISA_III
);
647 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
648 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
652 case PRID_IMP_VR41XX
:
653 set_isa(c
, MIPS_CPU_ISA_III
);
654 c
->options
= R4K_OPTS
;
656 switch (c
->processor_id
& 0xf0) {
657 case PRID_REV_VR4111
:
658 c
->cputype
= CPU_VR4111
;
659 __cpu_name
[cpu
] = "NEC VR4111";
661 case PRID_REV_VR4121
:
662 c
->cputype
= CPU_VR4121
;
663 __cpu_name
[cpu
] = "NEC VR4121";
665 case PRID_REV_VR4122
:
666 if ((c
->processor_id
& 0xf) < 0x3) {
667 c
->cputype
= CPU_VR4122
;
668 __cpu_name
[cpu
] = "NEC VR4122";
670 c
->cputype
= CPU_VR4181A
;
671 __cpu_name
[cpu
] = "NEC VR4181A";
674 case PRID_REV_VR4130
:
675 if ((c
->processor_id
& 0xf) < 0x4) {
676 c
->cputype
= CPU_VR4131
;
677 __cpu_name
[cpu
] = "NEC VR4131";
679 c
->cputype
= CPU_VR4133
;
680 c
->options
|= MIPS_CPU_LLSC
;
681 __cpu_name
[cpu
] = "NEC VR4133";
685 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
686 c
->cputype
= CPU_VR41XX
;
687 __cpu_name
[cpu
] = "NEC Vr41xx";
692 c
->cputype
= CPU_R4300
;
693 __cpu_name
[cpu
] = "R4300";
694 set_isa(c
, MIPS_CPU_ISA_III
);
695 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
700 c
->cputype
= CPU_R4600
;
701 __cpu_name
[cpu
] = "R4600";
702 set_isa(c
, MIPS_CPU_ISA_III
);
703 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
710 * This processor doesn't have an MMU, so it's not
711 * "real easy" to run Linux on it. It is left purely
712 * for documentation. Commented out because it shares
713 * it's c0_prid id number with the TX3900.
715 c
->cputype
= CPU_R4650
;
716 __cpu_name
[cpu
] = "R4650";
717 set_isa(c
, MIPS_CPU_ISA_III
);
718 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
723 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
725 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
726 c
->cputype
= CPU_TX3927
;
727 __cpu_name
[cpu
] = "TX3927";
730 switch (c
->processor_id
& PRID_REV_MASK
) {
731 case PRID_REV_TX3912
:
732 c
->cputype
= CPU_TX3912
;
733 __cpu_name
[cpu
] = "TX3912";
736 case PRID_REV_TX3922
:
737 c
->cputype
= CPU_TX3922
;
738 __cpu_name
[cpu
] = "TX3922";
745 c
->cputype
= CPU_R4700
;
746 __cpu_name
[cpu
] = "R4700";
747 set_isa(c
, MIPS_CPU_ISA_III
);
748 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
753 c
->cputype
= CPU_TX49XX
;
754 __cpu_name
[cpu
] = "R49XX";
755 set_isa(c
, MIPS_CPU_ISA_III
);
756 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
757 if (!(c
->processor_id
& 0x08))
758 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
762 c
->cputype
= CPU_R5000
;
763 __cpu_name
[cpu
] = "R5000";
764 set_isa(c
, MIPS_CPU_ISA_IV
);
765 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
770 c
->cputype
= CPU_R5432
;
771 __cpu_name
[cpu
] = "R5432";
772 set_isa(c
, MIPS_CPU_ISA_IV
);
773 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
774 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
778 c
->cputype
= CPU_R5500
;
779 __cpu_name
[cpu
] = "R5500";
780 set_isa(c
, MIPS_CPU_ISA_IV
);
781 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
782 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
785 case PRID_IMP_NEVADA
:
786 c
->cputype
= CPU_NEVADA
;
787 __cpu_name
[cpu
] = "Nevada";
788 set_isa(c
, MIPS_CPU_ISA_IV
);
789 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
790 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
794 c
->cputype
= CPU_R6000
;
795 __cpu_name
[cpu
] = "R6000";
796 set_isa(c
, MIPS_CPU_ISA_II
);
797 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
801 case PRID_IMP_R6000A
:
802 c
->cputype
= CPU_R6000A
;
803 __cpu_name
[cpu
] = "R6000A";
804 set_isa(c
, MIPS_CPU_ISA_II
);
805 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
809 case PRID_IMP_RM7000
:
810 c
->cputype
= CPU_RM7000
;
811 __cpu_name
[cpu
] = "RM7000";
812 set_isa(c
, MIPS_CPU_ISA_IV
);
813 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
816 * Undocumented RM7000: Bit 29 in the info register of
817 * the RM7000 v2.0 indicates if the TLB has 48 or 64
820 * 29 1 => 64 entry JTLB
823 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
826 c
->cputype
= CPU_R8000
;
827 __cpu_name
[cpu
] = "RM8000";
828 set_isa(c
, MIPS_CPU_ISA_IV
);
829 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
830 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
832 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
834 case PRID_IMP_R10000
:
835 c
->cputype
= CPU_R10000
;
836 __cpu_name
[cpu
] = "R10000";
837 set_isa(c
, MIPS_CPU_ISA_IV
);
838 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
839 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
840 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
844 case PRID_IMP_R12000
:
845 c
->cputype
= CPU_R12000
;
846 __cpu_name
[cpu
] = "R12000";
847 set_isa(c
, MIPS_CPU_ISA_IV
);
848 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
849 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
850 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
854 case PRID_IMP_R14000
:
855 if (((c
->processor_id
>> 4) & 0x0f) > 2) {
856 c
->cputype
= CPU_R16000
;
857 __cpu_name
[cpu
] = "R16000";
859 c
->cputype
= CPU_R14000
;
860 __cpu_name
[cpu
] = "R14000";
862 set_isa(c
, MIPS_CPU_ISA_IV
);
863 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
864 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
865 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
869 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
870 switch (c
->processor_id
& PRID_REV_MASK
) {
871 case PRID_REV_LOONGSON2E
:
872 c
->cputype
= CPU_LOONGSON2
;
873 __cpu_name
[cpu
] = "ICT Loongson-2";
874 set_elf_platform(cpu
, "loongson2e");
875 set_isa(c
, MIPS_CPU_ISA_III
);
877 case PRID_REV_LOONGSON2F
:
878 c
->cputype
= CPU_LOONGSON2
;
879 __cpu_name
[cpu
] = "ICT Loongson-2";
880 set_elf_platform(cpu
, "loongson2f");
881 set_isa(c
, MIPS_CPU_ISA_III
);
883 case PRID_REV_LOONGSON3A
:
884 c
->cputype
= CPU_LOONGSON3
;
885 __cpu_name
[cpu
] = "ICT Loongson-3";
886 set_elf_platform(cpu
, "loongson3a");
887 set_isa(c
, MIPS_CPU_ISA_M64R1
);
889 case PRID_REV_LOONGSON3B_R1
:
890 case PRID_REV_LOONGSON3B_R2
:
891 c
->cputype
= CPU_LOONGSON3
;
892 __cpu_name
[cpu
] = "ICT Loongson-3";
893 set_elf_platform(cpu
, "loongson3b");
894 set_isa(c
, MIPS_CPU_ISA_M64R1
);
898 c
->options
= R4K_OPTS
|
899 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
902 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
904 case PRID_IMP_LOONGSON_32
: /* Loongson-1 */
907 c
->cputype
= CPU_LOONGSON1
;
909 switch (c
->processor_id
& PRID_REV_MASK
) {
910 case PRID_REV_LOONGSON1B
:
911 __cpu_name
[cpu
] = "Loongson 1B";
919 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
921 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
922 switch (c
->processor_id
& PRID_IMP_MASK
) {
923 case PRID_IMP_QEMU_GENERIC
:
924 c
->writecombine
= _CACHE_UNCACHED
;
925 c
->cputype
= CPU_QEMU_GENERIC
;
926 __cpu_name
[cpu
] = "MIPS GENERIC QEMU";
929 c
->cputype
= CPU_4KC
;
930 c
->writecombine
= _CACHE_UNCACHED
;
931 __cpu_name
[cpu
] = "MIPS 4Kc";
934 case PRID_IMP_4KECR2
:
935 c
->cputype
= CPU_4KEC
;
936 c
->writecombine
= _CACHE_UNCACHED
;
937 __cpu_name
[cpu
] = "MIPS 4KEc";
941 c
->cputype
= CPU_4KSC
;
942 c
->writecombine
= _CACHE_UNCACHED
;
943 __cpu_name
[cpu
] = "MIPS 4KSc";
946 c
->cputype
= CPU_5KC
;
947 c
->writecombine
= _CACHE_UNCACHED
;
948 __cpu_name
[cpu
] = "MIPS 5Kc";
951 c
->cputype
= CPU_5KE
;
952 c
->writecombine
= _CACHE_UNCACHED
;
953 __cpu_name
[cpu
] = "MIPS 5KE";
956 c
->cputype
= CPU_20KC
;
957 c
->writecombine
= _CACHE_UNCACHED
;
958 __cpu_name
[cpu
] = "MIPS 20Kc";
961 c
->cputype
= CPU_24K
;
962 c
->writecombine
= _CACHE_UNCACHED
;
963 __cpu_name
[cpu
] = "MIPS 24Kc";
966 c
->cputype
= CPU_24K
;
967 c
->writecombine
= _CACHE_UNCACHED
;
968 __cpu_name
[cpu
] = "MIPS 24KEc";
971 c
->cputype
= CPU_25KF
;
972 c
->writecombine
= _CACHE_UNCACHED
;
973 __cpu_name
[cpu
] = "MIPS 25Kc";
976 c
->cputype
= CPU_34K
;
977 c
->writecombine
= _CACHE_UNCACHED
;
978 __cpu_name
[cpu
] = "MIPS 34Kc";
981 c
->cputype
= CPU_74K
;
982 c
->writecombine
= _CACHE_UNCACHED
;
983 __cpu_name
[cpu
] = "MIPS 74Kc";
986 c
->cputype
= CPU_M14KC
;
987 c
->writecombine
= _CACHE_UNCACHED
;
988 __cpu_name
[cpu
] = "MIPS M14Kc";
990 case PRID_IMP_M14KEC
:
991 c
->cputype
= CPU_M14KEC
;
992 c
->writecombine
= _CACHE_UNCACHED
;
993 __cpu_name
[cpu
] = "MIPS M14KEc";
996 c
->cputype
= CPU_1004K
;
997 c
->writecombine
= _CACHE_UNCACHED
;
998 __cpu_name
[cpu
] = "MIPS 1004Kc";
1000 case PRID_IMP_1074K
:
1001 c
->cputype
= CPU_1074K
;
1002 c
->writecombine
= _CACHE_UNCACHED
;
1003 __cpu_name
[cpu
] = "MIPS 1074Kc";
1005 case PRID_IMP_INTERAPTIV_UP
:
1006 c
->cputype
= CPU_INTERAPTIV
;
1007 __cpu_name
[cpu
] = "MIPS interAptiv";
1009 case PRID_IMP_INTERAPTIV_MP
:
1010 c
->cputype
= CPU_INTERAPTIV
;
1011 __cpu_name
[cpu
] = "MIPS interAptiv (multi)";
1013 case PRID_IMP_PROAPTIV_UP
:
1014 c
->cputype
= CPU_PROAPTIV
;
1015 __cpu_name
[cpu
] = "MIPS proAptiv";
1017 case PRID_IMP_PROAPTIV_MP
:
1018 c
->cputype
= CPU_PROAPTIV
;
1019 __cpu_name
[cpu
] = "MIPS proAptiv (multi)";
1021 case PRID_IMP_P5600
:
1022 c
->cputype
= CPU_P5600
;
1023 __cpu_name
[cpu
] = "MIPS P5600";
1025 case PRID_IMP_M5150
:
1026 c
->cputype
= CPU_M5150
;
1027 __cpu_name
[cpu
] = "MIPS M5150";
1036 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
1039 switch (c
->processor_id
& PRID_IMP_MASK
) {
1040 case PRID_IMP_AU1_REV1
:
1041 case PRID_IMP_AU1_REV2
:
1042 c
->cputype
= CPU_ALCHEMY
;
1043 switch ((c
->processor_id
>> 24) & 0xff) {
1045 __cpu_name
[cpu
] = "Au1000";
1048 __cpu_name
[cpu
] = "Au1500";
1051 __cpu_name
[cpu
] = "Au1100";
1054 __cpu_name
[cpu
] = "Au1550";
1057 __cpu_name
[cpu
] = "Au1200";
1058 if ((c
->processor_id
& PRID_REV_MASK
) == 2)
1059 __cpu_name
[cpu
] = "Au1250";
1062 __cpu_name
[cpu
] = "Au1210";
1065 __cpu_name
[cpu
] = "Au1xxx";
1072 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
1076 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1077 switch (c
->processor_id
& PRID_IMP_MASK
) {
1079 c
->cputype
= CPU_SB1
;
1080 __cpu_name
[cpu
] = "SiByte SB1";
1081 /* FPU in pass1 is known to have issues. */
1082 if ((c
->processor_id
& PRID_REV_MASK
) < 0x02)
1083 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
1086 c
->cputype
= CPU_SB1A
;
1087 __cpu_name
[cpu
] = "SiByte SB1A";
1092 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
1095 switch (c
->processor_id
& PRID_IMP_MASK
) {
1096 case PRID_IMP_SR71000
:
1097 c
->cputype
= CPU_SR71000
;
1098 __cpu_name
[cpu
] = "Sandcraft SR71000";
1105 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
1108 switch (c
->processor_id
& PRID_IMP_MASK
) {
1109 case PRID_IMP_PR4450
:
1110 c
->cputype
= CPU_PR4450
;
1111 __cpu_name
[cpu
] = "Philips PR4450";
1112 set_isa(c
, MIPS_CPU_ISA_M32R1
);
1117 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
1120 switch (c
->processor_id
& PRID_IMP_MASK
) {
1121 case PRID_IMP_BMIPS32_REV4
:
1122 case PRID_IMP_BMIPS32_REV8
:
1123 c
->cputype
= CPU_BMIPS32
;
1124 __cpu_name
[cpu
] = "Broadcom BMIPS32";
1125 set_elf_platform(cpu
, "bmips32");
1127 case PRID_IMP_BMIPS3300
:
1128 case PRID_IMP_BMIPS3300_ALT
:
1129 case PRID_IMP_BMIPS3300_BUG
:
1130 c
->cputype
= CPU_BMIPS3300
;
1131 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
1132 set_elf_platform(cpu
, "bmips3300");
1134 case PRID_IMP_BMIPS43XX
: {
1135 int rev
= c
->processor_id
& PRID_REV_MASK
;
1137 if (rev
>= PRID_REV_BMIPS4380_LO
&&
1138 rev
<= PRID_REV_BMIPS4380_HI
) {
1139 c
->cputype
= CPU_BMIPS4380
;
1140 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
1141 set_elf_platform(cpu
, "bmips4380");
1143 c
->cputype
= CPU_BMIPS4350
;
1144 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
1145 set_elf_platform(cpu
, "bmips4350");
1149 case PRID_IMP_BMIPS5000
:
1150 case PRID_IMP_BMIPS5200
:
1151 c
->cputype
= CPU_BMIPS5000
;
1152 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
1153 set_elf_platform(cpu
, "bmips5000");
1154 c
->options
|= MIPS_CPU_ULRI
;
1159 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
1162 switch (c
->processor_id
& PRID_IMP_MASK
) {
1163 case PRID_IMP_CAVIUM_CN38XX
:
1164 case PRID_IMP_CAVIUM_CN31XX
:
1165 case PRID_IMP_CAVIUM_CN30XX
:
1166 c
->cputype
= CPU_CAVIUM_OCTEON
;
1167 __cpu_name
[cpu
] = "Cavium Octeon";
1169 case PRID_IMP_CAVIUM_CN58XX
:
1170 case PRID_IMP_CAVIUM_CN56XX
:
1171 case PRID_IMP_CAVIUM_CN50XX
:
1172 case PRID_IMP_CAVIUM_CN52XX
:
1173 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1174 __cpu_name
[cpu
] = "Cavium Octeon+";
1176 set_elf_platform(cpu
, "octeon");
1178 case PRID_IMP_CAVIUM_CN61XX
:
1179 case PRID_IMP_CAVIUM_CN63XX
:
1180 case PRID_IMP_CAVIUM_CN66XX
:
1181 case PRID_IMP_CAVIUM_CN68XX
:
1182 case PRID_IMP_CAVIUM_CNF71XX
:
1183 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1184 __cpu_name
[cpu
] = "Cavium Octeon II";
1185 set_elf_platform(cpu
, "octeon2");
1187 case PRID_IMP_CAVIUM_CN70XX
:
1188 case PRID_IMP_CAVIUM_CN78XX
:
1189 c
->cputype
= CPU_CAVIUM_OCTEON3
;
1190 __cpu_name
[cpu
] = "Cavium Octeon III";
1191 set_elf_platform(cpu
, "octeon3");
1194 printk(KERN_INFO
"Unknown Octeon chip!\n");
1195 c
->cputype
= CPU_UNKNOWN
;
1200 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1203 /* JZRISC does not implement the CP0 counter. */
1204 c
->options
&= ~MIPS_CPU_COUNTER
;
1205 BUG_ON(!__builtin_constant_p(cpu_has_counter
) || cpu_has_counter
);
1206 switch (c
->processor_id
& PRID_IMP_MASK
) {
1207 case PRID_IMP_JZRISC
:
1208 c
->cputype
= CPU_JZRISC
;
1209 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1210 __cpu_name
[cpu
] = "Ingenic JZRISC";
1213 panic("Unknown Ingenic Processor ID!");
1218 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1222 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_NETLOGIC_AU13XX
) {
1223 c
->cputype
= CPU_ALCHEMY
;
1224 __cpu_name
[cpu
] = "Au1300";
1225 /* following stuff is not for Alchemy */
1229 c
->options
= (MIPS_CPU_TLB
|
1237 switch (c
->processor_id
& PRID_IMP_MASK
) {
1238 case PRID_IMP_NETLOGIC_XLP2XX
:
1239 case PRID_IMP_NETLOGIC_XLP9XX
:
1240 case PRID_IMP_NETLOGIC_XLP5XX
:
1241 c
->cputype
= CPU_XLP
;
1242 __cpu_name
[cpu
] = "Broadcom XLPII";
1245 case PRID_IMP_NETLOGIC_XLP8XX
:
1246 case PRID_IMP_NETLOGIC_XLP3XX
:
1247 c
->cputype
= CPU_XLP
;
1248 __cpu_name
[cpu
] = "Netlogic XLP";
1251 case PRID_IMP_NETLOGIC_XLR732
:
1252 case PRID_IMP_NETLOGIC_XLR716
:
1253 case PRID_IMP_NETLOGIC_XLR532
:
1254 case PRID_IMP_NETLOGIC_XLR308
:
1255 case PRID_IMP_NETLOGIC_XLR532C
:
1256 case PRID_IMP_NETLOGIC_XLR516C
:
1257 case PRID_IMP_NETLOGIC_XLR508C
:
1258 case PRID_IMP_NETLOGIC_XLR308C
:
1259 c
->cputype
= CPU_XLR
;
1260 __cpu_name
[cpu
] = "Netlogic XLR";
1263 case PRID_IMP_NETLOGIC_XLS608
:
1264 case PRID_IMP_NETLOGIC_XLS408
:
1265 case PRID_IMP_NETLOGIC_XLS404
:
1266 case PRID_IMP_NETLOGIC_XLS208
:
1267 case PRID_IMP_NETLOGIC_XLS204
:
1268 case PRID_IMP_NETLOGIC_XLS108
:
1269 case PRID_IMP_NETLOGIC_XLS104
:
1270 case PRID_IMP_NETLOGIC_XLS616B
:
1271 case PRID_IMP_NETLOGIC_XLS608B
:
1272 case PRID_IMP_NETLOGIC_XLS416B
:
1273 case PRID_IMP_NETLOGIC_XLS412B
:
1274 case PRID_IMP_NETLOGIC_XLS408B
:
1275 case PRID_IMP_NETLOGIC_XLS404B
:
1276 c
->cputype
= CPU_XLR
;
1277 __cpu_name
[cpu
] = "Netlogic XLS";
1281 pr_info("Unknown Netlogic chip id [%02x]!\n",
1283 c
->cputype
= CPU_XLR
;
1287 if (c
->cputype
== CPU_XLP
) {
1288 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1289 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1290 /* This will be updated again after all threads are woken up */
1291 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1293 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1294 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1296 c
->kscratch_mask
= 0xf;
1300 /* For use by uaccess.h */
1302 EXPORT_SYMBOL(__ua_limit
);
1305 const char *__cpu_name
[NR_CPUS
];
1306 const char *__elf_platform
;
1308 void cpu_probe(void)
1310 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1311 unsigned int cpu
= smp_processor_id();
1313 c
->processor_id
= PRID_IMP_UNKNOWN
;
1314 c
->fpu_id
= FPIR_IMP_NONE
;
1315 c
->cputype
= CPU_UNKNOWN
;
1316 c
->writecombine
= _CACHE_UNCACHED
;
1318 c
->processor_id
= read_c0_prid();
1319 switch (c
->processor_id
& PRID_COMP_MASK
) {
1320 case PRID_COMP_LEGACY
:
1321 cpu_probe_legacy(c
, cpu
);
1323 case PRID_COMP_MIPS
:
1324 cpu_probe_mips(c
, cpu
);
1326 case PRID_COMP_ALCHEMY
:
1327 cpu_probe_alchemy(c
, cpu
);
1329 case PRID_COMP_SIBYTE
:
1330 cpu_probe_sibyte(c
, cpu
);
1332 case PRID_COMP_BROADCOM
:
1333 cpu_probe_broadcom(c
, cpu
);
1335 case PRID_COMP_SANDCRAFT
:
1336 cpu_probe_sandcraft(c
, cpu
);
1339 cpu_probe_nxp(c
, cpu
);
1341 case PRID_COMP_CAVIUM
:
1342 cpu_probe_cavium(c
, cpu
);
1344 case PRID_COMP_INGENIC
:
1345 cpu_probe_ingenic(c
, cpu
);
1347 case PRID_COMP_NETLOGIC
:
1348 cpu_probe_netlogic(c
, cpu
);
1352 BUG_ON(!__cpu_name
[cpu
]);
1353 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1356 * Platform code can force the cpu type to optimize code
1357 * generation. In that case be sure the cpu type is correctly
1358 * manually setup otherwise it could trigger some nasty bugs.
1360 BUG_ON(current_cpu_type() != c
->cputype
);
1362 if (mips_fpu_disabled
)
1363 c
->options
&= ~MIPS_CPU_FPU
;
1365 if (mips_dsp_disabled
)
1366 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1368 if (mips_htw_disabled
) {
1369 c
->options
&= ~MIPS_CPU_HTW
;
1370 write_c0_pwctl(read_c0_pwctl() &
1371 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
1374 if (c
->options
& MIPS_CPU_FPU
) {
1375 c
->fpu_id
= cpu_get_fpu_id();
1377 if (c
->isa_level
& cpu_has_mips_r
) {
1378 if (c
->fpu_id
& MIPS_FPIR_3D
)
1379 c
->ases
|= MIPS_ASE_MIPS3D
;
1380 if (c
->fpu_id
& MIPS_FPIR_FREP
)
1381 c
->options
|= MIPS_CPU_FRE
;
1385 if (cpu_has_mips_r2_r6
) {
1386 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1387 /* R2 has Performance Counter Interrupt indicator */
1388 c
->options
|= MIPS_CPU_PCI
;
1394 c
->msa_id
= cpu_get_msa_id();
1395 WARN(c
->msa_id
& MSA_IR_WRPF
,
1396 "Vector register partitioning unimplemented!");
1399 cpu_probe_vmbits(c
);
1403 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1407 void cpu_report(void)
1409 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1411 pr_info("CPU%d revision is: %08x (%s)\n",
1412 smp_processor_id(), c
->processor_id
, cpu_name_string());
1413 if (c
->options
& MIPS_CPU_FPU
)
1414 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);
1416 pr_info("MSA revision is: %08x\n", c
->msa_id
);