2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly
;
39 * Get the FPU Implementation/Revision.
41 static inline unsigned long cpu_get_fpu_id(void)
43 unsigned long tmp
, fpu_id
;
45 tmp
= read_c0_status();
46 __enable_fpu(FPU_AS_IS
);
47 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
53 * Check if the CPU has an external FPU.
55 static inline int __cpu_has_fpu(void)
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK
) != FPIR_IMP_NONE
;
60 static inline unsigned long cpu_get_msa_id(void)
62 unsigned long status
, msa_id
;
64 status
= read_c0_status();
65 __enable_fpu(FPU_64BIT
);
67 msa_id
= read_msa_ir();
69 write_c0_status(status
);
74 * Determine the FCSR mask for FPU hardware.
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips
*c
)
78 unsigned long sr
, mask
, fcsr
, fcsr0
, fcsr1
;
81 mask
= FPU_CSR_ALL_X
| FPU_CSR_ALL_E
| FPU_CSR_ALL_S
| FPU_CSR_RM
;
83 sr
= read_c0_status();
84 __enable_fpu(FPU_AS_IS
);
87 write_32bit_cp1_register(CP1_STATUS
, fcsr0
);
88 fcsr0
= read_32bit_cp1_register(CP1_STATUS
);
91 write_32bit_cp1_register(CP1_STATUS
, fcsr1
);
92 fcsr1
= read_32bit_cp1_register(CP1_STATUS
);
94 write_32bit_cp1_register(CP1_STATUS
, fcsr
);
98 c
->fpu_msk31
= ~(fcsr0
^ fcsr1
) & ~mask
;
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
105 static void cpu_set_fpu_2008(struct cpuinfo_mips
*c
)
107 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
108 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
109 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
110 unsigned long sr
, fir
, fcsr
, fcsr0
, fcsr1
;
112 sr
= read_c0_status();
113 __enable_fpu(FPU_AS_IS
);
115 fir
= read_32bit_cp1_register(CP1_REVISION
);
116 if (fir
& MIPS_FPIR_HAS2008
) {
117 fcsr
= read_32bit_cp1_register(CP1_STATUS
);
119 fcsr0
= fcsr
& ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
120 write_32bit_cp1_register(CP1_STATUS
, fcsr0
);
121 fcsr0
= read_32bit_cp1_register(CP1_STATUS
);
123 fcsr1
= fcsr
| FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
124 write_32bit_cp1_register(CP1_STATUS
, fcsr1
);
125 fcsr1
= read_32bit_cp1_register(CP1_STATUS
);
127 write_32bit_cp1_register(CP1_STATUS
, fcsr
);
129 if (!(fcsr0
& FPU_CSR_NAN2008
))
130 c
->options
|= MIPS_CPU_NAN_LEGACY
;
131 if (fcsr1
& FPU_CSR_NAN2008
)
132 c
->options
|= MIPS_CPU_NAN_2008
;
134 if ((fcsr0
^ fcsr1
) & FPU_CSR_ABS2008
)
135 c
->fpu_msk31
&= ~FPU_CSR_ABS2008
;
137 c
->fpu_csr31
|= fcsr
& FPU_CSR_ABS2008
;
139 if ((fcsr0
^ fcsr1
) & FPU_CSR_NAN2008
)
140 c
->fpu_msk31
&= ~FPU_CSR_NAN2008
;
142 c
->fpu_csr31
|= fcsr
& FPU_CSR_NAN2008
;
144 c
->options
|= MIPS_CPU_NAN_LEGACY
;
149 c
->options
|= MIPS_CPU_NAN_LEGACY
;
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
157 static enum { STRICT
, LEGACY
, STD2008
, RELAXED
} ieee754
= STRICT
;
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips
*c
)
167 c
->options
&= ~(MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
);
168 c
->fpu_csr31
&= ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
169 c
->fpu_msk31
&= ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
173 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
174 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
175 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
176 c
->options
|= MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
;
178 c
->options
|= MIPS_CPU_NAN_LEGACY
;
179 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
183 c
->options
|= MIPS_CPU_NAN_LEGACY
;
184 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
187 c
->options
|= MIPS_CPU_NAN_2008
;
188 c
->fpu_csr31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
189 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
192 c
->options
|= MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
;
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
201 static void cpu_set_nan_2008(struct cpuinfo_mips
*c
)
205 mips_use_nan_legacy
= !!cpu_has_nan_legacy
;
206 mips_use_nan_2008
= !!cpu_has_nan_2008
;
209 mips_use_nan_legacy
= !!cpu_has_nan_legacy
;
210 mips_use_nan_2008
= !cpu_has_nan_legacy
;
213 mips_use_nan_legacy
= !cpu_has_nan_2008
;
214 mips_use_nan_2008
= !!cpu_has_nan_2008
;
217 mips_use_nan_legacy
= true;
218 mips_use_nan_2008
= true;
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
232 static int __init
ieee754_setup(char *s
)
236 else if (!strcmp(s
, "strict"))
238 else if (!strcmp(s
, "legacy"))
240 else if (!strcmp(s
, "2008"))
242 else if (!strcmp(s
, "relaxed"))
247 if (!(boot_cpu_data
.options
& MIPS_CPU_FPU
))
248 cpu_set_nofpu_2008(&boot_cpu_data
);
249 cpu_set_nan_2008(&boot_cpu_data
);
254 early_param("ieee754", ieee754_setup
);
257 * Set the FIR feature flags for the FPU emulator.
259 static void cpu_set_nofpu_id(struct cpuinfo_mips
*c
)
264 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
265 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
266 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
267 value
|= MIPS_FPIR_D
| MIPS_FPIR_S
;
268 if (c
->isa_level
& (MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
269 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
270 value
|= MIPS_FPIR_F64
| MIPS_FPIR_L
| MIPS_FPIR_W
;
271 if (c
->options
& MIPS_CPU_NAN_2008
)
272 value
|= MIPS_FPIR_HAS2008
;
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31
;
280 * Set options for FPU hardware.
282 static void cpu_set_fpu_opts(struct cpuinfo_mips
*c
)
284 c
->fpu_id
= cpu_get_fpu_id();
285 mips_nofpu_msk31
= c
->fpu_msk31
;
287 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
288 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
289 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
290 if (c
->fpu_id
& MIPS_FPIR_3D
)
291 c
->ases
|= MIPS_ASE_MIPS3D
;
292 if (c
->fpu_id
& MIPS_FPIR_FREP
)
293 c
->options
|= MIPS_CPU_FRE
;
296 cpu_set_fpu_fcsr_mask(c
);
302 * Set options for the FPU emulator.
304 static void cpu_set_nofpu_opts(struct cpuinfo_mips
*c
)
306 c
->options
&= ~MIPS_CPU_FPU
;
307 c
->fpu_msk31
= mips_nofpu_msk31
;
309 cpu_set_nofpu_2008(c
);
314 static int mips_fpu_disabled
;
316 static int __init
fpu_disable(char *s
)
318 cpu_set_nofpu_opts(&boot_cpu_data
);
319 mips_fpu_disabled
= 1;
324 __setup("nofpu", fpu_disable
);
326 int mips_dsp_disabled
;
328 static int __init
dsp_disable(char *s
)
330 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
331 mips_dsp_disabled
= 1;
336 __setup("nodsp", dsp_disable
);
338 static int mips_htw_disabled
;
340 static int __init
htw_disable(char *s
)
342 mips_htw_disabled
= 1;
343 cpu_data
[0].options
&= ~MIPS_CPU_HTW
;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
350 __setup("nohtw", htw_disable
);
352 static int mips_ftlb_disabled
;
353 static int mips_has_ftlb_configured
;
355 static int set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
);
357 static int __init
ftlb_disable(char *s
)
359 unsigned int config4
, mmuextdef
;
362 * If the core hasn't done any FTLB configuration, there is nothing
365 if (!mips_has_ftlb_configured
)
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data
[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
374 back_to_back_c0_hazard();
376 config4
= read_c0_config4();
378 /* Check that FTLB has been disabled */
379 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef
== MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
387 mips_ftlb_disabled
= 1;
388 mips_has_ftlb_configured
= 0;
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
394 pr_info("FTLB has been disabled\n");
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
401 cpu_data
[0].tlbsize
-= cpu_data
[0].tlbsizeftlbways
*
402 cpu_data
[0].tlbsizeftlbsets
;
403 cpu_data
[0].tlbsizeftlbsets
= 0;
404 cpu_data
[0].tlbsizeftlbways
= 0;
409 __setup("noftlb", ftlb_disable
);
412 static inline void check_errata(void)
414 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
416 switch (current_cpu_type()) {
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
423 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
431 void __init
check_bugs32(void)
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
441 static inline int cpu_has_confreg(void)
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1
, size2
;
446 unsigned long cfg
= read_c0_conf();
448 size1
= r3k_cache_size(ST0_ISC
);
449 write_c0_conf(cfg
^ R30XX_CONF_AC
);
450 size2
= r3k_cache_size(ST0_ISC
);
452 return size1
!= size2
;
458 static inline void set_elf_platform(int cpu
, const char *plat
)
461 __elf_platform
= plat
;
464 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL
);
468 back_to_back_c0_hazard();
469 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
473 static void set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
476 case MIPS_CPU_ISA_M64R2
:
477 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
478 case MIPS_CPU_ISA_M64R1
:
479 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
481 c
->isa_level
|= MIPS_CPU_ISA_V
;
482 case MIPS_CPU_ISA_IV
:
483 c
->isa_level
|= MIPS_CPU_ISA_IV
;
484 case MIPS_CPU_ISA_III
:
485 c
->isa_level
|= MIPS_CPU_ISA_II
| MIPS_CPU_ISA_III
;
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6
:
490 c
->isa_level
|= MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
;
491 case MIPS_CPU_ISA_M32R6
:
492 c
->isa_level
|= MIPS_CPU_ISA_M32R6
;
493 /* Break here so we don't add incompatible ISAs */
495 case MIPS_CPU_ISA_M32R2
:
496 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
497 case MIPS_CPU_ISA_M32R1
:
498 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
499 case MIPS_CPU_ISA_II
:
500 c
->isa_level
|= MIPS_CPU_ISA_II
;
505 static char unknown_isa
[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips
*c
)
511 unsigned int probability
= c
->tlbsize
/ c
->tlbsizevtlb
;
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
520 * Use the linear midpoint as the probability threshold.
522 if (probability
>= 12)
524 else if (probability
>= 6)
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
534 static int set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
)
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c
->cputype
) {
543 /* proAptiv & related cores use Config6 to enable the FTLB */
544 config
= read_c0_config6();
545 /* Clear the old probability value */
546 config
&= ~(3 << MIPS_CONF6_FTLBP_SHIFT
);
549 write_c0_config6(config
|
550 (calculate_ftlb_probability(c
)
551 << MIPS_CONF6_FTLBP_SHIFT
)
552 | MIPS_CONF6_FTLBEN
);
555 write_c0_config6(config
& ~MIPS_CONF6_FTLBEN
);
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config
= read_c0_config7();
560 /* Clear the old probability value */
561 config
&= ~(3 << MIPS_CONF7_FTLBP_SHIFT
);
562 write_c0_config7(config
| (calculate_ftlb_probability(c
)
563 << MIPS_CONF7_FTLBP_SHIFT
));
566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB
| LOONGSON_DIAG_DTLB
|
568 LOONGSON_DIAG_VTLB
| LOONGSON_DIAG_FTLB
);
569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config
= read_c0_config6();
573 write_c0_config6(config
& ~MIPS_CONF6_FTLBDIS
);
576 write_c0_config6(config
| MIPS_CONF6_FTLBDIS
);
585 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
587 unsigned int config0
;
590 config0
= read_c0_config();
593 * Look for Standard TLB or Dual VTLB and FTLB
595 mt
= config0
& MIPS_CONF_MT
;
596 if (mt
== MIPS_CONF_MT_TLB
)
597 c
->options
|= MIPS_CPU_TLB
;
598 else if (mt
== MIPS_CONF_MT_FTLB
)
599 c
->options
|= MIPS_CPU_TLB
| MIPS_CPU_FTLB
;
601 isa
= (config0
& MIPS_CONF_AT
) >> 13;
604 switch ((config0
& MIPS_CONF_AR
) >> 10) {
606 set_isa(c
, MIPS_CPU_ISA_M32R1
);
609 set_isa(c
, MIPS_CPU_ISA_M32R2
);
612 set_isa(c
, MIPS_CPU_ISA_M32R6
);
619 switch ((config0
& MIPS_CONF_AR
) >> 10) {
621 set_isa(c
, MIPS_CPU_ISA_M64R1
);
624 set_isa(c
, MIPS_CPU_ISA_M64R2
);
627 set_isa(c
, MIPS_CPU_ISA_M64R6
);
637 return config0
& MIPS_CONF_M
;
640 panic(unknown_isa
, config0
);
643 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
645 unsigned int config1
;
647 config1
= read_c0_config1();
649 if (config1
& MIPS_CONF1_MD
)
650 c
->ases
|= MIPS_ASE_MDMX
;
651 if (config1
& MIPS_CONF1_PC
)
652 c
->options
|= MIPS_CPU_PERF
;
653 if (config1
& MIPS_CONF1_WR
)
654 c
->options
|= MIPS_CPU_WATCH
;
655 if (config1
& MIPS_CONF1_CA
)
656 c
->ases
|= MIPS_ASE_MIPS16
;
657 if (config1
& MIPS_CONF1_EP
)
658 c
->options
|= MIPS_CPU_EJTAG
;
659 if (config1
& MIPS_CONF1_FP
) {
660 c
->options
|= MIPS_CPU_FPU
;
661 c
->options
|= MIPS_CPU_32FPR
;
664 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
665 c
->tlbsizevtlb
= c
->tlbsize
;
666 c
->tlbsizeftlbsets
= 0;
669 return config1
& MIPS_CONF_M
;
672 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
674 unsigned int config2
;
676 config2
= read_c0_config2();
678 if (config2
& MIPS_CONF2_SL
)
679 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
681 return config2
& MIPS_CONF_M
;
684 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
686 unsigned int config3
;
688 config3
= read_c0_config3();
690 if (config3
& MIPS_CONF3_SM
) {
691 c
->ases
|= MIPS_ASE_SMARTMIPS
;
692 c
->options
|= MIPS_CPU_RIXI
| MIPS_CPU_CTXTC
;
694 if (config3
& MIPS_CONF3_RXI
)
695 c
->options
|= MIPS_CPU_RIXI
;
696 if (config3
& MIPS_CONF3_CTXTC
)
697 c
->options
|= MIPS_CPU_CTXTC
;
698 if (config3
& MIPS_CONF3_DSP
)
699 c
->ases
|= MIPS_ASE_DSP
;
700 if (config3
& MIPS_CONF3_DSP2P
) {
701 c
->ases
|= MIPS_ASE_DSP2P
;
703 c
->ases
|= MIPS_ASE_DSP3
;
705 if (config3
& MIPS_CONF3_VINT
)
706 c
->options
|= MIPS_CPU_VINT
;
707 if (config3
& MIPS_CONF3_VEIC
)
708 c
->options
|= MIPS_CPU_VEIC
;
709 if (config3
& MIPS_CONF3_LPA
)
710 c
->options
|= MIPS_CPU_LPA
;
711 if (config3
& MIPS_CONF3_MT
)
712 c
->ases
|= MIPS_ASE_MIPSMT
;
713 if (config3
& MIPS_CONF3_ULRI
)
714 c
->options
|= MIPS_CPU_ULRI
;
715 if (config3
& MIPS_CONF3_ISA
)
716 c
->options
|= MIPS_CPU_MICROMIPS
;
717 if (config3
& MIPS_CONF3_VZ
)
718 c
->ases
|= MIPS_ASE_VZ
;
719 if (config3
& MIPS_CONF3_SC
)
720 c
->options
|= MIPS_CPU_SEGMENTS
;
721 if (config3
& MIPS_CONF3_BI
)
722 c
->options
|= MIPS_CPU_BADINSTR
;
723 if (config3
& MIPS_CONF3_BP
)
724 c
->options
|= MIPS_CPU_BADINSTRP
;
725 if (config3
& MIPS_CONF3_MSA
)
726 c
->ases
|= MIPS_ASE_MSA
;
727 if (config3
& MIPS_CONF3_PW
) {
729 c
->options
|= MIPS_CPU_HTW
;
731 if (config3
& MIPS_CONF3_CDMM
)
732 c
->options
|= MIPS_CPU_CDMM
;
733 if (config3
& MIPS_CONF3_SP
)
734 c
->options
|= MIPS_CPU_SP
;
736 return config3
& MIPS_CONF_M
;
739 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
741 unsigned int config4
;
743 unsigned int mmuextdef
;
744 unsigned int ftlb_page
= MIPS_CONF4_FTLBPAGESIZE
;
745 unsigned long asid_mask
;
747 config4
= read_c0_config4();
750 if (((config4
& MIPS_CONF4_IE
) >> 29) == 2)
751 c
->options
|= MIPS_CPU_TLBINV
;
754 * R6 has dropped the MMUExtDef field from config4.
755 * On R6 the fields always describe the FTLB, and only if it is
756 * present according to Config.MT.
758 if (!cpu_has_mips_r6
)
759 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
760 else if (cpu_has_ftlb
)
761 mmuextdef
= MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
;
766 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
:
767 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
768 c
->tlbsizevtlb
= c
->tlbsize
;
770 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
:
772 ((config4
& MIPS_CONF4_VTLBSIZEEXT
) >>
773 MIPS_CONF4_VTLBSIZEEXT_SHIFT
) * 0x40;
774 c
->tlbsize
= c
->tlbsizevtlb
;
775 ftlb_page
= MIPS_CONF4_VFTLBPAGESIZE
;
777 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
:
778 if (mips_ftlb_disabled
)
780 newcf4
= (config4
& ~ftlb_page
) |
781 (page_size_ftlb(mmuextdef
) <<
782 MIPS_CONF4_FTLBPAGESIZE_SHIFT
);
783 write_c0_config4(newcf4
);
784 back_to_back_c0_hazard();
785 config4
= read_c0_config4();
786 if (config4
!= newcf4
) {
787 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
789 /* Switch FTLB off */
790 set_ftlb_enable(c
, 0);
793 c
->tlbsizeftlbsets
= 1 <<
794 ((config4
& MIPS_CONF4_FTLBSETS
) >>
795 MIPS_CONF4_FTLBSETS_SHIFT
);
796 c
->tlbsizeftlbways
= ((config4
& MIPS_CONF4_FTLBWAYS
) >>
797 MIPS_CONF4_FTLBWAYS_SHIFT
) + 2;
798 c
->tlbsize
+= c
->tlbsizeftlbways
* c
->tlbsizeftlbsets
;
799 mips_has_ftlb_configured
= 1;
804 c
->kscratch_mask
= (config4
& MIPS_CONF4_KSCREXIST
)
805 >> MIPS_CONF4_KSCREXIST_SHIFT
;
807 asid_mask
= MIPS_ENTRYHI_ASID
;
808 if (config4
& MIPS_CONF4_AE
)
809 asid_mask
|= MIPS_ENTRYHI_ASIDX
;
810 set_cpu_asid_mask(c
, asid_mask
);
813 * Warn if the computed ASID mask doesn't match the mask the kernel
814 * is built for. This may indicate either a serious problem or an
815 * easy optimisation opportunity, but either way should be addressed.
817 WARN_ON(asid_mask
!= cpu_asid_mask(c
));
819 return config4
& MIPS_CONF_M
;
822 static inline unsigned int decode_config5(struct cpuinfo_mips
*c
)
824 unsigned int config5
;
826 config5
= read_c0_config5();
827 config5
&= ~(MIPS_CONF5_UFR
| MIPS_CONF5_UFE
);
828 write_c0_config5(config5
);
830 if (config5
& MIPS_CONF5_EVA
)
831 c
->options
|= MIPS_CPU_EVA
;
832 if (config5
& MIPS_CONF5_MRP
)
833 c
->options
|= MIPS_CPU_MAAR
;
834 if (config5
& MIPS_CONF5_LLB
)
835 c
->options
|= MIPS_CPU_RW_LLB
;
837 if (config5
& MIPS_CONF5_MVH
)
838 c
->options
|= MIPS_CPU_XPA
;
840 if (cpu_has_mips_r6
&& (config5
& MIPS_CONF5_VP
))
841 c
->options
|= MIPS_CPU_VP
;
843 return config5
& MIPS_CONF_M
;
846 static void decode_configs(struct cpuinfo_mips
*c
)
850 /* MIPS32 or MIPS64 compliant CPU. */
851 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
852 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
854 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
856 /* Enable FTLB if present and not disabled */
857 set_ftlb_enable(c
, !mips_ftlb_disabled
);
859 ok
= decode_config0(c
); /* Read Config registers. */
860 BUG_ON(!ok
); /* Arch spec violation! */
862 ok
= decode_config1(c
);
864 ok
= decode_config2(c
);
866 ok
= decode_config3(c
);
868 ok
= decode_config4(c
);
870 ok
= decode_config5(c
);
872 /* Probe the EBase.WG bit */
873 if (cpu_has_mips_r2_r6
) {
877 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
878 ebase
= cpu_has_mips64r6
? read_c0_ebase_64()
879 : (s32
)read_c0_ebase();
880 if (ebase
& MIPS_EBASE_WG
) {
881 /* WG bit already set, we can avoid the clumsy probe */
882 c
->options
|= MIPS_CPU_EBASE_WG
;
884 /* Its UNDEFINED to change EBase while BEV=0 */
885 status
= read_c0_status();
886 write_c0_status(status
| ST0_BEV
);
889 * On pre-r6 cores, this may well clobber the upper bits
890 * of EBase. This is hard to avoid without potentially
891 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
893 if (cpu_has_mips64r6
)
894 write_c0_ebase_64(ebase
| MIPS_EBASE_WG
);
896 write_c0_ebase(ebase
| MIPS_EBASE_WG
);
897 back_to_back_c0_hazard();
899 write_c0_status(status
);
900 if (read_c0_ebase() & MIPS_EBASE_WG
) {
901 c
->options
|= MIPS_CPU_EBASE_WG
;
902 write_c0_ebase(ebase
);
907 mips_probe_watch_registers(c
);
909 #ifndef CONFIG_MIPS_CPS
910 if (cpu_has_mips_r2_r6
) {
911 c
->core
= get_ebase_cpunum();
913 c
->core
>>= fls(core_nvpes()) - 1;
919 * Probe for certain guest capabilities by writing config bits and reading back.
920 * Finally write back the original value.
922 #define probe_gc0_config(name, maxconf, bits) \
925 tmp = read_gc0_##name(); \
926 write_gc0_##name(tmp | (bits)); \
927 back_to_back_c0_hazard(); \
928 maxconf = read_gc0_##name(); \
929 write_gc0_##name(tmp); \
933 * Probe for dynamic guest capabilities by changing certain config bits and
934 * reading back to see if they change. Finally write back the original value.
936 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
938 maxconf = read_gc0_##name(); \
939 write_gc0_##name(maxconf ^ (bits)); \
940 back_to_back_c0_hazard(); \
941 dynconf = maxconf ^ read_gc0_##name(); \
942 write_gc0_##name(maxconf); \
943 maxconf |= dynconf; \
946 static inline unsigned int decode_guest_config0(struct cpuinfo_mips
*c
)
948 unsigned int config0
;
950 probe_gc0_config(config
, config0
, MIPS_CONF_M
);
952 if (config0
& MIPS_CONF_M
)
953 c
->guest
.conf
|= BIT(1);
954 return config0
& MIPS_CONF_M
;
957 static inline unsigned int decode_guest_config1(struct cpuinfo_mips
*c
)
959 unsigned int config1
, config1_dyn
;
961 probe_gc0_config_dyn(config1
, config1
, config1_dyn
,
962 MIPS_CONF_M
| MIPS_CONF1_PC
| MIPS_CONF1_WR
|
965 if (config1
& MIPS_CONF1_FP
)
966 c
->guest
.options
|= MIPS_CPU_FPU
;
967 if (config1_dyn
& MIPS_CONF1_FP
)
968 c
->guest
.options_dyn
|= MIPS_CPU_FPU
;
970 if (config1
& MIPS_CONF1_WR
)
971 c
->guest
.options
|= MIPS_CPU_WATCH
;
972 if (config1_dyn
& MIPS_CONF1_WR
)
973 c
->guest
.options_dyn
|= MIPS_CPU_WATCH
;
975 if (config1
& MIPS_CONF1_PC
)
976 c
->guest
.options
|= MIPS_CPU_PERF
;
977 if (config1_dyn
& MIPS_CONF1_PC
)
978 c
->guest
.options_dyn
|= MIPS_CPU_PERF
;
980 if (config1
& MIPS_CONF_M
)
981 c
->guest
.conf
|= BIT(2);
982 return config1
& MIPS_CONF_M
;
985 static inline unsigned int decode_guest_config2(struct cpuinfo_mips
*c
)
987 unsigned int config2
;
989 probe_gc0_config(config2
, config2
, MIPS_CONF_M
);
991 if (config2
& MIPS_CONF_M
)
992 c
->guest
.conf
|= BIT(3);
993 return config2
& MIPS_CONF_M
;
996 static inline unsigned int decode_guest_config3(struct cpuinfo_mips
*c
)
998 unsigned int config3
, config3_dyn
;
1000 probe_gc0_config_dyn(config3
, config3
, config3_dyn
,
1001 MIPS_CONF_M
| MIPS_CONF3_MSA
| MIPS_CONF3_CTXTC
);
1003 if (config3
& MIPS_CONF3_CTXTC
)
1004 c
->guest
.options
|= MIPS_CPU_CTXTC
;
1005 if (config3_dyn
& MIPS_CONF3_CTXTC
)
1006 c
->guest
.options_dyn
|= MIPS_CPU_CTXTC
;
1008 if (config3
& MIPS_CONF3_PW
)
1009 c
->guest
.options
|= MIPS_CPU_HTW
;
1011 if (config3
& MIPS_CONF3_SC
)
1012 c
->guest
.options
|= MIPS_CPU_SEGMENTS
;
1014 if (config3
& MIPS_CONF3_BI
)
1015 c
->guest
.options
|= MIPS_CPU_BADINSTR
;
1016 if (config3
& MIPS_CONF3_BP
)
1017 c
->guest
.options
|= MIPS_CPU_BADINSTRP
;
1019 if (config3
& MIPS_CONF3_MSA
)
1020 c
->guest
.ases
|= MIPS_ASE_MSA
;
1021 if (config3_dyn
& MIPS_CONF3_MSA
)
1022 c
->guest
.ases_dyn
|= MIPS_ASE_MSA
;
1024 if (config3
& MIPS_CONF_M
)
1025 c
->guest
.conf
|= BIT(4);
1026 return config3
& MIPS_CONF_M
;
1029 static inline unsigned int decode_guest_config4(struct cpuinfo_mips
*c
)
1031 unsigned int config4
;
1033 probe_gc0_config(config4
, config4
,
1034 MIPS_CONF_M
| MIPS_CONF4_KSCREXIST
);
1036 c
->guest
.kscratch_mask
= (config4
& MIPS_CONF4_KSCREXIST
)
1037 >> MIPS_CONF4_KSCREXIST_SHIFT
;
1039 if (config4
& MIPS_CONF_M
)
1040 c
->guest
.conf
|= BIT(5);
1041 return config4
& MIPS_CONF_M
;
1044 static inline unsigned int decode_guest_config5(struct cpuinfo_mips
*c
)
1046 unsigned int config5
, config5_dyn
;
1048 probe_gc0_config_dyn(config5
, config5
, config5_dyn
,
1049 MIPS_CONF_M
| MIPS_CONF5_MRP
);
1051 if (config5
& MIPS_CONF5_MRP
)
1052 c
->guest
.options
|= MIPS_CPU_MAAR
;
1053 if (config5_dyn
& MIPS_CONF5_MRP
)
1054 c
->guest
.options_dyn
|= MIPS_CPU_MAAR
;
1056 if (config5
& MIPS_CONF5_LLB
)
1057 c
->guest
.options
|= MIPS_CPU_RW_LLB
;
1059 if (config5
& MIPS_CONF_M
)
1060 c
->guest
.conf
|= BIT(6);
1061 return config5
& MIPS_CONF_M
;
1064 static inline void decode_guest_configs(struct cpuinfo_mips
*c
)
1068 ok
= decode_guest_config0(c
);
1070 ok
= decode_guest_config1(c
);
1072 ok
= decode_guest_config2(c
);
1074 ok
= decode_guest_config3(c
);
1076 ok
= decode_guest_config4(c
);
1078 decode_guest_config5(c
);
1081 static inline void cpu_probe_guestctl0(struct cpuinfo_mips
*c
)
1083 unsigned int guestctl0
, temp
;
1085 guestctl0
= read_c0_guestctl0();
1087 if (guestctl0
& MIPS_GCTL0_G0E
)
1088 c
->options
|= MIPS_CPU_GUESTCTL0EXT
;
1089 if (guestctl0
& MIPS_GCTL0_G1
)
1090 c
->options
|= MIPS_CPU_GUESTCTL1
;
1091 if (guestctl0
& MIPS_GCTL0_G2
)
1092 c
->options
|= MIPS_CPU_GUESTCTL2
;
1093 if (!(guestctl0
& MIPS_GCTL0_RAD
)) {
1094 c
->options
|= MIPS_CPU_GUESTID
;
1097 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1098 * first, otherwise all data accesses will be fully virtualised
1099 * as if they were performed by guest mode.
1101 write_c0_guestctl1(0);
1104 write_c0_guestctl0(guestctl0
| MIPS_GCTL0_DRG
);
1105 back_to_back_c0_hazard();
1106 temp
= read_c0_guestctl0();
1108 if (temp
& MIPS_GCTL0_DRG
) {
1109 write_c0_guestctl0(guestctl0
);
1110 c
->options
|= MIPS_CPU_DRG
;
1115 static inline void cpu_probe_guestctl1(struct cpuinfo_mips
*c
)
1117 if (cpu_has_guestid
) {
1118 /* determine the number of bits of GuestID available */
1119 write_c0_guestctl1(MIPS_GCTL1_ID
);
1120 back_to_back_c0_hazard();
1121 c
->guestid_mask
= (read_c0_guestctl1() & MIPS_GCTL1_ID
)
1122 >> MIPS_GCTL1_ID_SHIFT
;
1123 write_c0_guestctl1(0);
1127 static inline void cpu_probe_gtoffset(struct cpuinfo_mips
*c
)
1129 /* determine the number of bits of GTOffset available */
1130 write_c0_gtoffset(0xffffffff);
1131 back_to_back_c0_hazard();
1132 c
->gtoffset_mask
= read_c0_gtoffset();
1133 write_c0_gtoffset(0);
1136 static inline void cpu_probe_vz(struct cpuinfo_mips
*c
)
1138 cpu_probe_guestctl0(c
);
1139 if (cpu_has_guestctl1
)
1140 cpu_probe_guestctl1(c
);
1142 cpu_probe_gtoffset(c
);
1144 decode_guest_configs(c
);
1147 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1150 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
1152 switch (c
->processor_id
& PRID_IMP_MASK
) {
1153 case PRID_IMP_R2000
:
1154 c
->cputype
= CPU_R2000
;
1155 __cpu_name
[cpu
] = "R2000";
1156 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1157 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
1159 if (__cpu_has_fpu())
1160 c
->options
|= MIPS_CPU_FPU
;
1163 case PRID_IMP_R3000
:
1164 if ((c
->processor_id
& PRID_REV_MASK
) == PRID_REV_R3000A
) {
1165 if (cpu_has_confreg()) {
1166 c
->cputype
= CPU_R3081E
;
1167 __cpu_name
[cpu
] = "R3081";
1169 c
->cputype
= CPU_R3000A
;
1170 __cpu_name
[cpu
] = "R3000A";
1173 c
->cputype
= CPU_R3000
;
1174 __cpu_name
[cpu
] = "R3000";
1176 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1177 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
1179 if (__cpu_has_fpu())
1180 c
->options
|= MIPS_CPU_FPU
;
1183 case PRID_IMP_R4000
:
1184 if (read_c0_config() & CONF_SC
) {
1185 if ((c
->processor_id
& PRID_REV_MASK
) >=
1187 c
->cputype
= CPU_R4400PC
;
1188 __cpu_name
[cpu
] = "R4400PC";
1190 c
->cputype
= CPU_R4000PC
;
1191 __cpu_name
[cpu
] = "R4000PC";
1194 int cca
= read_c0_config() & CONF_CM_CMASK
;
1198 * SC and MC versions can't be reliably told apart,
1199 * but only the latter support coherent caching
1200 * modes so assume the firmware has set the KSEG0
1201 * coherency attribute reasonably (if uncached, we
1205 case CONF_CM_CACHABLE_CE
:
1206 case CONF_CM_CACHABLE_COW
:
1207 case CONF_CM_CACHABLE_CUW
:
1214 if ((c
->processor_id
& PRID_REV_MASK
) >=
1216 c
->cputype
= mc
? CPU_R4400MC
: CPU_R4400SC
;
1217 __cpu_name
[cpu
] = mc
? "R4400MC" : "R4400SC";
1219 c
->cputype
= mc
? CPU_R4000MC
: CPU_R4000SC
;
1220 __cpu_name
[cpu
] = mc
? "R4000MC" : "R4000SC";
1224 set_isa(c
, MIPS_CPU_ISA_III
);
1225 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1226 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1227 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
1231 case PRID_IMP_VR41XX
:
1232 set_isa(c
, MIPS_CPU_ISA_III
);
1233 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1234 c
->options
= R4K_OPTS
;
1236 switch (c
->processor_id
& 0xf0) {
1237 case PRID_REV_VR4111
:
1238 c
->cputype
= CPU_VR4111
;
1239 __cpu_name
[cpu
] = "NEC VR4111";
1241 case PRID_REV_VR4121
:
1242 c
->cputype
= CPU_VR4121
;
1243 __cpu_name
[cpu
] = "NEC VR4121";
1245 case PRID_REV_VR4122
:
1246 if ((c
->processor_id
& 0xf) < 0x3) {
1247 c
->cputype
= CPU_VR4122
;
1248 __cpu_name
[cpu
] = "NEC VR4122";
1250 c
->cputype
= CPU_VR4181A
;
1251 __cpu_name
[cpu
] = "NEC VR4181A";
1254 case PRID_REV_VR4130
:
1255 if ((c
->processor_id
& 0xf) < 0x4) {
1256 c
->cputype
= CPU_VR4131
;
1257 __cpu_name
[cpu
] = "NEC VR4131";
1259 c
->cputype
= CPU_VR4133
;
1260 c
->options
|= MIPS_CPU_LLSC
;
1261 __cpu_name
[cpu
] = "NEC VR4133";
1265 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
1266 c
->cputype
= CPU_VR41XX
;
1267 __cpu_name
[cpu
] = "NEC Vr41xx";
1271 case PRID_IMP_R4300
:
1272 c
->cputype
= CPU_R4300
;
1273 __cpu_name
[cpu
] = "R4300";
1274 set_isa(c
, MIPS_CPU_ISA_III
);
1275 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1276 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1280 case PRID_IMP_R4600
:
1281 c
->cputype
= CPU_R4600
;
1282 __cpu_name
[cpu
] = "R4600";
1283 set_isa(c
, MIPS_CPU_ISA_III
);
1284 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1285 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1290 case PRID_IMP_R4650
:
1292 * This processor doesn't have an MMU, so it's not
1293 * "real easy" to run Linux on it. It is left purely
1294 * for documentation. Commented out because it shares
1295 * it's c0_prid id number with the TX3900.
1297 c
->cputype
= CPU_R4650
;
1298 __cpu_name
[cpu
] = "R4650";
1299 set_isa(c
, MIPS_CPU_ISA_III
);
1300 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1301 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
1306 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1307 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
1309 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
1310 c
->cputype
= CPU_TX3927
;
1311 __cpu_name
[cpu
] = "TX3927";
1314 switch (c
->processor_id
& PRID_REV_MASK
) {
1315 case PRID_REV_TX3912
:
1316 c
->cputype
= CPU_TX3912
;
1317 __cpu_name
[cpu
] = "TX3912";
1320 case PRID_REV_TX3922
:
1321 c
->cputype
= CPU_TX3922
;
1322 __cpu_name
[cpu
] = "TX3922";
1328 case PRID_IMP_R4700
:
1329 c
->cputype
= CPU_R4700
;
1330 __cpu_name
[cpu
] = "R4700";
1331 set_isa(c
, MIPS_CPU_ISA_III
);
1332 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1333 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1338 c
->cputype
= CPU_TX49XX
;
1339 __cpu_name
[cpu
] = "R49XX";
1340 set_isa(c
, MIPS_CPU_ISA_III
);
1341 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1342 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
1343 if (!(c
->processor_id
& 0x08))
1344 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
1347 case PRID_IMP_R5000
:
1348 c
->cputype
= CPU_R5000
;
1349 __cpu_name
[cpu
] = "R5000";
1350 set_isa(c
, MIPS_CPU_ISA_IV
);
1351 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1355 case PRID_IMP_R5432
:
1356 c
->cputype
= CPU_R5432
;
1357 __cpu_name
[cpu
] = "R5432";
1358 set_isa(c
, MIPS_CPU_ISA_IV
);
1359 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1360 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
1363 case PRID_IMP_R5500
:
1364 c
->cputype
= CPU_R5500
;
1365 __cpu_name
[cpu
] = "R5500";
1366 set_isa(c
, MIPS_CPU_ISA_IV
);
1367 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1368 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
1371 case PRID_IMP_NEVADA
:
1372 c
->cputype
= CPU_NEVADA
;
1373 __cpu_name
[cpu
] = "Nevada";
1374 set_isa(c
, MIPS_CPU_ISA_IV
);
1375 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1376 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
1379 case PRID_IMP_R6000
:
1380 c
->cputype
= CPU_R6000
;
1381 __cpu_name
[cpu
] = "R6000";
1382 set_isa(c
, MIPS_CPU_ISA_II
);
1383 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1384 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
1388 case PRID_IMP_R6000A
:
1389 c
->cputype
= CPU_R6000A
;
1390 __cpu_name
[cpu
] = "R6000A";
1391 set_isa(c
, MIPS_CPU_ISA_II
);
1392 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1393 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
1397 case PRID_IMP_RM7000
:
1398 c
->cputype
= CPU_RM7000
;
1399 __cpu_name
[cpu
] = "RM7000";
1400 set_isa(c
, MIPS_CPU_ISA_IV
);
1401 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1404 * Undocumented RM7000: Bit 29 in the info register of
1405 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1408 * 29 1 => 64 entry JTLB
1409 * 0 => 48 entry JTLB
1411 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
1413 case PRID_IMP_R8000
:
1414 c
->cputype
= CPU_R8000
;
1415 __cpu_name
[cpu
] = "RM8000";
1416 set_isa(c
, MIPS_CPU_ISA_IV
);
1417 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
1418 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1420 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
1422 case PRID_IMP_R10000
:
1423 c
->cputype
= CPU_R10000
;
1424 __cpu_name
[cpu
] = "R10000";
1425 set_isa(c
, MIPS_CPU_ISA_IV
);
1426 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1427 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1428 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1432 case PRID_IMP_R12000
:
1433 c
->cputype
= CPU_R12000
;
1434 __cpu_name
[cpu
] = "R12000";
1435 set_isa(c
, MIPS_CPU_ISA_IV
);
1436 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1437 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1438 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1439 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
1442 case PRID_IMP_R14000
:
1443 if (((c
->processor_id
>> 4) & 0x0f) > 2) {
1444 c
->cputype
= CPU_R16000
;
1445 __cpu_name
[cpu
] = "R16000";
1447 c
->cputype
= CPU_R14000
;
1448 __cpu_name
[cpu
] = "R14000";
1450 set_isa(c
, MIPS_CPU_ISA_IV
);
1451 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1452 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1453 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1454 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
1457 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
1458 switch (c
->processor_id
& PRID_REV_MASK
) {
1459 case PRID_REV_LOONGSON2E
:
1460 c
->cputype
= CPU_LOONGSON2
;
1461 __cpu_name
[cpu
] = "ICT Loongson-2";
1462 set_elf_platform(cpu
, "loongson2e");
1463 set_isa(c
, MIPS_CPU_ISA_III
);
1464 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1466 case PRID_REV_LOONGSON2F
:
1467 c
->cputype
= CPU_LOONGSON2
;
1468 __cpu_name
[cpu
] = "ICT Loongson-2";
1469 set_elf_platform(cpu
, "loongson2f");
1470 set_isa(c
, MIPS_CPU_ISA_III
);
1471 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1473 case PRID_REV_LOONGSON3A_R1
:
1474 c
->cputype
= CPU_LOONGSON3
;
1475 __cpu_name
[cpu
] = "ICT Loongson-3";
1476 set_elf_platform(cpu
, "loongson3a");
1477 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1479 case PRID_REV_LOONGSON3B_R1
:
1480 case PRID_REV_LOONGSON3B_R2
:
1481 c
->cputype
= CPU_LOONGSON3
;
1482 __cpu_name
[cpu
] = "ICT Loongson-3";
1483 set_elf_platform(cpu
, "loongson3b");
1484 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1488 c
->options
= R4K_OPTS
|
1489 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
1492 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1494 case PRID_IMP_LOONGSON_32
: /* Loongson-1 */
1497 c
->cputype
= CPU_LOONGSON1
;
1499 switch (c
->processor_id
& PRID_REV_MASK
) {
1500 case PRID_REV_LOONGSON1B
:
1501 __cpu_name
[cpu
] = "Loongson 1B";
1509 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
1511 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1512 switch (c
->processor_id
& PRID_IMP_MASK
) {
1513 case PRID_IMP_QEMU_GENERIC
:
1514 c
->writecombine
= _CACHE_UNCACHED
;
1515 c
->cputype
= CPU_QEMU_GENERIC
;
1516 __cpu_name
[cpu
] = "MIPS GENERIC QEMU";
1519 c
->cputype
= CPU_4KC
;
1520 c
->writecombine
= _CACHE_UNCACHED
;
1521 __cpu_name
[cpu
] = "MIPS 4Kc";
1524 case PRID_IMP_4KECR2
:
1525 c
->cputype
= CPU_4KEC
;
1526 c
->writecombine
= _CACHE_UNCACHED
;
1527 __cpu_name
[cpu
] = "MIPS 4KEc";
1531 c
->cputype
= CPU_4KSC
;
1532 c
->writecombine
= _CACHE_UNCACHED
;
1533 __cpu_name
[cpu
] = "MIPS 4KSc";
1536 c
->cputype
= CPU_5KC
;
1537 c
->writecombine
= _CACHE_UNCACHED
;
1538 __cpu_name
[cpu
] = "MIPS 5Kc";
1541 c
->cputype
= CPU_5KE
;
1542 c
->writecombine
= _CACHE_UNCACHED
;
1543 __cpu_name
[cpu
] = "MIPS 5KE";
1546 c
->cputype
= CPU_20KC
;
1547 c
->writecombine
= _CACHE_UNCACHED
;
1548 __cpu_name
[cpu
] = "MIPS 20Kc";
1551 c
->cputype
= CPU_24K
;
1552 c
->writecombine
= _CACHE_UNCACHED
;
1553 __cpu_name
[cpu
] = "MIPS 24Kc";
1556 c
->cputype
= CPU_24K
;
1557 c
->writecombine
= _CACHE_UNCACHED
;
1558 __cpu_name
[cpu
] = "MIPS 24KEc";
1561 c
->cputype
= CPU_25KF
;
1562 c
->writecombine
= _CACHE_UNCACHED
;
1563 __cpu_name
[cpu
] = "MIPS 25Kc";
1566 c
->cputype
= CPU_34K
;
1567 c
->writecombine
= _CACHE_UNCACHED
;
1568 __cpu_name
[cpu
] = "MIPS 34Kc";
1571 c
->cputype
= CPU_74K
;
1572 c
->writecombine
= _CACHE_UNCACHED
;
1573 __cpu_name
[cpu
] = "MIPS 74Kc";
1575 case PRID_IMP_M14KC
:
1576 c
->cputype
= CPU_M14KC
;
1577 c
->writecombine
= _CACHE_UNCACHED
;
1578 __cpu_name
[cpu
] = "MIPS M14Kc";
1580 case PRID_IMP_M14KEC
:
1581 c
->cputype
= CPU_M14KEC
;
1582 c
->writecombine
= _CACHE_UNCACHED
;
1583 __cpu_name
[cpu
] = "MIPS M14KEc";
1585 case PRID_IMP_1004K
:
1586 c
->cputype
= CPU_1004K
;
1587 c
->writecombine
= _CACHE_UNCACHED
;
1588 __cpu_name
[cpu
] = "MIPS 1004Kc";
1590 case PRID_IMP_1074K
:
1591 c
->cputype
= CPU_1074K
;
1592 c
->writecombine
= _CACHE_UNCACHED
;
1593 __cpu_name
[cpu
] = "MIPS 1074Kc";
1595 case PRID_IMP_INTERAPTIV_UP
:
1596 c
->cputype
= CPU_INTERAPTIV
;
1597 __cpu_name
[cpu
] = "MIPS interAptiv";
1599 case PRID_IMP_INTERAPTIV_MP
:
1600 c
->cputype
= CPU_INTERAPTIV
;
1601 __cpu_name
[cpu
] = "MIPS interAptiv (multi)";
1603 case PRID_IMP_PROAPTIV_UP
:
1604 c
->cputype
= CPU_PROAPTIV
;
1605 __cpu_name
[cpu
] = "MIPS proAptiv";
1607 case PRID_IMP_PROAPTIV_MP
:
1608 c
->cputype
= CPU_PROAPTIV
;
1609 __cpu_name
[cpu
] = "MIPS proAptiv (multi)";
1611 case PRID_IMP_P5600
:
1612 c
->cputype
= CPU_P5600
;
1613 __cpu_name
[cpu
] = "MIPS P5600";
1615 case PRID_IMP_P6600
:
1616 c
->cputype
= CPU_P6600
;
1617 __cpu_name
[cpu
] = "MIPS P6600";
1619 case PRID_IMP_I6400
:
1620 c
->cputype
= CPU_I6400
;
1621 __cpu_name
[cpu
] = "MIPS I6400";
1623 case PRID_IMP_M5150
:
1624 c
->cputype
= CPU_M5150
;
1625 __cpu_name
[cpu
] = "MIPS M5150";
1627 case PRID_IMP_M6250
:
1628 c
->cputype
= CPU_M6250
;
1629 __cpu_name
[cpu
] = "MIPS M6250";
1638 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
1641 switch (c
->processor_id
& PRID_IMP_MASK
) {
1642 case PRID_IMP_AU1_REV1
:
1643 case PRID_IMP_AU1_REV2
:
1644 c
->cputype
= CPU_ALCHEMY
;
1645 switch ((c
->processor_id
>> 24) & 0xff) {
1647 __cpu_name
[cpu
] = "Au1000";
1650 __cpu_name
[cpu
] = "Au1500";
1653 __cpu_name
[cpu
] = "Au1100";
1656 __cpu_name
[cpu
] = "Au1550";
1659 __cpu_name
[cpu
] = "Au1200";
1660 if ((c
->processor_id
& PRID_REV_MASK
) == 2)
1661 __cpu_name
[cpu
] = "Au1250";
1664 __cpu_name
[cpu
] = "Au1210";
1667 __cpu_name
[cpu
] = "Au1xxx";
1674 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
1678 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1679 switch (c
->processor_id
& PRID_IMP_MASK
) {
1681 c
->cputype
= CPU_SB1
;
1682 __cpu_name
[cpu
] = "SiByte SB1";
1683 /* FPU in pass1 is known to have issues. */
1684 if ((c
->processor_id
& PRID_REV_MASK
) < 0x02)
1685 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
1688 c
->cputype
= CPU_SB1A
;
1689 __cpu_name
[cpu
] = "SiByte SB1A";
1694 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
1697 switch (c
->processor_id
& PRID_IMP_MASK
) {
1698 case PRID_IMP_SR71000
:
1699 c
->cputype
= CPU_SR71000
;
1700 __cpu_name
[cpu
] = "Sandcraft SR71000";
1707 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
1710 switch (c
->processor_id
& PRID_IMP_MASK
) {
1711 case PRID_IMP_PR4450
:
1712 c
->cputype
= CPU_PR4450
;
1713 __cpu_name
[cpu
] = "Philips PR4450";
1714 set_isa(c
, MIPS_CPU_ISA_M32R1
);
1719 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
1722 switch (c
->processor_id
& PRID_IMP_MASK
) {
1723 case PRID_IMP_BMIPS32_REV4
:
1724 case PRID_IMP_BMIPS32_REV8
:
1725 c
->cputype
= CPU_BMIPS32
;
1726 __cpu_name
[cpu
] = "Broadcom BMIPS32";
1727 set_elf_platform(cpu
, "bmips32");
1729 case PRID_IMP_BMIPS3300
:
1730 case PRID_IMP_BMIPS3300_ALT
:
1731 case PRID_IMP_BMIPS3300_BUG
:
1732 c
->cputype
= CPU_BMIPS3300
;
1733 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
1734 set_elf_platform(cpu
, "bmips3300");
1736 case PRID_IMP_BMIPS43XX
: {
1737 int rev
= c
->processor_id
& PRID_REV_MASK
;
1739 if (rev
>= PRID_REV_BMIPS4380_LO
&&
1740 rev
<= PRID_REV_BMIPS4380_HI
) {
1741 c
->cputype
= CPU_BMIPS4380
;
1742 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
1743 set_elf_platform(cpu
, "bmips4380");
1744 c
->options
|= MIPS_CPU_RIXI
;
1746 c
->cputype
= CPU_BMIPS4350
;
1747 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
1748 set_elf_platform(cpu
, "bmips4350");
1752 case PRID_IMP_BMIPS5000
:
1753 case PRID_IMP_BMIPS5200
:
1754 c
->cputype
= CPU_BMIPS5000
;
1755 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_BMIPS5200
)
1756 __cpu_name
[cpu
] = "Broadcom BMIPS5200";
1758 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
1759 set_elf_platform(cpu
, "bmips5000");
1760 c
->options
|= MIPS_CPU_ULRI
| MIPS_CPU_RIXI
;
1765 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
1768 switch (c
->processor_id
& PRID_IMP_MASK
) {
1769 case PRID_IMP_CAVIUM_CN38XX
:
1770 case PRID_IMP_CAVIUM_CN31XX
:
1771 case PRID_IMP_CAVIUM_CN30XX
:
1772 c
->cputype
= CPU_CAVIUM_OCTEON
;
1773 __cpu_name
[cpu
] = "Cavium Octeon";
1775 case PRID_IMP_CAVIUM_CN58XX
:
1776 case PRID_IMP_CAVIUM_CN56XX
:
1777 case PRID_IMP_CAVIUM_CN50XX
:
1778 case PRID_IMP_CAVIUM_CN52XX
:
1779 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1780 __cpu_name
[cpu
] = "Cavium Octeon+";
1782 set_elf_platform(cpu
, "octeon");
1784 case PRID_IMP_CAVIUM_CN61XX
:
1785 case PRID_IMP_CAVIUM_CN63XX
:
1786 case PRID_IMP_CAVIUM_CN66XX
:
1787 case PRID_IMP_CAVIUM_CN68XX
:
1788 case PRID_IMP_CAVIUM_CNF71XX
:
1789 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1790 __cpu_name
[cpu
] = "Cavium Octeon II";
1791 set_elf_platform(cpu
, "octeon2");
1793 case PRID_IMP_CAVIUM_CN70XX
:
1794 case PRID_IMP_CAVIUM_CN73XX
:
1795 case PRID_IMP_CAVIUM_CNF75XX
:
1796 case PRID_IMP_CAVIUM_CN78XX
:
1797 c
->cputype
= CPU_CAVIUM_OCTEON3
;
1798 __cpu_name
[cpu
] = "Cavium Octeon III";
1799 set_elf_platform(cpu
, "octeon3");
1802 printk(KERN_INFO
"Unknown Octeon chip!\n");
1803 c
->cputype
= CPU_UNKNOWN
;
1808 static inline void cpu_probe_loongson(struct cpuinfo_mips
*c
, unsigned int cpu
)
1810 switch (c
->processor_id
& PRID_IMP_MASK
) {
1811 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
1812 switch (c
->processor_id
& PRID_REV_MASK
) {
1813 case PRID_REV_LOONGSON3A_R2
:
1814 c
->cputype
= CPU_LOONGSON3
;
1815 __cpu_name
[cpu
] = "ICT Loongson-3";
1816 set_elf_platform(cpu
, "loongson3a");
1817 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1822 c
->options
|= MIPS_CPU_TLBINV
| MIPS_CPU_LDPTE
;
1823 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1826 panic("Unknown Loongson Processor ID!");
1831 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1834 /* JZRISC does not implement the CP0 counter. */
1835 c
->options
&= ~MIPS_CPU_COUNTER
;
1836 BUG_ON(!__builtin_constant_p(cpu_has_counter
) || cpu_has_counter
);
1837 switch (c
->processor_id
& PRID_IMP_MASK
) {
1838 case PRID_IMP_JZRISC
:
1839 c
->cputype
= CPU_JZRISC
;
1840 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1841 __cpu_name
[cpu
] = "Ingenic JZRISC";
1844 panic("Unknown Ingenic Processor ID!");
1849 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1853 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_NETLOGIC_AU13XX
) {
1854 c
->cputype
= CPU_ALCHEMY
;
1855 __cpu_name
[cpu
] = "Au1300";
1856 /* following stuff is not for Alchemy */
1860 c
->options
= (MIPS_CPU_TLB
|
1868 switch (c
->processor_id
& PRID_IMP_MASK
) {
1869 case PRID_IMP_NETLOGIC_XLP2XX
:
1870 case PRID_IMP_NETLOGIC_XLP9XX
:
1871 case PRID_IMP_NETLOGIC_XLP5XX
:
1872 c
->cputype
= CPU_XLP
;
1873 __cpu_name
[cpu
] = "Broadcom XLPII";
1876 case PRID_IMP_NETLOGIC_XLP8XX
:
1877 case PRID_IMP_NETLOGIC_XLP3XX
:
1878 c
->cputype
= CPU_XLP
;
1879 __cpu_name
[cpu
] = "Netlogic XLP";
1882 case PRID_IMP_NETLOGIC_XLR732
:
1883 case PRID_IMP_NETLOGIC_XLR716
:
1884 case PRID_IMP_NETLOGIC_XLR532
:
1885 case PRID_IMP_NETLOGIC_XLR308
:
1886 case PRID_IMP_NETLOGIC_XLR532C
:
1887 case PRID_IMP_NETLOGIC_XLR516C
:
1888 case PRID_IMP_NETLOGIC_XLR508C
:
1889 case PRID_IMP_NETLOGIC_XLR308C
:
1890 c
->cputype
= CPU_XLR
;
1891 __cpu_name
[cpu
] = "Netlogic XLR";
1894 case PRID_IMP_NETLOGIC_XLS608
:
1895 case PRID_IMP_NETLOGIC_XLS408
:
1896 case PRID_IMP_NETLOGIC_XLS404
:
1897 case PRID_IMP_NETLOGIC_XLS208
:
1898 case PRID_IMP_NETLOGIC_XLS204
:
1899 case PRID_IMP_NETLOGIC_XLS108
:
1900 case PRID_IMP_NETLOGIC_XLS104
:
1901 case PRID_IMP_NETLOGIC_XLS616B
:
1902 case PRID_IMP_NETLOGIC_XLS608B
:
1903 case PRID_IMP_NETLOGIC_XLS416B
:
1904 case PRID_IMP_NETLOGIC_XLS412B
:
1905 case PRID_IMP_NETLOGIC_XLS408B
:
1906 case PRID_IMP_NETLOGIC_XLS404B
:
1907 c
->cputype
= CPU_XLR
;
1908 __cpu_name
[cpu
] = "Netlogic XLS";
1912 pr_info("Unknown Netlogic chip id [%02x]!\n",
1914 c
->cputype
= CPU_XLR
;
1918 if (c
->cputype
== CPU_XLP
) {
1919 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1920 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1921 /* This will be updated again after all threads are woken up */
1922 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1924 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1925 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1927 c
->kscratch_mask
= 0xf;
1931 /* For use by uaccess.h */
1933 EXPORT_SYMBOL(__ua_limit
);
1936 const char *__cpu_name
[NR_CPUS
];
1937 const char *__elf_platform
;
1939 void cpu_probe(void)
1941 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1942 unsigned int cpu
= smp_processor_id();
1944 c
->processor_id
= PRID_IMP_UNKNOWN
;
1945 c
->fpu_id
= FPIR_IMP_NONE
;
1946 c
->cputype
= CPU_UNKNOWN
;
1947 c
->writecombine
= _CACHE_UNCACHED
;
1949 c
->fpu_csr31
= FPU_CSR_RN
;
1950 c
->fpu_msk31
= FPU_CSR_RSVD
| FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
1952 c
->processor_id
= read_c0_prid();
1953 switch (c
->processor_id
& PRID_COMP_MASK
) {
1954 case PRID_COMP_LEGACY
:
1955 cpu_probe_legacy(c
, cpu
);
1957 case PRID_COMP_MIPS
:
1958 cpu_probe_mips(c
, cpu
);
1960 case PRID_COMP_ALCHEMY
:
1961 cpu_probe_alchemy(c
, cpu
);
1963 case PRID_COMP_SIBYTE
:
1964 cpu_probe_sibyte(c
, cpu
);
1966 case PRID_COMP_BROADCOM
:
1967 cpu_probe_broadcom(c
, cpu
);
1969 case PRID_COMP_SANDCRAFT
:
1970 cpu_probe_sandcraft(c
, cpu
);
1973 cpu_probe_nxp(c
, cpu
);
1975 case PRID_COMP_CAVIUM
:
1976 cpu_probe_cavium(c
, cpu
);
1978 case PRID_COMP_LOONGSON
:
1979 cpu_probe_loongson(c
, cpu
);
1981 case PRID_COMP_INGENIC_D0
:
1982 case PRID_COMP_INGENIC_D1
:
1983 case PRID_COMP_INGENIC_E1
:
1984 cpu_probe_ingenic(c
, cpu
);
1986 case PRID_COMP_NETLOGIC
:
1987 cpu_probe_netlogic(c
, cpu
);
1991 BUG_ON(!__cpu_name
[cpu
]);
1992 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1995 * Platform code can force the cpu type to optimize code
1996 * generation. In that case be sure the cpu type is correctly
1997 * manually setup otherwise it could trigger some nasty bugs.
1999 BUG_ON(current_cpu_type() != c
->cputype
);
2002 /* Enable the RIXI exceptions */
2003 set_c0_pagegrain(PG_IEC
);
2004 back_to_back_c0_hazard();
2005 /* Verify the IEC bit is set */
2006 if (read_c0_pagegrain() & PG_IEC
)
2007 c
->options
|= MIPS_CPU_RIXIEX
;
2010 if (mips_fpu_disabled
)
2011 c
->options
&= ~MIPS_CPU_FPU
;
2013 if (mips_dsp_disabled
)
2014 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
2016 if (mips_htw_disabled
) {
2017 c
->options
&= ~MIPS_CPU_HTW
;
2018 write_c0_pwctl(read_c0_pwctl() &
2019 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
2022 if (c
->options
& MIPS_CPU_FPU
)
2023 cpu_set_fpu_opts(c
);
2025 cpu_set_nofpu_opts(c
);
2027 if (cpu_has_bp_ghist
)
2028 write_c0_r10k_diag(read_c0_r10k_diag() |
2031 if (cpu_has_mips_r2_r6
) {
2032 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2033 /* R2 has Performance Counter Interrupt indicator */
2034 c
->options
|= MIPS_CPU_PCI
;
2039 if (cpu_has_mips_r6
)
2040 elf_hwcap
|= HWCAP_MIPS_R6
;
2043 c
->msa_id
= cpu_get_msa_id();
2044 WARN(c
->msa_id
& MSA_IR_WRPF
,
2045 "Vector register partitioning unimplemented!");
2046 elf_hwcap
|= HWCAP_MIPS_MSA
;
2052 cpu_probe_vmbits(c
);
2056 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
2060 void cpu_report(void)
2062 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
2064 pr_info("CPU%d revision is: %08x (%s)\n",
2065 smp_processor_id(), c
->processor_id
, cpu_name_string());
2066 if (c
->options
& MIPS_CPU_FPU
)
2067 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);
2069 pr_info("MSA revision is: %08x\n", c
->msa_id
);