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MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulation
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37
38 /*
39 * Get the FPU Implementation/Revision.
40 */
41 static inline unsigned long cpu_get_fpu_id(void)
42 {
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50 }
51
52 /*
53 * Check if the CPU has an external FPU.
54 */
55 static inline int __cpu_has_fpu(void)
56 {
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58 }
59
60 static inline unsigned long cpu_get_msa_id(void)
61 {
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71 }
72
73 /*
74 * Determine the FCSR mask for FPU hardware.
75 */
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77 {
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99 }
100
101 /*
102 * Set the FIR feature flags for the FPU emulator.
103 */
104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
105 {
106 u32 value;
107
108 value = 0;
109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_D | MIPS_FPIR_S;
113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
116 if (c->options & MIPS_CPU_NAN_2008)
117 value |= MIPS_FPIR_HAS2008;
118 c->fpu_id = value;
119 }
120
121 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
122 static unsigned int mips_nofpu_msk31;
123
124 /*
125 * Set options for FPU hardware.
126 */
127 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
128 {
129 c->fpu_id = cpu_get_fpu_id();
130 mips_nofpu_msk31 = c->fpu_msk31;
131
132 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
133 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
134 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
135 if (c->fpu_id & MIPS_FPIR_3D)
136 c->ases |= MIPS_ASE_MIPS3D;
137 if (c->fpu_id & MIPS_FPIR_FREP)
138 c->options |= MIPS_CPU_FRE;
139 }
140
141 cpu_set_fpu_fcsr_mask(c);
142 c->options |= MIPS_CPU_NAN_LEGACY;
143 }
144
145 /*
146 * Set options for the FPU emulator.
147 */
148 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
149 {
150 c->options &= ~MIPS_CPU_FPU;
151 c->fpu_msk31 = mips_nofpu_msk31;
152
153 c->options |= MIPS_CPU_NAN_LEGACY;
154 cpu_set_nofpu_id(c);
155 }
156
157 static int mips_fpu_disabled;
158
159 static int __init fpu_disable(char *s)
160 {
161 cpu_set_nofpu_opts(&boot_cpu_data);
162 mips_fpu_disabled = 1;
163
164 return 1;
165 }
166
167 __setup("nofpu", fpu_disable);
168
169 int mips_dsp_disabled;
170
171 static int __init dsp_disable(char *s)
172 {
173 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
174 mips_dsp_disabled = 1;
175
176 return 1;
177 }
178
179 __setup("nodsp", dsp_disable);
180
181 static int mips_htw_disabled;
182
183 static int __init htw_disable(char *s)
184 {
185 mips_htw_disabled = 1;
186 cpu_data[0].options &= ~MIPS_CPU_HTW;
187 write_c0_pwctl(read_c0_pwctl() &
188 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
189
190 return 1;
191 }
192
193 __setup("nohtw", htw_disable);
194
195 static int mips_ftlb_disabled;
196 static int mips_has_ftlb_configured;
197
198 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
199
200 static int __init ftlb_disable(char *s)
201 {
202 unsigned int config4, mmuextdef;
203
204 /*
205 * If the core hasn't done any FTLB configuration, there is nothing
206 * for us to do here.
207 */
208 if (!mips_has_ftlb_configured)
209 return 1;
210
211 /* Disable it in the boot cpu */
212 if (set_ftlb_enable(&cpu_data[0], 0)) {
213 pr_warn("Can't turn FTLB off\n");
214 return 1;
215 }
216
217 back_to_back_c0_hazard();
218
219 config4 = read_c0_config4();
220
221 /* Check that FTLB has been disabled */
222 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
223 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
224 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
225 /* This should never happen */
226 pr_warn("FTLB could not be disabled!\n");
227 return 1;
228 }
229
230 mips_ftlb_disabled = 1;
231 mips_has_ftlb_configured = 0;
232
233 /*
234 * noftlb is mainly used for debug purposes so print
235 * an informative message instead of using pr_debug()
236 */
237 pr_info("FTLB has been disabled\n");
238
239 /*
240 * Some of these bits are duplicated in the decode_config4.
241 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
242 * once FTLB has been disabled so undo what decode_config4 did.
243 */
244 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
245 cpu_data[0].tlbsizeftlbsets;
246 cpu_data[0].tlbsizeftlbsets = 0;
247 cpu_data[0].tlbsizeftlbways = 0;
248
249 return 1;
250 }
251
252 __setup("noftlb", ftlb_disable);
253
254
255 static inline void check_errata(void)
256 {
257 struct cpuinfo_mips *c = &current_cpu_data;
258
259 switch (current_cpu_type()) {
260 case CPU_34K:
261 /*
262 * Erratum "RPS May Cause Incorrect Instruction Execution"
263 * This code only handles VPE0, any SMP/RTOS code
264 * making use of VPE1 will be responsable for that VPE.
265 */
266 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
267 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
268 break;
269 default:
270 break;
271 }
272 }
273
274 void __init check_bugs32(void)
275 {
276 check_errata();
277 }
278
279 /*
280 * Probe whether cpu has config register by trying to play with
281 * alternate cache bit and see whether it matters.
282 * It's used by cpu_probe to distinguish between R3000A and R3081.
283 */
284 static inline int cpu_has_confreg(void)
285 {
286 #ifdef CONFIG_CPU_R3000
287 extern unsigned long r3k_cache_size(unsigned long);
288 unsigned long size1, size2;
289 unsigned long cfg = read_c0_conf();
290
291 size1 = r3k_cache_size(ST0_ISC);
292 write_c0_conf(cfg ^ R30XX_CONF_AC);
293 size2 = r3k_cache_size(ST0_ISC);
294 write_c0_conf(cfg);
295 return size1 != size2;
296 #else
297 return 0;
298 #endif
299 }
300
301 static inline void set_elf_platform(int cpu, const char *plat)
302 {
303 if (cpu == 0)
304 __elf_platform = plat;
305 }
306
307 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
308 {
309 #ifdef __NEED_VMBITS_PROBE
310 write_c0_entryhi(0x3fffffffffffe000ULL);
311 back_to_back_c0_hazard();
312 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
313 #endif
314 }
315
316 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
317 {
318 switch (isa) {
319 case MIPS_CPU_ISA_M64R2:
320 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
321 case MIPS_CPU_ISA_M64R1:
322 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
323 case MIPS_CPU_ISA_V:
324 c->isa_level |= MIPS_CPU_ISA_V;
325 case MIPS_CPU_ISA_IV:
326 c->isa_level |= MIPS_CPU_ISA_IV;
327 case MIPS_CPU_ISA_III:
328 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
329 break;
330
331 /* R6 incompatible with everything else */
332 case MIPS_CPU_ISA_M64R6:
333 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
334 case MIPS_CPU_ISA_M32R6:
335 c->isa_level |= MIPS_CPU_ISA_M32R6;
336 /* Break here so we don't add incompatible ISAs */
337 break;
338 case MIPS_CPU_ISA_M32R2:
339 c->isa_level |= MIPS_CPU_ISA_M32R2;
340 case MIPS_CPU_ISA_M32R1:
341 c->isa_level |= MIPS_CPU_ISA_M32R1;
342 case MIPS_CPU_ISA_II:
343 c->isa_level |= MIPS_CPU_ISA_II;
344 break;
345 }
346 }
347
348 static char unknown_isa[] = KERN_ERR \
349 "Unsupported ISA type, c0.config0: %d.";
350
351 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
352 {
353
354 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
355
356 /*
357 * 0 = All TLBWR instructions go to FTLB
358 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
359 * FTLB and 1 goes to the VTLB.
360 * 2 = 7:1: As above with 7:1 ratio.
361 * 3 = 3:1: As above with 3:1 ratio.
362 *
363 * Use the linear midpoint as the probability threshold.
364 */
365 if (probability >= 12)
366 return 1;
367 else if (probability >= 6)
368 return 2;
369 else
370 /*
371 * So FTLB is less than 4 times bigger than VTLB.
372 * A 3:1 ratio can still be useful though.
373 */
374 return 3;
375 }
376
377 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
378 {
379 unsigned int config;
380
381 /* It's implementation dependent how the FTLB can be enabled */
382 switch (c->cputype) {
383 case CPU_PROAPTIV:
384 case CPU_P5600:
385 /* proAptiv & related cores use Config6 to enable the FTLB */
386 config = read_c0_config6();
387 /* Clear the old probability value */
388 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
389 if (enable)
390 /* Enable FTLB */
391 write_c0_config6(config |
392 (calculate_ftlb_probability(c)
393 << MIPS_CONF6_FTLBP_SHIFT)
394 | MIPS_CONF6_FTLBEN);
395 else
396 /* Disable FTLB */
397 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
398 break;
399 case CPU_I6400:
400 /* I6400 & related cores use Config7 to configure FTLB */
401 config = read_c0_config7();
402 /* Clear the old probability value */
403 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
404 write_c0_config7(config | (calculate_ftlb_probability(c)
405 << MIPS_CONF7_FTLBP_SHIFT));
406 break;
407 default:
408 return 1;
409 }
410
411 return 0;
412 }
413
414 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
415 {
416 unsigned int config0;
417 int isa, mt;
418
419 config0 = read_c0_config();
420
421 /*
422 * Look for Standard TLB or Dual VTLB and FTLB
423 */
424 mt = config0 & MIPS_CONF_MT;
425 if (mt == MIPS_CONF_MT_TLB)
426 c->options |= MIPS_CPU_TLB;
427 else if (mt == MIPS_CONF_MT_FTLB)
428 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
429
430 isa = (config0 & MIPS_CONF_AT) >> 13;
431 switch (isa) {
432 case 0:
433 switch ((config0 & MIPS_CONF_AR) >> 10) {
434 case 0:
435 set_isa(c, MIPS_CPU_ISA_M32R1);
436 break;
437 case 1:
438 set_isa(c, MIPS_CPU_ISA_M32R2);
439 break;
440 case 2:
441 set_isa(c, MIPS_CPU_ISA_M32R6);
442 break;
443 default:
444 goto unknown;
445 }
446 break;
447 case 2:
448 switch ((config0 & MIPS_CONF_AR) >> 10) {
449 case 0:
450 set_isa(c, MIPS_CPU_ISA_M64R1);
451 break;
452 case 1:
453 set_isa(c, MIPS_CPU_ISA_M64R2);
454 break;
455 case 2:
456 set_isa(c, MIPS_CPU_ISA_M64R6);
457 break;
458 default:
459 goto unknown;
460 }
461 break;
462 default:
463 goto unknown;
464 }
465
466 return config0 & MIPS_CONF_M;
467
468 unknown:
469 panic(unknown_isa, config0);
470 }
471
472 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
473 {
474 unsigned int config1;
475
476 config1 = read_c0_config1();
477
478 if (config1 & MIPS_CONF1_MD)
479 c->ases |= MIPS_ASE_MDMX;
480 if (config1 & MIPS_CONF1_WR)
481 c->options |= MIPS_CPU_WATCH;
482 if (config1 & MIPS_CONF1_CA)
483 c->ases |= MIPS_ASE_MIPS16;
484 if (config1 & MIPS_CONF1_EP)
485 c->options |= MIPS_CPU_EJTAG;
486 if (config1 & MIPS_CONF1_FP) {
487 c->options |= MIPS_CPU_FPU;
488 c->options |= MIPS_CPU_32FPR;
489 }
490 if (cpu_has_tlb) {
491 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
492 c->tlbsizevtlb = c->tlbsize;
493 c->tlbsizeftlbsets = 0;
494 }
495
496 return config1 & MIPS_CONF_M;
497 }
498
499 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
500 {
501 unsigned int config2;
502
503 config2 = read_c0_config2();
504
505 if (config2 & MIPS_CONF2_SL)
506 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
507
508 return config2 & MIPS_CONF_M;
509 }
510
511 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
512 {
513 unsigned int config3;
514
515 config3 = read_c0_config3();
516
517 if (config3 & MIPS_CONF3_SM) {
518 c->ases |= MIPS_ASE_SMARTMIPS;
519 c->options |= MIPS_CPU_RIXI;
520 }
521 if (config3 & MIPS_CONF3_RXI)
522 c->options |= MIPS_CPU_RIXI;
523 if (config3 & MIPS_CONF3_DSP)
524 c->ases |= MIPS_ASE_DSP;
525 if (config3 & MIPS_CONF3_DSP2P)
526 c->ases |= MIPS_ASE_DSP2P;
527 if (config3 & MIPS_CONF3_VINT)
528 c->options |= MIPS_CPU_VINT;
529 if (config3 & MIPS_CONF3_VEIC)
530 c->options |= MIPS_CPU_VEIC;
531 if (config3 & MIPS_CONF3_MT)
532 c->ases |= MIPS_ASE_MIPSMT;
533 if (config3 & MIPS_CONF3_ULRI)
534 c->options |= MIPS_CPU_ULRI;
535 if (config3 & MIPS_CONF3_ISA)
536 c->options |= MIPS_CPU_MICROMIPS;
537 if (config3 & MIPS_CONF3_VZ)
538 c->ases |= MIPS_ASE_VZ;
539 if (config3 & MIPS_CONF3_SC)
540 c->options |= MIPS_CPU_SEGMENTS;
541 if (config3 & MIPS_CONF3_MSA)
542 c->ases |= MIPS_ASE_MSA;
543 if (config3 & MIPS_CONF3_PW) {
544 c->htw_seq = 0;
545 c->options |= MIPS_CPU_HTW;
546 }
547 if (config3 & MIPS_CONF3_CDMM)
548 c->options |= MIPS_CPU_CDMM;
549 if (config3 & MIPS_CONF3_SP)
550 c->options |= MIPS_CPU_SP;
551
552 return config3 & MIPS_CONF_M;
553 }
554
555 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
556 {
557 unsigned int config4;
558 unsigned int newcf4;
559 unsigned int mmuextdef;
560 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
561
562 config4 = read_c0_config4();
563
564 if (cpu_has_tlb) {
565 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
566 c->options |= MIPS_CPU_TLBINV;
567
568 /*
569 * R6 has dropped the MMUExtDef field from config4.
570 * On R6 the fields always describe the FTLB, and only if it is
571 * present according to Config.MT.
572 */
573 if (!cpu_has_mips_r6)
574 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
575 else if (cpu_has_ftlb)
576 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
577 else
578 mmuextdef = 0;
579
580 switch (mmuextdef) {
581 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
582 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
583 c->tlbsizevtlb = c->tlbsize;
584 break;
585 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
586 c->tlbsizevtlb +=
587 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
588 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
589 c->tlbsize = c->tlbsizevtlb;
590 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
591 /* fall through */
592 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
593 if (mips_ftlb_disabled)
594 break;
595 newcf4 = (config4 & ~ftlb_page) |
596 (page_size_ftlb(mmuextdef) <<
597 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
598 write_c0_config4(newcf4);
599 back_to_back_c0_hazard();
600 config4 = read_c0_config4();
601 if (config4 != newcf4) {
602 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
603 PAGE_SIZE, config4);
604 /* Switch FTLB off */
605 set_ftlb_enable(c, 0);
606 break;
607 }
608 c->tlbsizeftlbsets = 1 <<
609 ((config4 & MIPS_CONF4_FTLBSETS) >>
610 MIPS_CONF4_FTLBSETS_SHIFT);
611 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
612 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
613 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
614 mips_has_ftlb_configured = 1;
615 break;
616 }
617 }
618
619 c->kscratch_mask = (config4 >> 16) & 0xff;
620
621 return config4 & MIPS_CONF_M;
622 }
623
624 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
625 {
626 unsigned int config5;
627
628 config5 = read_c0_config5();
629 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
630 write_c0_config5(config5);
631
632 if (config5 & MIPS_CONF5_EVA)
633 c->options |= MIPS_CPU_EVA;
634 if (config5 & MIPS_CONF5_MRP)
635 c->options |= MIPS_CPU_MAAR;
636 if (config5 & MIPS_CONF5_LLB)
637 c->options |= MIPS_CPU_RW_LLB;
638 #ifdef CONFIG_XPA
639 if (config5 & MIPS_CONF5_MVH)
640 c->options |= MIPS_CPU_XPA;
641 #endif
642
643 return config5 & MIPS_CONF_M;
644 }
645
646 static void decode_configs(struct cpuinfo_mips *c)
647 {
648 int ok;
649
650 /* MIPS32 or MIPS64 compliant CPU. */
651 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
653
654 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
655
656 /* Enable FTLB if present and not disabled */
657 set_ftlb_enable(c, !mips_ftlb_disabled);
658
659 ok = decode_config0(c); /* Read Config registers. */
660 BUG_ON(!ok); /* Arch spec violation! */
661 if (ok)
662 ok = decode_config1(c);
663 if (ok)
664 ok = decode_config2(c);
665 if (ok)
666 ok = decode_config3(c);
667 if (ok)
668 ok = decode_config4(c);
669 if (ok)
670 ok = decode_config5(c);
671
672 mips_probe_watch_registers(c);
673
674 if (cpu_has_rixi) {
675 /* Enable the RIXI exceptions */
676 set_c0_pagegrain(PG_IEC);
677 back_to_back_c0_hazard();
678 /* Verify the IEC bit is set */
679 if (read_c0_pagegrain() & PG_IEC)
680 c->options |= MIPS_CPU_RIXIEX;
681 }
682
683 #ifndef CONFIG_MIPS_CPS
684 if (cpu_has_mips_r2_r6) {
685 c->core = get_ebase_cpunum();
686 if (cpu_has_mipsmt)
687 c->core >>= fls(core_nvpes()) - 1;
688 }
689 #endif
690 }
691
692 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
693 | MIPS_CPU_COUNTER)
694
695 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
696 {
697 switch (c->processor_id & PRID_IMP_MASK) {
698 case PRID_IMP_R2000:
699 c->cputype = CPU_R2000;
700 __cpu_name[cpu] = "R2000";
701 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
702 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
703 MIPS_CPU_NOFPUEX;
704 if (__cpu_has_fpu())
705 c->options |= MIPS_CPU_FPU;
706 c->tlbsize = 64;
707 break;
708 case PRID_IMP_R3000:
709 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
710 if (cpu_has_confreg()) {
711 c->cputype = CPU_R3081E;
712 __cpu_name[cpu] = "R3081";
713 } else {
714 c->cputype = CPU_R3000A;
715 __cpu_name[cpu] = "R3000A";
716 }
717 } else {
718 c->cputype = CPU_R3000;
719 __cpu_name[cpu] = "R3000";
720 }
721 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
722 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
723 MIPS_CPU_NOFPUEX;
724 if (__cpu_has_fpu())
725 c->options |= MIPS_CPU_FPU;
726 c->tlbsize = 64;
727 break;
728 case PRID_IMP_R4000:
729 if (read_c0_config() & CONF_SC) {
730 if ((c->processor_id & PRID_REV_MASK) >=
731 PRID_REV_R4400) {
732 c->cputype = CPU_R4400PC;
733 __cpu_name[cpu] = "R4400PC";
734 } else {
735 c->cputype = CPU_R4000PC;
736 __cpu_name[cpu] = "R4000PC";
737 }
738 } else {
739 int cca = read_c0_config() & CONF_CM_CMASK;
740 int mc;
741
742 /*
743 * SC and MC versions can't be reliably told apart,
744 * but only the latter support coherent caching
745 * modes so assume the firmware has set the KSEG0
746 * coherency attribute reasonably (if uncached, we
747 * assume SC).
748 */
749 switch (cca) {
750 case CONF_CM_CACHABLE_CE:
751 case CONF_CM_CACHABLE_COW:
752 case CONF_CM_CACHABLE_CUW:
753 mc = 1;
754 break;
755 default:
756 mc = 0;
757 break;
758 }
759 if ((c->processor_id & PRID_REV_MASK) >=
760 PRID_REV_R4400) {
761 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
762 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
763 } else {
764 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
765 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
766 }
767 }
768
769 set_isa(c, MIPS_CPU_ISA_III);
770 c->fpu_msk31 |= FPU_CSR_CONDX;
771 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
772 MIPS_CPU_WATCH | MIPS_CPU_VCE |
773 MIPS_CPU_LLSC;
774 c->tlbsize = 48;
775 break;
776 case PRID_IMP_VR41XX:
777 set_isa(c, MIPS_CPU_ISA_III);
778 c->fpu_msk31 |= FPU_CSR_CONDX;
779 c->options = R4K_OPTS;
780 c->tlbsize = 32;
781 switch (c->processor_id & 0xf0) {
782 case PRID_REV_VR4111:
783 c->cputype = CPU_VR4111;
784 __cpu_name[cpu] = "NEC VR4111";
785 break;
786 case PRID_REV_VR4121:
787 c->cputype = CPU_VR4121;
788 __cpu_name[cpu] = "NEC VR4121";
789 break;
790 case PRID_REV_VR4122:
791 if ((c->processor_id & 0xf) < 0x3) {
792 c->cputype = CPU_VR4122;
793 __cpu_name[cpu] = "NEC VR4122";
794 } else {
795 c->cputype = CPU_VR4181A;
796 __cpu_name[cpu] = "NEC VR4181A";
797 }
798 break;
799 case PRID_REV_VR4130:
800 if ((c->processor_id & 0xf) < 0x4) {
801 c->cputype = CPU_VR4131;
802 __cpu_name[cpu] = "NEC VR4131";
803 } else {
804 c->cputype = CPU_VR4133;
805 c->options |= MIPS_CPU_LLSC;
806 __cpu_name[cpu] = "NEC VR4133";
807 }
808 break;
809 default:
810 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
811 c->cputype = CPU_VR41XX;
812 __cpu_name[cpu] = "NEC Vr41xx";
813 break;
814 }
815 break;
816 case PRID_IMP_R4300:
817 c->cputype = CPU_R4300;
818 __cpu_name[cpu] = "R4300";
819 set_isa(c, MIPS_CPU_ISA_III);
820 c->fpu_msk31 |= FPU_CSR_CONDX;
821 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
822 MIPS_CPU_LLSC;
823 c->tlbsize = 32;
824 break;
825 case PRID_IMP_R4600:
826 c->cputype = CPU_R4600;
827 __cpu_name[cpu] = "R4600";
828 set_isa(c, MIPS_CPU_ISA_III);
829 c->fpu_msk31 |= FPU_CSR_CONDX;
830 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
831 MIPS_CPU_LLSC;
832 c->tlbsize = 48;
833 break;
834 #if 0
835 case PRID_IMP_R4650:
836 /*
837 * This processor doesn't have an MMU, so it's not
838 * "real easy" to run Linux on it. It is left purely
839 * for documentation. Commented out because it shares
840 * it's c0_prid id number with the TX3900.
841 */
842 c->cputype = CPU_R4650;
843 __cpu_name[cpu] = "R4650";
844 set_isa(c, MIPS_CPU_ISA_III);
845 c->fpu_msk31 |= FPU_CSR_CONDX;
846 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
847 c->tlbsize = 48;
848 break;
849 #endif
850 case PRID_IMP_TX39:
851 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
852 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
853
854 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
855 c->cputype = CPU_TX3927;
856 __cpu_name[cpu] = "TX3927";
857 c->tlbsize = 64;
858 } else {
859 switch (c->processor_id & PRID_REV_MASK) {
860 case PRID_REV_TX3912:
861 c->cputype = CPU_TX3912;
862 __cpu_name[cpu] = "TX3912";
863 c->tlbsize = 32;
864 break;
865 case PRID_REV_TX3922:
866 c->cputype = CPU_TX3922;
867 __cpu_name[cpu] = "TX3922";
868 c->tlbsize = 64;
869 break;
870 }
871 }
872 break;
873 case PRID_IMP_R4700:
874 c->cputype = CPU_R4700;
875 __cpu_name[cpu] = "R4700";
876 set_isa(c, MIPS_CPU_ISA_III);
877 c->fpu_msk31 |= FPU_CSR_CONDX;
878 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
879 MIPS_CPU_LLSC;
880 c->tlbsize = 48;
881 break;
882 case PRID_IMP_TX49:
883 c->cputype = CPU_TX49XX;
884 __cpu_name[cpu] = "R49XX";
885 set_isa(c, MIPS_CPU_ISA_III);
886 c->fpu_msk31 |= FPU_CSR_CONDX;
887 c->options = R4K_OPTS | MIPS_CPU_LLSC;
888 if (!(c->processor_id & 0x08))
889 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
890 c->tlbsize = 48;
891 break;
892 case PRID_IMP_R5000:
893 c->cputype = CPU_R5000;
894 __cpu_name[cpu] = "R5000";
895 set_isa(c, MIPS_CPU_ISA_IV);
896 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
897 MIPS_CPU_LLSC;
898 c->tlbsize = 48;
899 break;
900 case PRID_IMP_R5432:
901 c->cputype = CPU_R5432;
902 __cpu_name[cpu] = "R5432";
903 set_isa(c, MIPS_CPU_ISA_IV);
904 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
905 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
906 c->tlbsize = 48;
907 break;
908 case PRID_IMP_R5500:
909 c->cputype = CPU_R5500;
910 __cpu_name[cpu] = "R5500";
911 set_isa(c, MIPS_CPU_ISA_IV);
912 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
913 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
914 c->tlbsize = 48;
915 break;
916 case PRID_IMP_NEVADA:
917 c->cputype = CPU_NEVADA;
918 __cpu_name[cpu] = "Nevada";
919 set_isa(c, MIPS_CPU_ISA_IV);
920 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
921 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
922 c->tlbsize = 48;
923 break;
924 case PRID_IMP_R6000:
925 c->cputype = CPU_R6000;
926 __cpu_name[cpu] = "R6000";
927 set_isa(c, MIPS_CPU_ISA_II);
928 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
929 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
930 MIPS_CPU_LLSC;
931 c->tlbsize = 32;
932 break;
933 case PRID_IMP_R6000A:
934 c->cputype = CPU_R6000A;
935 __cpu_name[cpu] = "R6000A";
936 set_isa(c, MIPS_CPU_ISA_II);
937 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
938 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
939 MIPS_CPU_LLSC;
940 c->tlbsize = 32;
941 break;
942 case PRID_IMP_RM7000:
943 c->cputype = CPU_RM7000;
944 __cpu_name[cpu] = "RM7000";
945 set_isa(c, MIPS_CPU_ISA_IV);
946 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
947 MIPS_CPU_LLSC;
948 /*
949 * Undocumented RM7000: Bit 29 in the info register of
950 * the RM7000 v2.0 indicates if the TLB has 48 or 64
951 * entries.
952 *
953 * 29 1 => 64 entry JTLB
954 * 0 => 48 entry JTLB
955 */
956 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
957 break;
958 case PRID_IMP_R8000:
959 c->cputype = CPU_R8000;
960 __cpu_name[cpu] = "RM8000";
961 set_isa(c, MIPS_CPU_ISA_IV);
962 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
963 MIPS_CPU_FPU | MIPS_CPU_32FPR |
964 MIPS_CPU_LLSC;
965 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
966 break;
967 case PRID_IMP_R10000:
968 c->cputype = CPU_R10000;
969 __cpu_name[cpu] = "R10000";
970 set_isa(c, MIPS_CPU_ISA_IV);
971 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
972 MIPS_CPU_FPU | MIPS_CPU_32FPR |
973 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
974 MIPS_CPU_LLSC;
975 c->tlbsize = 64;
976 break;
977 case PRID_IMP_R12000:
978 c->cputype = CPU_R12000;
979 __cpu_name[cpu] = "R12000";
980 set_isa(c, MIPS_CPU_ISA_IV);
981 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
982 MIPS_CPU_FPU | MIPS_CPU_32FPR |
983 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
984 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
985 c->tlbsize = 64;
986 break;
987 case PRID_IMP_R14000:
988 if (((c->processor_id >> 4) & 0x0f) > 2) {
989 c->cputype = CPU_R16000;
990 __cpu_name[cpu] = "R16000";
991 } else {
992 c->cputype = CPU_R14000;
993 __cpu_name[cpu] = "R14000";
994 }
995 set_isa(c, MIPS_CPU_ISA_IV);
996 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
997 MIPS_CPU_FPU | MIPS_CPU_32FPR |
998 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
999 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1000 c->tlbsize = 64;
1001 break;
1002 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1003 switch (c->processor_id & PRID_REV_MASK) {
1004 case PRID_REV_LOONGSON2E:
1005 c->cputype = CPU_LOONGSON2;
1006 __cpu_name[cpu] = "ICT Loongson-2";
1007 set_elf_platform(cpu, "loongson2e");
1008 set_isa(c, MIPS_CPU_ISA_III);
1009 c->fpu_msk31 |= FPU_CSR_CONDX;
1010 break;
1011 case PRID_REV_LOONGSON2F:
1012 c->cputype = CPU_LOONGSON2;
1013 __cpu_name[cpu] = "ICT Loongson-2";
1014 set_elf_platform(cpu, "loongson2f");
1015 set_isa(c, MIPS_CPU_ISA_III);
1016 c->fpu_msk31 |= FPU_CSR_CONDX;
1017 break;
1018 case PRID_REV_LOONGSON3A:
1019 c->cputype = CPU_LOONGSON3;
1020 __cpu_name[cpu] = "ICT Loongson-3";
1021 set_elf_platform(cpu, "loongson3a");
1022 set_isa(c, MIPS_CPU_ISA_M64R1);
1023 break;
1024 case PRID_REV_LOONGSON3B_R1:
1025 case PRID_REV_LOONGSON3B_R2:
1026 c->cputype = CPU_LOONGSON3;
1027 __cpu_name[cpu] = "ICT Loongson-3";
1028 set_elf_platform(cpu, "loongson3b");
1029 set_isa(c, MIPS_CPU_ISA_M64R1);
1030 break;
1031 }
1032
1033 c->options = R4K_OPTS |
1034 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1035 MIPS_CPU_32FPR;
1036 c->tlbsize = 64;
1037 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1038 break;
1039 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1040 decode_configs(c);
1041
1042 c->cputype = CPU_LOONGSON1;
1043
1044 switch (c->processor_id & PRID_REV_MASK) {
1045 case PRID_REV_LOONGSON1B:
1046 __cpu_name[cpu] = "Loongson 1B";
1047 break;
1048 }
1049
1050 break;
1051 }
1052 }
1053
1054 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1055 {
1056 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1057 switch (c->processor_id & PRID_IMP_MASK) {
1058 case PRID_IMP_QEMU_GENERIC:
1059 c->writecombine = _CACHE_UNCACHED;
1060 c->cputype = CPU_QEMU_GENERIC;
1061 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1062 break;
1063 case PRID_IMP_4KC:
1064 c->cputype = CPU_4KC;
1065 c->writecombine = _CACHE_UNCACHED;
1066 __cpu_name[cpu] = "MIPS 4Kc";
1067 break;
1068 case PRID_IMP_4KEC:
1069 case PRID_IMP_4KECR2:
1070 c->cputype = CPU_4KEC;
1071 c->writecombine = _CACHE_UNCACHED;
1072 __cpu_name[cpu] = "MIPS 4KEc";
1073 break;
1074 case PRID_IMP_4KSC:
1075 case PRID_IMP_4KSD:
1076 c->cputype = CPU_4KSC;
1077 c->writecombine = _CACHE_UNCACHED;
1078 __cpu_name[cpu] = "MIPS 4KSc";
1079 break;
1080 case PRID_IMP_5KC:
1081 c->cputype = CPU_5KC;
1082 c->writecombine = _CACHE_UNCACHED;
1083 __cpu_name[cpu] = "MIPS 5Kc";
1084 break;
1085 case PRID_IMP_5KE:
1086 c->cputype = CPU_5KE;
1087 c->writecombine = _CACHE_UNCACHED;
1088 __cpu_name[cpu] = "MIPS 5KE";
1089 break;
1090 case PRID_IMP_20KC:
1091 c->cputype = CPU_20KC;
1092 c->writecombine = _CACHE_UNCACHED;
1093 __cpu_name[cpu] = "MIPS 20Kc";
1094 break;
1095 case PRID_IMP_24K:
1096 c->cputype = CPU_24K;
1097 c->writecombine = _CACHE_UNCACHED;
1098 __cpu_name[cpu] = "MIPS 24Kc";
1099 break;
1100 case PRID_IMP_24KE:
1101 c->cputype = CPU_24K;
1102 c->writecombine = _CACHE_UNCACHED;
1103 __cpu_name[cpu] = "MIPS 24KEc";
1104 break;
1105 case PRID_IMP_25KF:
1106 c->cputype = CPU_25KF;
1107 c->writecombine = _CACHE_UNCACHED;
1108 __cpu_name[cpu] = "MIPS 25Kc";
1109 break;
1110 case PRID_IMP_34K:
1111 c->cputype = CPU_34K;
1112 c->writecombine = _CACHE_UNCACHED;
1113 __cpu_name[cpu] = "MIPS 34Kc";
1114 break;
1115 case PRID_IMP_74K:
1116 c->cputype = CPU_74K;
1117 c->writecombine = _CACHE_UNCACHED;
1118 __cpu_name[cpu] = "MIPS 74Kc";
1119 break;
1120 case PRID_IMP_M14KC:
1121 c->cputype = CPU_M14KC;
1122 c->writecombine = _CACHE_UNCACHED;
1123 __cpu_name[cpu] = "MIPS M14Kc";
1124 break;
1125 case PRID_IMP_M14KEC:
1126 c->cputype = CPU_M14KEC;
1127 c->writecombine = _CACHE_UNCACHED;
1128 __cpu_name[cpu] = "MIPS M14KEc";
1129 break;
1130 case PRID_IMP_1004K:
1131 c->cputype = CPU_1004K;
1132 c->writecombine = _CACHE_UNCACHED;
1133 __cpu_name[cpu] = "MIPS 1004Kc";
1134 break;
1135 case PRID_IMP_1074K:
1136 c->cputype = CPU_1074K;
1137 c->writecombine = _CACHE_UNCACHED;
1138 __cpu_name[cpu] = "MIPS 1074Kc";
1139 break;
1140 case PRID_IMP_INTERAPTIV_UP:
1141 c->cputype = CPU_INTERAPTIV;
1142 __cpu_name[cpu] = "MIPS interAptiv";
1143 break;
1144 case PRID_IMP_INTERAPTIV_MP:
1145 c->cputype = CPU_INTERAPTIV;
1146 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1147 break;
1148 case PRID_IMP_PROAPTIV_UP:
1149 c->cputype = CPU_PROAPTIV;
1150 __cpu_name[cpu] = "MIPS proAptiv";
1151 break;
1152 case PRID_IMP_PROAPTIV_MP:
1153 c->cputype = CPU_PROAPTIV;
1154 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1155 break;
1156 case PRID_IMP_P5600:
1157 c->cputype = CPU_P5600;
1158 __cpu_name[cpu] = "MIPS P5600";
1159 break;
1160 case PRID_IMP_I6400:
1161 c->cputype = CPU_I6400;
1162 __cpu_name[cpu] = "MIPS I6400";
1163 break;
1164 case PRID_IMP_M5150:
1165 c->cputype = CPU_M5150;
1166 __cpu_name[cpu] = "MIPS M5150";
1167 break;
1168 }
1169
1170 decode_configs(c);
1171
1172 spram_config();
1173 }
1174
1175 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1176 {
1177 decode_configs(c);
1178 switch (c->processor_id & PRID_IMP_MASK) {
1179 case PRID_IMP_AU1_REV1:
1180 case PRID_IMP_AU1_REV2:
1181 c->cputype = CPU_ALCHEMY;
1182 switch ((c->processor_id >> 24) & 0xff) {
1183 case 0:
1184 __cpu_name[cpu] = "Au1000";
1185 break;
1186 case 1:
1187 __cpu_name[cpu] = "Au1500";
1188 break;
1189 case 2:
1190 __cpu_name[cpu] = "Au1100";
1191 break;
1192 case 3:
1193 __cpu_name[cpu] = "Au1550";
1194 break;
1195 case 4:
1196 __cpu_name[cpu] = "Au1200";
1197 if ((c->processor_id & PRID_REV_MASK) == 2)
1198 __cpu_name[cpu] = "Au1250";
1199 break;
1200 case 5:
1201 __cpu_name[cpu] = "Au1210";
1202 break;
1203 default:
1204 __cpu_name[cpu] = "Au1xxx";
1205 break;
1206 }
1207 break;
1208 }
1209 }
1210
1211 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1212 {
1213 decode_configs(c);
1214
1215 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1216 switch (c->processor_id & PRID_IMP_MASK) {
1217 case PRID_IMP_SB1:
1218 c->cputype = CPU_SB1;
1219 __cpu_name[cpu] = "SiByte SB1";
1220 /* FPU in pass1 is known to have issues. */
1221 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1222 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1223 break;
1224 case PRID_IMP_SB1A:
1225 c->cputype = CPU_SB1A;
1226 __cpu_name[cpu] = "SiByte SB1A";
1227 break;
1228 }
1229 }
1230
1231 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1232 {
1233 decode_configs(c);
1234 switch (c->processor_id & PRID_IMP_MASK) {
1235 case PRID_IMP_SR71000:
1236 c->cputype = CPU_SR71000;
1237 __cpu_name[cpu] = "Sandcraft SR71000";
1238 c->scache.ways = 8;
1239 c->tlbsize = 64;
1240 break;
1241 }
1242 }
1243
1244 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1245 {
1246 decode_configs(c);
1247 switch (c->processor_id & PRID_IMP_MASK) {
1248 case PRID_IMP_PR4450:
1249 c->cputype = CPU_PR4450;
1250 __cpu_name[cpu] = "Philips PR4450";
1251 set_isa(c, MIPS_CPU_ISA_M32R1);
1252 break;
1253 }
1254 }
1255
1256 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1257 {
1258 decode_configs(c);
1259 switch (c->processor_id & PRID_IMP_MASK) {
1260 case PRID_IMP_BMIPS32_REV4:
1261 case PRID_IMP_BMIPS32_REV8:
1262 c->cputype = CPU_BMIPS32;
1263 __cpu_name[cpu] = "Broadcom BMIPS32";
1264 set_elf_platform(cpu, "bmips32");
1265 break;
1266 case PRID_IMP_BMIPS3300:
1267 case PRID_IMP_BMIPS3300_ALT:
1268 case PRID_IMP_BMIPS3300_BUG:
1269 c->cputype = CPU_BMIPS3300;
1270 __cpu_name[cpu] = "Broadcom BMIPS3300";
1271 set_elf_platform(cpu, "bmips3300");
1272 break;
1273 case PRID_IMP_BMIPS43XX: {
1274 int rev = c->processor_id & PRID_REV_MASK;
1275
1276 if (rev >= PRID_REV_BMIPS4380_LO &&
1277 rev <= PRID_REV_BMIPS4380_HI) {
1278 c->cputype = CPU_BMIPS4380;
1279 __cpu_name[cpu] = "Broadcom BMIPS4380";
1280 set_elf_platform(cpu, "bmips4380");
1281 } else {
1282 c->cputype = CPU_BMIPS4350;
1283 __cpu_name[cpu] = "Broadcom BMIPS4350";
1284 set_elf_platform(cpu, "bmips4350");
1285 }
1286 break;
1287 }
1288 case PRID_IMP_BMIPS5000:
1289 case PRID_IMP_BMIPS5200:
1290 c->cputype = CPU_BMIPS5000;
1291 __cpu_name[cpu] = "Broadcom BMIPS5000";
1292 set_elf_platform(cpu, "bmips5000");
1293 c->options |= MIPS_CPU_ULRI;
1294 break;
1295 }
1296 }
1297
1298 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1299 {
1300 decode_configs(c);
1301 switch (c->processor_id & PRID_IMP_MASK) {
1302 case PRID_IMP_CAVIUM_CN38XX:
1303 case PRID_IMP_CAVIUM_CN31XX:
1304 case PRID_IMP_CAVIUM_CN30XX:
1305 c->cputype = CPU_CAVIUM_OCTEON;
1306 __cpu_name[cpu] = "Cavium Octeon";
1307 goto platform;
1308 case PRID_IMP_CAVIUM_CN58XX:
1309 case PRID_IMP_CAVIUM_CN56XX:
1310 case PRID_IMP_CAVIUM_CN50XX:
1311 case PRID_IMP_CAVIUM_CN52XX:
1312 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1313 __cpu_name[cpu] = "Cavium Octeon+";
1314 platform:
1315 set_elf_platform(cpu, "octeon");
1316 break;
1317 case PRID_IMP_CAVIUM_CN61XX:
1318 case PRID_IMP_CAVIUM_CN63XX:
1319 case PRID_IMP_CAVIUM_CN66XX:
1320 case PRID_IMP_CAVIUM_CN68XX:
1321 case PRID_IMP_CAVIUM_CNF71XX:
1322 c->cputype = CPU_CAVIUM_OCTEON2;
1323 __cpu_name[cpu] = "Cavium Octeon II";
1324 set_elf_platform(cpu, "octeon2");
1325 break;
1326 case PRID_IMP_CAVIUM_CN70XX:
1327 case PRID_IMP_CAVIUM_CN78XX:
1328 c->cputype = CPU_CAVIUM_OCTEON3;
1329 __cpu_name[cpu] = "Cavium Octeon III";
1330 set_elf_platform(cpu, "octeon3");
1331 break;
1332 default:
1333 printk(KERN_INFO "Unknown Octeon chip!\n");
1334 c->cputype = CPU_UNKNOWN;
1335 break;
1336 }
1337 }
1338
1339 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1340 {
1341 decode_configs(c);
1342 /* JZRISC does not implement the CP0 counter. */
1343 c->options &= ~MIPS_CPU_COUNTER;
1344 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1345 switch (c->processor_id & PRID_IMP_MASK) {
1346 case PRID_IMP_JZRISC:
1347 c->cputype = CPU_JZRISC;
1348 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1349 __cpu_name[cpu] = "Ingenic JZRISC";
1350 break;
1351 default:
1352 panic("Unknown Ingenic Processor ID!");
1353 break;
1354 }
1355 }
1356
1357 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1358 {
1359 decode_configs(c);
1360
1361 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1362 c->cputype = CPU_ALCHEMY;
1363 __cpu_name[cpu] = "Au1300";
1364 /* following stuff is not for Alchemy */
1365 return;
1366 }
1367
1368 c->options = (MIPS_CPU_TLB |
1369 MIPS_CPU_4KEX |
1370 MIPS_CPU_COUNTER |
1371 MIPS_CPU_DIVEC |
1372 MIPS_CPU_WATCH |
1373 MIPS_CPU_EJTAG |
1374 MIPS_CPU_LLSC);
1375
1376 switch (c->processor_id & PRID_IMP_MASK) {
1377 case PRID_IMP_NETLOGIC_XLP2XX:
1378 case PRID_IMP_NETLOGIC_XLP9XX:
1379 case PRID_IMP_NETLOGIC_XLP5XX:
1380 c->cputype = CPU_XLP;
1381 __cpu_name[cpu] = "Broadcom XLPII";
1382 break;
1383
1384 case PRID_IMP_NETLOGIC_XLP8XX:
1385 case PRID_IMP_NETLOGIC_XLP3XX:
1386 c->cputype = CPU_XLP;
1387 __cpu_name[cpu] = "Netlogic XLP";
1388 break;
1389
1390 case PRID_IMP_NETLOGIC_XLR732:
1391 case PRID_IMP_NETLOGIC_XLR716:
1392 case PRID_IMP_NETLOGIC_XLR532:
1393 case PRID_IMP_NETLOGIC_XLR308:
1394 case PRID_IMP_NETLOGIC_XLR532C:
1395 case PRID_IMP_NETLOGIC_XLR516C:
1396 case PRID_IMP_NETLOGIC_XLR508C:
1397 case PRID_IMP_NETLOGIC_XLR308C:
1398 c->cputype = CPU_XLR;
1399 __cpu_name[cpu] = "Netlogic XLR";
1400 break;
1401
1402 case PRID_IMP_NETLOGIC_XLS608:
1403 case PRID_IMP_NETLOGIC_XLS408:
1404 case PRID_IMP_NETLOGIC_XLS404:
1405 case PRID_IMP_NETLOGIC_XLS208:
1406 case PRID_IMP_NETLOGIC_XLS204:
1407 case PRID_IMP_NETLOGIC_XLS108:
1408 case PRID_IMP_NETLOGIC_XLS104:
1409 case PRID_IMP_NETLOGIC_XLS616B:
1410 case PRID_IMP_NETLOGIC_XLS608B:
1411 case PRID_IMP_NETLOGIC_XLS416B:
1412 case PRID_IMP_NETLOGIC_XLS412B:
1413 case PRID_IMP_NETLOGIC_XLS408B:
1414 case PRID_IMP_NETLOGIC_XLS404B:
1415 c->cputype = CPU_XLR;
1416 __cpu_name[cpu] = "Netlogic XLS";
1417 break;
1418
1419 default:
1420 pr_info("Unknown Netlogic chip id [%02x]!\n",
1421 c->processor_id);
1422 c->cputype = CPU_XLR;
1423 break;
1424 }
1425
1426 if (c->cputype == CPU_XLP) {
1427 set_isa(c, MIPS_CPU_ISA_M64R2);
1428 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1429 /* This will be updated again after all threads are woken up */
1430 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1431 } else {
1432 set_isa(c, MIPS_CPU_ISA_M64R1);
1433 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1434 }
1435 c->kscratch_mask = 0xf;
1436 }
1437
1438 #ifdef CONFIG_64BIT
1439 /* For use by uaccess.h */
1440 u64 __ua_limit;
1441 EXPORT_SYMBOL(__ua_limit);
1442 #endif
1443
1444 const char *__cpu_name[NR_CPUS];
1445 const char *__elf_platform;
1446
1447 void cpu_probe(void)
1448 {
1449 struct cpuinfo_mips *c = &current_cpu_data;
1450 unsigned int cpu = smp_processor_id();
1451
1452 c->processor_id = PRID_IMP_UNKNOWN;
1453 c->fpu_id = FPIR_IMP_NONE;
1454 c->cputype = CPU_UNKNOWN;
1455 c->writecombine = _CACHE_UNCACHED;
1456
1457 c->fpu_csr31 = FPU_CSR_RN;
1458 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1459
1460 c->processor_id = read_c0_prid();
1461 switch (c->processor_id & PRID_COMP_MASK) {
1462 case PRID_COMP_LEGACY:
1463 cpu_probe_legacy(c, cpu);
1464 break;
1465 case PRID_COMP_MIPS:
1466 cpu_probe_mips(c, cpu);
1467 break;
1468 case PRID_COMP_ALCHEMY:
1469 cpu_probe_alchemy(c, cpu);
1470 break;
1471 case PRID_COMP_SIBYTE:
1472 cpu_probe_sibyte(c, cpu);
1473 break;
1474 case PRID_COMP_BROADCOM:
1475 cpu_probe_broadcom(c, cpu);
1476 break;
1477 case PRID_COMP_SANDCRAFT:
1478 cpu_probe_sandcraft(c, cpu);
1479 break;
1480 case PRID_COMP_NXP:
1481 cpu_probe_nxp(c, cpu);
1482 break;
1483 case PRID_COMP_CAVIUM:
1484 cpu_probe_cavium(c, cpu);
1485 break;
1486 case PRID_COMP_INGENIC_D0:
1487 case PRID_COMP_INGENIC_D1:
1488 case PRID_COMP_INGENIC_E1:
1489 cpu_probe_ingenic(c, cpu);
1490 break;
1491 case PRID_COMP_NETLOGIC:
1492 cpu_probe_netlogic(c, cpu);
1493 break;
1494 }
1495
1496 BUG_ON(!__cpu_name[cpu]);
1497 BUG_ON(c->cputype == CPU_UNKNOWN);
1498
1499 /*
1500 * Platform code can force the cpu type to optimize code
1501 * generation. In that case be sure the cpu type is correctly
1502 * manually setup otherwise it could trigger some nasty bugs.
1503 */
1504 BUG_ON(current_cpu_type() != c->cputype);
1505
1506 if (mips_fpu_disabled)
1507 c->options &= ~MIPS_CPU_FPU;
1508
1509 if (mips_dsp_disabled)
1510 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1511
1512 if (mips_htw_disabled) {
1513 c->options &= ~MIPS_CPU_HTW;
1514 write_c0_pwctl(read_c0_pwctl() &
1515 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1516 }
1517
1518 if (c->options & MIPS_CPU_FPU)
1519 cpu_set_fpu_opts(c);
1520 else
1521 cpu_set_nofpu_opts(c);
1522
1523 if (cpu_has_bp_ghist)
1524 write_c0_r10k_diag(read_c0_r10k_diag() |
1525 R10K_DIAG_E_GHIST);
1526
1527 if (cpu_has_mips_r2_r6) {
1528 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1529 /* R2 has Performance Counter Interrupt indicator */
1530 c->options |= MIPS_CPU_PCI;
1531 }
1532 else
1533 c->srsets = 1;
1534
1535 if (cpu_has_mips_r6)
1536 elf_hwcap |= HWCAP_MIPS_R6;
1537
1538 if (cpu_has_msa) {
1539 c->msa_id = cpu_get_msa_id();
1540 WARN(c->msa_id & MSA_IR_WRPF,
1541 "Vector register partitioning unimplemented!");
1542 elf_hwcap |= HWCAP_MIPS_MSA;
1543 }
1544
1545 cpu_probe_vmbits(c);
1546
1547 #ifdef CONFIG_64BIT
1548 if (cpu == 0)
1549 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1550 #endif
1551 }
1552
1553 void cpu_report(void)
1554 {
1555 struct cpuinfo_mips *c = &current_cpu_data;
1556
1557 pr_info("CPU%d revision is: %08x (%s)\n",
1558 smp_processor_id(), c->processor_id, cpu_name_string());
1559 if (c->options & MIPS_CPU_FPU)
1560 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1561 if (cpu_has_msa)
1562 pr_info("MSA revision is: %08x\n", c->msa_id);
1563 }
Linux kernel - Deliverables
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