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rtlwifi: Change order in device startup
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-type.h>
24 #include <asm/fpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
27 #include <asm/msa.h>
28 #include <asm/watch.h>
29 #include <asm/elf.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/spram.h>
32 #include <asm/uaccess.h>
33
34 static int mips_fpu_disabled;
35
36 static int __init fpu_disable(char *s)
37 {
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42 }
43
44 __setup("nofpu", fpu_disable);
45
46 int mips_dsp_disabled;
47
48 static int __init dsp_disable(char *s)
49 {
50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
51 mips_dsp_disabled = 1;
52
53 return 1;
54 }
55
56 __setup("nodsp", dsp_disable);
57
58 static int mips_htw_disabled;
59
60 static int __init htw_disable(char *s)
61 {
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68 }
69
70 __setup("nohtw", htw_disable);
71
72 static inline void check_errata(void)
73 {
74 struct cpuinfo_mips *c = &current_cpu_data;
75
76 switch (current_cpu_type()) {
77 case CPU_34K:
78 /*
79 * Erratum "RPS May Cause Incorrect Instruction Execution"
80 * This code only handles VPE0, any SMP/RTOS code
81 * making use of VPE1 will be responsable for that VPE.
82 */
83 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
84 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
85 break;
86 default:
87 break;
88 }
89 }
90
91 void __init check_bugs32(void)
92 {
93 check_errata();
94 }
95
96 /*
97 * Probe whether cpu has config register by trying to play with
98 * alternate cache bit and see whether it matters.
99 * It's used by cpu_probe to distinguish between R3000A and R3081.
100 */
101 static inline int cpu_has_confreg(void)
102 {
103 #ifdef CONFIG_CPU_R3000
104 extern unsigned long r3k_cache_size(unsigned long);
105 unsigned long size1, size2;
106 unsigned long cfg = read_c0_conf();
107
108 size1 = r3k_cache_size(ST0_ISC);
109 write_c0_conf(cfg ^ R30XX_CONF_AC);
110 size2 = r3k_cache_size(ST0_ISC);
111 write_c0_conf(cfg);
112 return size1 != size2;
113 #else
114 return 0;
115 #endif
116 }
117
118 static inline void set_elf_platform(int cpu, const char *plat)
119 {
120 if (cpu == 0)
121 __elf_platform = plat;
122 }
123
124 /*
125 * Get the FPU Implementation/Revision.
126 */
127 static inline unsigned long cpu_get_fpu_id(void)
128 {
129 unsigned long tmp, fpu_id;
130
131 tmp = read_c0_status();
132 __enable_fpu(FPU_AS_IS);
133 fpu_id = read_32bit_cp1_register(CP1_REVISION);
134 write_c0_status(tmp);
135 return fpu_id;
136 }
137
138 /*
139 * Check the CPU has an FPU the official way.
140 */
141 static inline int __cpu_has_fpu(void)
142 {
143 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
144 }
145
146 static inline unsigned long cpu_get_msa_id(void)
147 {
148 unsigned long status, msa_id;
149
150 status = read_c0_status();
151 __enable_fpu(FPU_64BIT);
152 enable_msa();
153 msa_id = read_msa_ir();
154 disable_msa();
155 write_c0_status(status);
156 return msa_id;
157 }
158
159 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
160 {
161 #ifdef __NEED_VMBITS_PROBE
162 write_c0_entryhi(0x3fffffffffffe000ULL);
163 back_to_back_c0_hazard();
164 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
165 #endif
166 }
167
168 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
169 {
170 switch (isa) {
171 case MIPS_CPU_ISA_M64R2:
172 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
173 case MIPS_CPU_ISA_M64R1:
174 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
175 case MIPS_CPU_ISA_V:
176 c->isa_level |= MIPS_CPU_ISA_V;
177 case MIPS_CPU_ISA_IV:
178 c->isa_level |= MIPS_CPU_ISA_IV;
179 case MIPS_CPU_ISA_III:
180 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
181 break;
182
183 case MIPS_CPU_ISA_M32R2:
184 c->isa_level |= MIPS_CPU_ISA_M32R2;
185 case MIPS_CPU_ISA_M32R1:
186 c->isa_level |= MIPS_CPU_ISA_M32R1;
187 case MIPS_CPU_ISA_II:
188 c->isa_level |= MIPS_CPU_ISA_II;
189 break;
190 }
191 }
192
193 static char unknown_isa[] = KERN_ERR \
194 "Unsupported ISA type, c0.config0: %d.";
195
196 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
197 {
198 unsigned int config6;
199
200 /* It's implementation dependent how the FTLB can be enabled */
201 switch (c->cputype) {
202 case CPU_PROAPTIV:
203 case CPU_P5600:
204 /* proAptiv & related cores use Config6 to enable the FTLB */
205 config6 = read_c0_config6();
206 if (enable)
207 /* Enable FTLB */
208 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
209 else
210 /* Disable FTLB */
211 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
212 back_to_back_c0_hazard();
213 break;
214 }
215 }
216
217 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
218 {
219 unsigned int config0;
220 int isa;
221
222 config0 = read_c0_config();
223
224 /*
225 * Look for Standard TLB or Dual VTLB and FTLB
226 */
227 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
228 (((config0 & MIPS_CONF_MT) >> 7) == 4))
229 c->options |= MIPS_CPU_TLB;
230
231 isa = (config0 & MIPS_CONF_AT) >> 13;
232 switch (isa) {
233 case 0:
234 switch ((config0 & MIPS_CONF_AR) >> 10) {
235 case 0:
236 set_isa(c, MIPS_CPU_ISA_M32R1);
237 break;
238 case 1:
239 set_isa(c, MIPS_CPU_ISA_M32R2);
240 break;
241 default:
242 goto unknown;
243 }
244 break;
245 case 2:
246 switch ((config0 & MIPS_CONF_AR) >> 10) {
247 case 0:
248 set_isa(c, MIPS_CPU_ISA_M64R1);
249 break;
250 case 1:
251 set_isa(c, MIPS_CPU_ISA_M64R2);
252 break;
253 default:
254 goto unknown;
255 }
256 break;
257 default:
258 goto unknown;
259 }
260
261 return config0 & MIPS_CONF_M;
262
263 unknown:
264 panic(unknown_isa, config0);
265 }
266
267 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
268 {
269 unsigned int config1;
270
271 config1 = read_c0_config1();
272
273 if (config1 & MIPS_CONF1_MD)
274 c->ases |= MIPS_ASE_MDMX;
275 if (config1 & MIPS_CONF1_WR)
276 c->options |= MIPS_CPU_WATCH;
277 if (config1 & MIPS_CONF1_CA)
278 c->ases |= MIPS_ASE_MIPS16;
279 if (config1 & MIPS_CONF1_EP)
280 c->options |= MIPS_CPU_EJTAG;
281 if (config1 & MIPS_CONF1_FP) {
282 c->options |= MIPS_CPU_FPU;
283 c->options |= MIPS_CPU_32FPR;
284 }
285 if (cpu_has_tlb) {
286 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
287 c->tlbsizevtlb = c->tlbsize;
288 c->tlbsizeftlbsets = 0;
289 }
290
291 return config1 & MIPS_CONF_M;
292 }
293
294 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
295 {
296 unsigned int config2;
297
298 config2 = read_c0_config2();
299
300 if (config2 & MIPS_CONF2_SL)
301 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
302
303 return config2 & MIPS_CONF_M;
304 }
305
306 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
307 {
308 unsigned int config3;
309
310 config3 = read_c0_config3();
311
312 if (config3 & MIPS_CONF3_SM) {
313 c->ases |= MIPS_ASE_SMARTMIPS;
314 c->options |= MIPS_CPU_RIXI;
315 }
316 if (config3 & MIPS_CONF3_RXI)
317 c->options |= MIPS_CPU_RIXI;
318 if (config3 & MIPS_CONF3_DSP)
319 c->ases |= MIPS_ASE_DSP;
320 if (config3 & MIPS_CONF3_DSP2P)
321 c->ases |= MIPS_ASE_DSP2P;
322 if (config3 & MIPS_CONF3_VINT)
323 c->options |= MIPS_CPU_VINT;
324 if (config3 & MIPS_CONF3_VEIC)
325 c->options |= MIPS_CPU_VEIC;
326 if (config3 & MIPS_CONF3_MT)
327 c->ases |= MIPS_ASE_MIPSMT;
328 if (config3 & MIPS_CONF3_ULRI)
329 c->options |= MIPS_CPU_ULRI;
330 if (config3 & MIPS_CONF3_ISA)
331 c->options |= MIPS_CPU_MICROMIPS;
332 if (config3 & MIPS_CONF3_VZ)
333 c->ases |= MIPS_ASE_VZ;
334 if (config3 & MIPS_CONF3_SC)
335 c->options |= MIPS_CPU_SEGMENTS;
336 if (config3 & MIPS_CONF3_MSA)
337 c->ases |= MIPS_ASE_MSA;
338 /* Only tested on 32-bit cores */
339 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
340 c->options |= MIPS_CPU_HTW;
341
342 return config3 & MIPS_CONF_M;
343 }
344
345 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
346 {
347 unsigned int config4;
348 unsigned int newcf4;
349 unsigned int mmuextdef;
350 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
351
352 config4 = read_c0_config4();
353
354 if (cpu_has_tlb) {
355 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
356 c->options |= MIPS_CPU_TLBINV;
357 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
358 switch (mmuextdef) {
359 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
360 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
361 c->tlbsizevtlb = c->tlbsize;
362 break;
363 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
364 c->tlbsizevtlb +=
365 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
366 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
367 c->tlbsize = c->tlbsizevtlb;
368 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
369 /* fall through */
370 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
371 newcf4 = (config4 & ~ftlb_page) |
372 (page_size_ftlb(mmuextdef) <<
373 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
374 write_c0_config4(newcf4);
375 back_to_back_c0_hazard();
376 config4 = read_c0_config4();
377 if (config4 != newcf4) {
378 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
379 PAGE_SIZE, config4);
380 /* Switch FTLB off */
381 set_ftlb_enable(c, 0);
382 break;
383 }
384 c->tlbsizeftlbsets = 1 <<
385 ((config4 & MIPS_CONF4_FTLBSETS) >>
386 MIPS_CONF4_FTLBSETS_SHIFT);
387 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
388 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
389 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
390 break;
391 }
392 }
393
394 c->kscratch_mask = (config4 >> 16) & 0xff;
395
396 return config4 & MIPS_CONF_M;
397 }
398
399 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
400 {
401 unsigned int config5;
402
403 config5 = read_c0_config5();
404 config5 &= ~MIPS_CONF5_UFR;
405 write_c0_config5(config5);
406
407 if (config5 & MIPS_CONF5_EVA)
408 c->options |= MIPS_CPU_EVA;
409 if (config5 & MIPS_CONF5_MRP)
410 c->options |= MIPS_CPU_MAAR;
411
412 return config5 & MIPS_CONF_M;
413 }
414
415 static void decode_configs(struct cpuinfo_mips *c)
416 {
417 int ok;
418
419 /* MIPS32 or MIPS64 compliant CPU. */
420 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
421 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
422
423 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
424
425 /* Enable FTLB if present */
426 set_ftlb_enable(c, 1);
427
428 ok = decode_config0(c); /* Read Config registers. */
429 BUG_ON(!ok); /* Arch spec violation! */
430 if (ok)
431 ok = decode_config1(c);
432 if (ok)
433 ok = decode_config2(c);
434 if (ok)
435 ok = decode_config3(c);
436 if (ok)
437 ok = decode_config4(c);
438 if (ok)
439 ok = decode_config5(c);
440
441 mips_probe_watch_registers(c);
442
443 if (cpu_has_rixi) {
444 /* Enable the RIXI exceptions */
445 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
446 back_to_back_c0_hazard();
447 /* Verify the IEC bit is set */
448 if (read_c0_pagegrain() & PG_IEC)
449 c->options |= MIPS_CPU_RIXIEX;
450 }
451
452 #ifndef CONFIG_MIPS_CPS
453 if (cpu_has_mips_r2) {
454 c->core = get_ebase_cpunum();
455 if (cpu_has_mipsmt)
456 c->core >>= fls(core_nvpes()) - 1;
457 }
458 #endif
459 }
460
461 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
462 | MIPS_CPU_COUNTER)
463
464 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
465 {
466 switch (c->processor_id & PRID_IMP_MASK) {
467 case PRID_IMP_R2000:
468 c->cputype = CPU_R2000;
469 __cpu_name[cpu] = "R2000";
470 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
471 MIPS_CPU_NOFPUEX;
472 if (__cpu_has_fpu())
473 c->options |= MIPS_CPU_FPU;
474 c->tlbsize = 64;
475 break;
476 case PRID_IMP_R3000:
477 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
478 if (cpu_has_confreg()) {
479 c->cputype = CPU_R3081E;
480 __cpu_name[cpu] = "R3081";
481 } else {
482 c->cputype = CPU_R3000A;
483 __cpu_name[cpu] = "R3000A";
484 }
485 } else {
486 c->cputype = CPU_R3000;
487 __cpu_name[cpu] = "R3000";
488 }
489 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
490 MIPS_CPU_NOFPUEX;
491 if (__cpu_has_fpu())
492 c->options |= MIPS_CPU_FPU;
493 c->tlbsize = 64;
494 break;
495 case PRID_IMP_R4000:
496 if (read_c0_config() & CONF_SC) {
497 if ((c->processor_id & PRID_REV_MASK) >=
498 PRID_REV_R4400) {
499 c->cputype = CPU_R4400PC;
500 __cpu_name[cpu] = "R4400PC";
501 } else {
502 c->cputype = CPU_R4000PC;
503 __cpu_name[cpu] = "R4000PC";
504 }
505 } else {
506 int cca = read_c0_config() & CONF_CM_CMASK;
507 int mc;
508
509 /*
510 * SC and MC versions can't be reliably told apart,
511 * but only the latter support coherent caching
512 * modes so assume the firmware has set the KSEG0
513 * coherency attribute reasonably (if uncached, we
514 * assume SC).
515 */
516 switch (cca) {
517 case CONF_CM_CACHABLE_CE:
518 case CONF_CM_CACHABLE_COW:
519 case CONF_CM_CACHABLE_CUW:
520 mc = 1;
521 break;
522 default:
523 mc = 0;
524 break;
525 }
526 if ((c->processor_id & PRID_REV_MASK) >=
527 PRID_REV_R4400) {
528 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
529 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
530 } else {
531 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
532 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
533 }
534 }
535
536 set_isa(c, MIPS_CPU_ISA_III);
537 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
538 MIPS_CPU_WATCH | MIPS_CPU_VCE |
539 MIPS_CPU_LLSC;
540 c->tlbsize = 48;
541 break;
542 case PRID_IMP_VR41XX:
543 set_isa(c, MIPS_CPU_ISA_III);
544 c->options = R4K_OPTS;
545 c->tlbsize = 32;
546 switch (c->processor_id & 0xf0) {
547 case PRID_REV_VR4111:
548 c->cputype = CPU_VR4111;
549 __cpu_name[cpu] = "NEC VR4111";
550 break;
551 case PRID_REV_VR4121:
552 c->cputype = CPU_VR4121;
553 __cpu_name[cpu] = "NEC VR4121";
554 break;
555 case PRID_REV_VR4122:
556 if ((c->processor_id & 0xf) < 0x3) {
557 c->cputype = CPU_VR4122;
558 __cpu_name[cpu] = "NEC VR4122";
559 } else {
560 c->cputype = CPU_VR4181A;
561 __cpu_name[cpu] = "NEC VR4181A";
562 }
563 break;
564 case PRID_REV_VR4130:
565 if ((c->processor_id & 0xf) < 0x4) {
566 c->cputype = CPU_VR4131;
567 __cpu_name[cpu] = "NEC VR4131";
568 } else {
569 c->cputype = CPU_VR4133;
570 c->options |= MIPS_CPU_LLSC;
571 __cpu_name[cpu] = "NEC VR4133";
572 }
573 break;
574 default:
575 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
576 c->cputype = CPU_VR41XX;
577 __cpu_name[cpu] = "NEC Vr41xx";
578 break;
579 }
580 break;
581 case PRID_IMP_R4300:
582 c->cputype = CPU_R4300;
583 __cpu_name[cpu] = "R4300";
584 set_isa(c, MIPS_CPU_ISA_III);
585 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
586 MIPS_CPU_LLSC;
587 c->tlbsize = 32;
588 break;
589 case PRID_IMP_R4600:
590 c->cputype = CPU_R4600;
591 __cpu_name[cpu] = "R4600";
592 set_isa(c, MIPS_CPU_ISA_III);
593 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
594 MIPS_CPU_LLSC;
595 c->tlbsize = 48;
596 break;
597 #if 0
598 case PRID_IMP_R4650:
599 /*
600 * This processor doesn't have an MMU, so it's not
601 * "real easy" to run Linux on it. It is left purely
602 * for documentation. Commented out because it shares
603 * it's c0_prid id number with the TX3900.
604 */
605 c->cputype = CPU_R4650;
606 __cpu_name[cpu] = "R4650";
607 set_isa(c, MIPS_CPU_ISA_III);
608 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
609 c->tlbsize = 48;
610 break;
611 #endif
612 case PRID_IMP_TX39:
613 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
614
615 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
616 c->cputype = CPU_TX3927;
617 __cpu_name[cpu] = "TX3927";
618 c->tlbsize = 64;
619 } else {
620 switch (c->processor_id & PRID_REV_MASK) {
621 case PRID_REV_TX3912:
622 c->cputype = CPU_TX3912;
623 __cpu_name[cpu] = "TX3912";
624 c->tlbsize = 32;
625 break;
626 case PRID_REV_TX3922:
627 c->cputype = CPU_TX3922;
628 __cpu_name[cpu] = "TX3922";
629 c->tlbsize = 64;
630 break;
631 }
632 }
633 break;
634 case PRID_IMP_R4700:
635 c->cputype = CPU_R4700;
636 __cpu_name[cpu] = "R4700";
637 set_isa(c, MIPS_CPU_ISA_III);
638 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
639 MIPS_CPU_LLSC;
640 c->tlbsize = 48;
641 break;
642 case PRID_IMP_TX49:
643 c->cputype = CPU_TX49XX;
644 __cpu_name[cpu] = "R49XX";
645 set_isa(c, MIPS_CPU_ISA_III);
646 c->options = R4K_OPTS | MIPS_CPU_LLSC;
647 if (!(c->processor_id & 0x08))
648 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
649 c->tlbsize = 48;
650 break;
651 case PRID_IMP_R5000:
652 c->cputype = CPU_R5000;
653 __cpu_name[cpu] = "R5000";
654 set_isa(c, MIPS_CPU_ISA_IV);
655 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
656 MIPS_CPU_LLSC;
657 c->tlbsize = 48;
658 break;
659 case PRID_IMP_R5432:
660 c->cputype = CPU_R5432;
661 __cpu_name[cpu] = "R5432";
662 set_isa(c, MIPS_CPU_ISA_IV);
663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
664 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
665 c->tlbsize = 48;
666 break;
667 case PRID_IMP_R5500:
668 c->cputype = CPU_R5500;
669 __cpu_name[cpu] = "R5500";
670 set_isa(c, MIPS_CPU_ISA_IV);
671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
672 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
673 c->tlbsize = 48;
674 break;
675 case PRID_IMP_NEVADA:
676 c->cputype = CPU_NEVADA;
677 __cpu_name[cpu] = "Nevada";
678 set_isa(c, MIPS_CPU_ISA_IV);
679 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
680 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
681 c->tlbsize = 48;
682 break;
683 case PRID_IMP_R6000:
684 c->cputype = CPU_R6000;
685 __cpu_name[cpu] = "R6000";
686 set_isa(c, MIPS_CPU_ISA_II);
687 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
688 MIPS_CPU_LLSC;
689 c->tlbsize = 32;
690 break;
691 case PRID_IMP_R6000A:
692 c->cputype = CPU_R6000A;
693 __cpu_name[cpu] = "R6000A";
694 set_isa(c, MIPS_CPU_ISA_II);
695 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
696 MIPS_CPU_LLSC;
697 c->tlbsize = 32;
698 break;
699 case PRID_IMP_RM7000:
700 c->cputype = CPU_RM7000;
701 __cpu_name[cpu] = "RM7000";
702 set_isa(c, MIPS_CPU_ISA_IV);
703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 MIPS_CPU_LLSC;
705 /*
706 * Undocumented RM7000: Bit 29 in the info register of
707 * the RM7000 v2.0 indicates if the TLB has 48 or 64
708 * entries.
709 *
710 * 29 1 => 64 entry JTLB
711 * 0 => 48 entry JTLB
712 */
713 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
714 break;
715 case PRID_IMP_R8000:
716 c->cputype = CPU_R8000;
717 __cpu_name[cpu] = "RM8000";
718 set_isa(c, MIPS_CPU_ISA_IV);
719 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
720 MIPS_CPU_FPU | MIPS_CPU_32FPR |
721 MIPS_CPU_LLSC;
722 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
723 break;
724 case PRID_IMP_R10000:
725 c->cputype = CPU_R10000;
726 __cpu_name[cpu] = "R10000";
727 set_isa(c, MIPS_CPU_ISA_IV);
728 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
729 MIPS_CPU_FPU | MIPS_CPU_32FPR |
730 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
731 MIPS_CPU_LLSC;
732 c->tlbsize = 64;
733 break;
734 case PRID_IMP_R12000:
735 c->cputype = CPU_R12000;
736 __cpu_name[cpu] = "R12000";
737 set_isa(c, MIPS_CPU_ISA_IV);
738 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
739 MIPS_CPU_FPU | MIPS_CPU_32FPR |
740 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
741 MIPS_CPU_LLSC;
742 c->tlbsize = 64;
743 break;
744 case PRID_IMP_R14000:
745 c->cputype = CPU_R14000;
746 __cpu_name[cpu] = "R14000";
747 set_isa(c, MIPS_CPU_ISA_IV);
748 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
749 MIPS_CPU_FPU | MIPS_CPU_32FPR |
750 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
751 MIPS_CPU_LLSC;
752 c->tlbsize = 64;
753 break;
754 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
755 switch (c->processor_id & PRID_REV_MASK) {
756 case PRID_REV_LOONGSON2E:
757 c->cputype = CPU_LOONGSON2;
758 __cpu_name[cpu] = "ICT Loongson-2";
759 set_elf_platform(cpu, "loongson2e");
760 break;
761 case PRID_REV_LOONGSON2F:
762 c->cputype = CPU_LOONGSON2;
763 __cpu_name[cpu] = "ICT Loongson-2";
764 set_elf_platform(cpu, "loongson2f");
765 break;
766 case PRID_REV_LOONGSON3A:
767 c->cputype = CPU_LOONGSON3;
768 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
769 __cpu_name[cpu] = "ICT Loongson-3";
770 set_elf_platform(cpu, "loongson3a");
771 break;
772 case PRID_REV_LOONGSON3B_R1:
773 case PRID_REV_LOONGSON3B_R2:
774 c->cputype = CPU_LOONGSON3;
775 __cpu_name[cpu] = "ICT Loongson-3";
776 set_elf_platform(cpu, "loongson3b");
777 break;
778 }
779
780 set_isa(c, MIPS_CPU_ISA_III);
781 c->options = R4K_OPTS |
782 MIPS_CPU_FPU | MIPS_CPU_LLSC |
783 MIPS_CPU_32FPR;
784 c->tlbsize = 64;
785 break;
786 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
787 decode_configs(c);
788
789 c->cputype = CPU_LOONGSON1;
790
791 switch (c->processor_id & PRID_REV_MASK) {
792 case PRID_REV_LOONGSON1B:
793 __cpu_name[cpu] = "Loongson 1B";
794 break;
795 }
796
797 break;
798 }
799 }
800
801 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
802 {
803 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
804 switch (c->processor_id & PRID_IMP_MASK) {
805 case PRID_IMP_4KC:
806 c->cputype = CPU_4KC;
807 c->writecombine = _CACHE_UNCACHED;
808 __cpu_name[cpu] = "MIPS 4Kc";
809 break;
810 case PRID_IMP_4KEC:
811 case PRID_IMP_4KECR2:
812 c->cputype = CPU_4KEC;
813 c->writecombine = _CACHE_UNCACHED;
814 __cpu_name[cpu] = "MIPS 4KEc";
815 break;
816 case PRID_IMP_4KSC:
817 case PRID_IMP_4KSD:
818 c->cputype = CPU_4KSC;
819 c->writecombine = _CACHE_UNCACHED;
820 __cpu_name[cpu] = "MIPS 4KSc";
821 break;
822 case PRID_IMP_5KC:
823 c->cputype = CPU_5KC;
824 c->writecombine = _CACHE_UNCACHED;
825 __cpu_name[cpu] = "MIPS 5Kc";
826 break;
827 case PRID_IMP_5KE:
828 c->cputype = CPU_5KE;
829 c->writecombine = _CACHE_UNCACHED;
830 __cpu_name[cpu] = "MIPS 5KE";
831 break;
832 case PRID_IMP_20KC:
833 c->cputype = CPU_20KC;
834 c->writecombine = _CACHE_UNCACHED;
835 __cpu_name[cpu] = "MIPS 20Kc";
836 break;
837 case PRID_IMP_24K:
838 c->cputype = CPU_24K;
839 c->writecombine = _CACHE_UNCACHED;
840 __cpu_name[cpu] = "MIPS 24Kc";
841 break;
842 case PRID_IMP_24KE:
843 c->cputype = CPU_24K;
844 c->writecombine = _CACHE_UNCACHED;
845 __cpu_name[cpu] = "MIPS 24KEc";
846 break;
847 case PRID_IMP_25KF:
848 c->cputype = CPU_25KF;
849 c->writecombine = _CACHE_UNCACHED;
850 __cpu_name[cpu] = "MIPS 25Kc";
851 break;
852 case PRID_IMP_34K:
853 c->cputype = CPU_34K;
854 c->writecombine = _CACHE_UNCACHED;
855 __cpu_name[cpu] = "MIPS 34Kc";
856 break;
857 case PRID_IMP_74K:
858 c->cputype = CPU_74K;
859 c->writecombine = _CACHE_UNCACHED;
860 __cpu_name[cpu] = "MIPS 74Kc";
861 break;
862 case PRID_IMP_M14KC:
863 c->cputype = CPU_M14KC;
864 c->writecombine = _CACHE_UNCACHED;
865 __cpu_name[cpu] = "MIPS M14Kc";
866 break;
867 case PRID_IMP_M14KEC:
868 c->cputype = CPU_M14KEC;
869 c->writecombine = _CACHE_UNCACHED;
870 __cpu_name[cpu] = "MIPS M14KEc";
871 break;
872 case PRID_IMP_1004K:
873 c->cputype = CPU_1004K;
874 c->writecombine = _CACHE_UNCACHED;
875 __cpu_name[cpu] = "MIPS 1004Kc";
876 break;
877 case PRID_IMP_1074K:
878 c->cputype = CPU_1074K;
879 c->writecombine = _CACHE_UNCACHED;
880 __cpu_name[cpu] = "MIPS 1074Kc";
881 break;
882 case PRID_IMP_INTERAPTIV_UP:
883 c->cputype = CPU_INTERAPTIV;
884 __cpu_name[cpu] = "MIPS interAptiv";
885 break;
886 case PRID_IMP_INTERAPTIV_MP:
887 c->cputype = CPU_INTERAPTIV;
888 __cpu_name[cpu] = "MIPS interAptiv (multi)";
889 break;
890 case PRID_IMP_PROAPTIV_UP:
891 c->cputype = CPU_PROAPTIV;
892 __cpu_name[cpu] = "MIPS proAptiv";
893 break;
894 case PRID_IMP_PROAPTIV_MP:
895 c->cputype = CPU_PROAPTIV;
896 __cpu_name[cpu] = "MIPS proAptiv (multi)";
897 break;
898 case PRID_IMP_P5600:
899 c->cputype = CPU_P5600;
900 __cpu_name[cpu] = "MIPS P5600";
901 break;
902 case PRID_IMP_M5150:
903 c->cputype = CPU_M5150;
904 __cpu_name[cpu] = "MIPS M5150";
905 break;
906 }
907
908 decode_configs(c);
909
910 spram_config();
911 }
912
913 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
914 {
915 decode_configs(c);
916 switch (c->processor_id & PRID_IMP_MASK) {
917 case PRID_IMP_AU1_REV1:
918 case PRID_IMP_AU1_REV2:
919 c->cputype = CPU_ALCHEMY;
920 switch ((c->processor_id >> 24) & 0xff) {
921 case 0:
922 __cpu_name[cpu] = "Au1000";
923 break;
924 case 1:
925 __cpu_name[cpu] = "Au1500";
926 break;
927 case 2:
928 __cpu_name[cpu] = "Au1100";
929 break;
930 case 3:
931 __cpu_name[cpu] = "Au1550";
932 break;
933 case 4:
934 __cpu_name[cpu] = "Au1200";
935 if ((c->processor_id & PRID_REV_MASK) == 2)
936 __cpu_name[cpu] = "Au1250";
937 break;
938 case 5:
939 __cpu_name[cpu] = "Au1210";
940 break;
941 default:
942 __cpu_name[cpu] = "Au1xxx";
943 break;
944 }
945 break;
946 }
947 }
948
949 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
950 {
951 decode_configs(c);
952
953 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
954 switch (c->processor_id & PRID_IMP_MASK) {
955 case PRID_IMP_SB1:
956 c->cputype = CPU_SB1;
957 __cpu_name[cpu] = "SiByte SB1";
958 /* FPU in pass1 is known to have issues. */
959 if ((c->processor_id & PRID_REV_MASK) < 0x02)
960 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
961 break;
962 case PRID_IMP_SB1A:
963 c->cputype = CPU_SB1A;
964 __cpu_name[cpu] = "SiByte SB1A";
965 break;
966 }
967 }
968
969 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
970 {
971 decode_configs(c);
972 switch (c->processor_id & PRID_IMP_MASK) {
973 case PRID_IMP_SR71000:
974 c->cputype = CPU_SR71000;
975 __cpu_name[cpu] = "Sandcraft SR71000";
976 c->scache.ways = 8;
977 c->tlbsize = 64;
978 break;
979 }
980 }
981
982 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
983 {
984 decode_configs(c);
985 switch (c->processor_id & PRID_IMP_MASK) {
986 case PRID_IMP_PR4450:
987 c->cputype = CPU_PR4450;
988 __cpu_name[cpu] = "Philips PR4450";
989 set_isa(c, MIPS_CPU_ISA_M32R1);
990 break;
991 }
992 }
993
994 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
995 {
996 decode_configs(c);
997 switch (c->processor_id & PRID_IMP_MASK) {
998 case PRID_IMP_BMIPS32_REV4:
999 case PRID_IMP_BMIPS32_REV8:
1000 c->cputype = CPU_BMIPS32;
1001 __cpu_name[cpu] = "Broadcom BMIPS32";
1002 set_elf_platform(cpu, "bmips32");
1003 break;
1004 case PRID_IMP_BMIPS3300:
1005 case PRID_IMP_BMIPS3300_ALT:
1006 case PRID_IMP_BMIPS3300_BUG:
1007 c->cputype = CPU_BMIPS3300;
1008 __cpu_name[cpu] = "Broadcom BMIPS3300";
1009 set_elf_platform(cpu, "bmips3300");
1010 break;
1011 case PRID_IMP_BMIPS43XX: {
1012 int rev = c->processor_id & PRID_REV_MASK;
1013
1014 if (rev >= PRID_REV_BMIPS4380_LO &&
1015 rev <= PRID_REV_BMIPS4380_HI) {
1016 c->cputype = CPU_BMIPS4380;
1017 __cpu_name[cpu] = "Broadcom BMIPS4380";
1018 set_elf_platform(cpu, "bmips4380");
1019 } else {
1020 c->cputype = CPU_BMIPS4350;
1021 __cpu_name[cpu] = "Broadcom BMIPS4350";
1022 set_elf_platform(cpu, "bmips4350");
1023 }
1024 break;
1025 }
1026 case PRID_IMP_BMIPS5000:
1027 c->cputype = CPU_BMIPS5000;
1028 __cpu_name[cpu] = "Broadcom BMIPS5000";
1029 set_elf_platform(cpu, "bmips5000");
1030 c->options |= MIPS_CPU_ULRI;
1031 break;
1032 }
1033 }
1034
1035 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1036 {
1037 decode_configs(c);
1038 switch (c->processor_id & PRID_IMP_MASK) {
1039 case PRID_IMP_CAVIUM_CN38XX:
1040 case PRID_IMP_CAVIUM_CN31XX:
1041 case PRID_IMP_CAVIUM_CN30XX:
1042 c->cputype = CPU_CAVIUM_OCTEON;
1043 __cpu_name[cpu] = "Cavium Octeon";
1044 goto platform;
1045 case PRID_IMP_CAVIUM_CN58XX:
1046 case PRID_IMP_CAVIUM_CN56XX:
1047 case PRID_IMP_CAVIUM_CN50XX:
1048 case PRID_IMP_CAVIUM_CN52XX:
1049 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1050 __cpu_name[cpu] = "Cavium Octeon+";
1051 platform:
1052 set_elf_platform(cpu, "octeon");
1053 break;
1054 case PRID_IMP_CAVIUM_CN61XX:
1055 case PRID_IMP_CAVIUM_CN63XX:
1056 case PRID_IMP_CAVIUM_CN66XX:
1057 case PRID_IMP_CAVIUM_CN68XX:
1058 case PRID_IMP_CAVIUM_CNF71XX:
1059 c->cputype = CPU_CAVIUM_OCTEON2;
1060 __cpu_name[cpu] = "Cavium Octeon II";
1061 set_elf_platform(cpu, "octeon2");
1062 break;
1063 case PRID_IMP_CAVIUM_CN70XX:
1064 case PRID_IMP_CAVIUM_CN78XX:
1065 c->cputype = CPU_CAVIUM_OCTEON3;
1066 __cpu_name[cpu] = "Cavium Octeon III";
1067 set_elf_platform(cpu, "octeon3");
1068 break;
1069 default:
1070 printk(KERN_INFO "Unknown Octeon chip!\n");
1071 c->cputype = CPU_UNKNOWN;
1072 break;
1073 }
1074 }
1075
1076 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1077 {
1078 decode_configs(c);
1079 /* JZRISC does not implement the CP0 counter. */
1080 c->options &= ~MIPS_CPU_COUNTER;
1081 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1082 switch (c->processor_id & PRID_IMP_MASK) {
1083 case PRID_IMP_JZRISC:
1084 c->cputype = CPU_JZRISC;
1085 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1086 __cpu_name[cpu] = "Ingenic JZRISC";
1087 break;
1088 default:
1089 panic("Unknown Ingenic Processor ID!");
1090 break;
1091 }
1092 }
1093
1094 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1095 {
1096 decode_configs(c);
1097
1098 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1099 c->cputype = CPU_ALCHEMY;
1100 __cpu_name[cpu] = "Au1300";
1101 /* following stuff is not for Alchemy */
1102 return;
1103 }
1104
1105 c->options = (MIPS_CPU_TLB |
1106 MIPS_CPU_4KEX |
1107 MIPS_CPU_COUNTER |
1108 MIPS_CPU_DIVEC |
1109 MIPS_CPU_WATCH |
1110 MIPS_CPU_EJTAG |
1111 MIPS_CPU_LLSC);
1112
1113 switch (c->processor_id & PRID_IMP_MASK) {
1114 case PRID_IMP_NETLOGIC_XLP2XX:
1115 case PRID_IMP_NETLOGIC_XLP9XX:
1116 case PRID_IMP_NETLOGIC_XLP5XX:
1117 c->cputype = CPU_XLP;
1118 __cpu_name[cpu] = "Broadcom XLPII";
1119 break;
1120
1121 case PRID_IMP_NETLOGIC_XLP8XX:
1122 case PRID_IMP_NETLOGIC_XLP3XX:
1123 c->cputype = CPU_XLP;
1124 __cpu_name[cpu] = "Netlogic XLP";
1125 break;
1126
1127 case PRID_IMP_NETLOGIC_XLR732:
1128 case PRID_IMP_NETLOGIC_XLR716:
1129 case PRID_IMP_NETLOGIC_XLR532:
1130 case PRID_IMP_NETLOGIC_XLR308:
1131 case PRID_IMP_NETLOGIC_XLR532C:
1132 case PRID_IMP_NETLOGIC_XLR516C:
1133 case PRID_IMP_NETLOGIC_XLR508C:
1134 case PRID_IMP_NETLOGIC_XLR308C:
1135 c->cputype = CPU_XLR;
1136 __cpu_name[cpu] = "Netlogic XLR";
1137 break;
1138
1139 case PRID_IMP_NETLOGIC_XLS608:
1140 case PRID_IMP_NETLOGIC_XLS408:
1141 case PRID_IMP_NETLOGIC_XLS404:
1142 case PRID_IMP_NETLOGIC_XLS208:
1143 case PRID_IMP_NETLOGIC_XLS204:
1144 case PRID_IMP_NETLOGIC_XLS108:
1145 case PRID_IMP_NETLOGIC_XLS104:
1146 case PRID_IMP_NETLOGIC_XLS616B:
1147 case PRID_IMP_NETLOGIC_XLS608B:
1148 case PRID_IMP_NETLOGIC_XLS416B:
1149 case PRID_IMP_NETLOGIC_XLS412B:
1150 case PRID_IMP_NETLOGIC_XLS408B:
1151 case PRID_IMP_NETLOGIC_XLS404B:
1152 c->cputype = CPU_XLR;
1153 __cpu_name[cpu] = "Netlogic XLS";
1154 break;
1155
1156 default:
1157 pr_info("Unknown Netlogic chip id [%02x]!\n",
1158 c->processor_id);
1159 c->cputype = CPU_XLR;
1160 break;
1161 }
1162
1163 if (c->cputype == CPU_XLP) {
1164 set_isa(c, MIPS_CPU_ISA_M64R2);
1165 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1166 /* This will be updated again after all threads are woken up */
1167 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1168 } else {
1169 set_isa(c, MIPS_CPU_ISA_M64R1);
1170 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1171 }
1172 c->kscratch_mask = 0xf;
1173 }
1174
1175 #ifdef CONFIG_64BIT
1176 /* For use by uaccess.h */
1177 u64 __ua_limit;
1178 EXPORT_SYMBOL(__ua_limit);
1179 #endif
1180
1181 const char *__cpu_name[NR_CPUS];
1182 const char *__elf_platform;
1183
1184 void cpu_probe(void)
1185 {
1186 struct cpuinfo_mips *c = &current_cpu_data;
1187 unsigned int cpu = smp_processor_id();
1188
1189 c->processor_id = PRID_IMP_UNKNOWN;
1190 c->fpu_id = FPIR_IMP_NONE;
1191 c->cputype = CPU_UNKNOWN;
1192 c->writecombine = _CACHE_UNCACHED;
1193
1194 c->processor_id = read_c0_prid();
1195 switch (c->processor_id & PRID_COMP_MASK) {
1196 case PRID_COMP_LEGACY:
1197 cpu_probe_legacy(c, cpu);
1198 break;
1199 case PRID_COMP_MIPS:
1200 cpu_probe_mips(c, cpu);
1201 break;
1202 case PRID_COMP_ALCHEMY:
1203 cpu_probe_alchemy(c, cpu);
1204 break;
1205 case PRID_COMP_SIBYTE:
1206 cpu_probe_sibyte(c, cpu);
1207 break;
1208 case PRID_COMP_BROADCOM:
1209 cpu_probe_broadcom(c, cpu);
1210 break;
1211 case PRID_COMP_SANDCRAFT:
1212 cpu_probe_sandcraft(c, cpu);
1213 break;
1214 case PRID_COMP_NXP:
1215 cpu_probe_nxp(c, cpu);
1216 break;
1217 case PRID_COMP_CAVIUM:
1218 cpu_probe_cavium(c, cpu);
1219 break;
1220 case PRID_COMP_INGENIC:
1221 cpu_probe_ingenic(c, cpu);
1222 break;
1223 case PRID_COMP_NETLOGIC:
1224 cpu_probe_netlogic(c, cpu);
1225 break;
1226 }
1227
1228 BUG_ON(!__cpu_name[cpu]);
1229 BUG_ON(c->cputype == CPU_UNKNOWN);
1230
1231 /*
1232 * Platform code can force the cpu type to optimize code
1233 * generation. In that case be sure the cpu type is correctly
1234 * manually setup otherwise it could trigger some nasty bugs.
1235 */
1236 BUG_ON(current_cpu_type() != c->cputype);
1237
1238 if (mips_fpu_disabled)
1239 c->options &= ~MIPS_CPU_FPU;
1240
1241 if (mips_dsp_disabled)
1242 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1243
1244 if (mips_htw_disabled) {
1245 c->options &= ~MIPS_CPU_HTW;
1246 write_c0_pwctl(read_c0_pwctl() &
1247 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1248 }
1249
1250 if (c->options & MIPS_CPU_FPU) {
1251 c->fpu_id = cpu_get_fpu_id();
1252
1253 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1254 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1255 if (c->fpu_id & MIPS_FPIR_3D)
1256 c->ases |= MIPS_ASE_MIPS3D;
1257 }
1258 }
1259
1260 if (cpu_has_mips_r2) {
1261 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1262 /* R2 has Performance Counter Interrupt indicator */
1263 c->options |= MIPS_CPU_PCI;
1264 }
1265 else
1266 c->srsets = 1;
1267
1268 if (cpu_has_msa) {
1269 c->msa_id = cpu_get_msa_id();
1270 WARN(c->msa_id & MSA_IR_WRPF,
1271 "Vector register partitioning unimplemented!");
1272 }
1273
1274 cpu_probe_vmbits(c);
1275
1276 #ifdef CONFIG_64BIT
1277 if (cpu == 0)
1278 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1279 #endif
1280 }
1281
1282 void cpu_report(void)
1283 {
1284 struct cpuinfo_mips *c = &current_cpu_data;
1285
1286 pr_info("CPU%d revision is: %08x (%s)\n",
1287 smp_processor_id(), c->processor_id, cpu_name_string());
1288 if (c->options & MIPS_CPU_FPU)
1289 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1290 if (cpu_has_msa)
1291 pr_info("MSA revision is: %08x\n", c->msa_id);
1292 }
Linux kernel - Deliverables
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