projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[media] omap3isp: Replace cpu_is_omap3630() with ISP revision check
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
26 #include <asm/elf.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
29
30 /*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
39
40 static void r3081_wait(void)
41 {
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44 }
45
46 static void r39xx_wait(void)
47 {
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52 }
53
54 extern void r4k_wait(void);
55
56 /*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63 void r4k_wait_irqoff(void)
64 {
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74 }
75
76 /*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80 static void rm7k_wait_irqoff(void)
81 {
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95 }
96
97 /*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102 static void au1k_wait(void)
103 {
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116 }
117
118 static int __initdata nowait;
119
120 static int __init wait_disable(char *s)
121 {
122 nowait = 1;
123
124 return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 static int __cpuinitdata mips_fpu_disabled;
130
131 static int __init fpu_disable(char *s)
132 {
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137 }
138
139 __setup("nofpu", fpu_disable);
140
141 int __cpuinitdata mips_dsp_disabled;
142
143 static int __init dsp_disable(char *s)
144 {
145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
146 mips_dsp_disabled = 1;
147
148 return 1;
149 }
150
151 __setup("nodsp", dsp_disable);
152
153 void __init check_wait(void)
154 {
155 struct cpuinfo_mips *c = &current_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171 /* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
203 case CPU_M14KC:
204 case CPU_24K:
205 case CPU_34K:
206 case CPU_1004K:
207 cpu_wait = r4k_wait;
208 if (read_c0_config7() & MIPS_CONF7_WII)
209 cpu_wait = r4k_wait_irqoff;
210 break;
211
212 case CPU_74K:
213 cpu_wait = r4k_wait;
214 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
215 cpu_wait = r4k_wait_irqoff;
216 break;
217
218 case CPU_TX49XX:
219 cpu_wait = r4k_wait_irqoff;
220 break;
221 case CPU_ALCHEMY:
222 cpu_wait = au1k_wait;
223 break;
224 case CPU_20KC:
225 /*
226 * WAIT on Rev1.0 has E1, E2, E3 and E16.
227 * WAIT on Rev2.0 and Rev3.0 has E16.
228 * Rev3.1 WAIT is nop, why bother
229 */
230 if ((c->processor_id & 0xff) <= 0x64)
231 break;
232
233 /*
234 * Another rev is incremeting c0_count at a reduced clock
235 * rate while in WAIT mode. So we basically have the choice
236 * between using the cp0 timer as clocksource or avoiding
237 * the WAIT instruction. Until more details are known,
238 * disable the use of WAIT for 20Kc entirely.
239 cpu_wait = r4k_wait;
240 */
241 break;
242 case CPU_RM9000:
243 if ((c->processor_id & 0x00ff) >= 0x40)
244 cpu_wait = r4k_wait;
245 break;
246 default:
247 break;
248 }
249 }
250
251 static inline void check_errata(void)
252 {
253 struct cpuinfo_mips *c = &current_cpu_data;
254
255 switch (c->cputype) {
256 case CPU_34K:
257 /*
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/SMTC/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
261 */
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
264 break;
265 default:
266 break;
267 }
268 }
269
270 void __init check_bugs32(void)
271 {
272 check_errata();
273 }
274
275 /*
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
279 */
280 static inline int cpu_has_confreg(void)
281 {
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
286
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
290 write_c0_conf(cfg);
291 return size1 != size2;
292 #else
293 return 0;
294 #endif
295 }
296
297 static inline void set_elf_platform(int cpu, const char *plat)
298 {
299 if (cpu == 0)
300 __elf_platform = plat;
301 }
302
303 /*
304 * Get the FPU Implementation/Revision.
305 */
306 static inline unsigned long cpu_get_fpu_id(void)
307 {
308 unsigned long tmp, fpu_id;
309
310 tmp = read_c0_status();
311 __enable_fpu();
312 fpu_id = read_32bit_cp1_register(CP1_REVISION);
313 write_c0_status(tmp);
314 return fpu_id;
315 }
316
317 /*
318 * Check the CPU has an FPU the official way.
319 */
320 static inline int __cpu_has_fpu(void)
321 {
322 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
323 }
324
325 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
326 {
327 #ifdef __NEED_VMBITS_PROBE
328 write_c0_entryhi(0x3fffffffffffe000ULL);
329 back_to_back_c0_hazard();
330 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
331 #endif
332 }
333
334 static char unknown_isa[] __cpuinitdata = KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
336
337 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
338 {
339 unsigned int config0;
340 int isa;
341
342 config0 = read_c0_config();
343
344 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
345 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
347 switch (isa) {
348 case 0:
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
350 case 0:
351 c->isa_level = MIPS_CPU_ISA_M32R1;
352 break;
353 case 1:
354 c->isa_level = MIPS_CPU_ISA_M32R2;
355 break;
356 default:
357 goto unknown;
358 }
359 break;
360 case 2:
361 switch ((config0 & MIPS_CONF_AR) >> 10) {
362 case 0:
363 c->isa_level = MIPS_CPU_ISA_M64R1;
364 break;
365 case 1:
366 c->isa_level = MIPS_CPU_ISA_M64R2;
367 break;
368 default:
369 goto unknown;
370 }
371 break;
372 default:
373 goto unknown;
374 }
375
376 return config0 & MIPS_CONF_M;
377
378 unknown:
379 panic(unknown_isa, config0);
380 }
381
382 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
383 {
384 unsigned int config1;
385
386 config1 = read_c0_config1();
387
388 if (config1 & MIPS_CONF1_MD)
389 c->ases |= MIPS_ASE_MDMX;
390 if (config1 & MIPS_CONF1_WR)
391 c->options |= MIPS_CPU_WATCH;
392 if (config1 & MIPS_CONF1_CA)
393 c->ases |= MIPS_ASE_MIPS16;
394 if (config1 & MIPS_CONF1_EP)
395 c->options |= MIPS_CPU_EJTAG;
396 if (config1 & MIPS_CONF1_FP) {
397 c->options |= MIPS_CPU_FPU;
398 c->options |= MIPS_CPU_32FPR;
399 }
400 if (cpu_has_tlb)
401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
402
403 return config1 & MIPS_CONF_M;
404 }
405
406 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
407 {
408 unsigned int config2;
409
410 config2 = read_c0_config2();
411
412 if (config2 & MIPS_CONF2_SL)
413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
414
415 return config2 & MIPS_CONF_M;
416 }
417
418 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
419 {
420 unsigned int config3;
421
422 config3 = read_c0_config3();
423
424 if (config3 & MIPS_CONF3_SM) {
425 c->ases |= MIPS_ASE_SMARTMIPS;
426 c->options |= MIPS_CPU_RIXI;
427 }
428 if (config3 & MIPS_CONF3_RXI)
429 c->options |= MIPS_CPU_RIXI;
430 if (config3 & MIPS_CONF3_DSP)
431 c->ases |= MIPS_ASE_DSP;
432 if (config3 & MIPS_CONF3_DSP2P)
433 c->ases |= MIPS_ASE_DSP2P;
434 if (config3 & MIPS_CONF3_VINT)
435 c->options |= MIPS_CPU_VINT;
436 if (config3 & MIPS_CONF3_VEIC)
437 c->options |= MIPS_CPU_VEIC;
438 if (config3 & MIPS_CONF3_MT)
439 c->ases |= MIPS_ASE_MIPSMT;
440 if (config3 & MIPS_CONF3_ULRI)
441 c->options |= MIPS_CPU_ULRI;
442
443 return config3 & MIPS_CONF_M;
444 }
445
446 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
447 {
448 unsigned int config4;
449
450 config4 = read_c0_config4();
451
452 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
453 && cpu_has_tlb)
454 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
455
456 c->kscratch_mask = (config4 >> 16) & 0xff;
457
458 return config4 & MIPS_CONF_M;
459 }
460
461 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
462 {
463 int ok;
464
465 /* MIPS32 or MIPS64 compliant CPU. */
466 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
467 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
468
469 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
470
471 ok = decode_config0(c); /* Read Config registers. */
472 BUG_ON(!ok); /* Arch spec violation! */
473 if (ok)
474 ok = decode_config1(c);
475 if (ok)
476 ok = decode_config2(c);
477 if (ok)
478 ok = decode_config3(c);
479 if (ok)
480 ok = decode_config4(c);
481
482 mips_probe_watch_registers(c);
483
484 if (cpu_has_mips_r2)
485 c->core = read_c0_ebase() & 0x3ff;
486 }
487
488 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
489 | MIPS_CPU_COUNTER)
490
491 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
492 {
493 switch (c->processor_id & 0xff00) {
494 case PRID_IMP_R2000:
495 c->cputype = CPU_R2000;
496 __cpu_name[cpu] = "R2000";
497 c->isa_level = MIPS_CPU_ISA_I;
498 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
499 MIPS_CPU_NOFPUEX;
500 if (__cpu_has_fpu())
501 c->options |= MIPS_CPU_FPU;
502 c->tlbsize = 64;
503 break;
504 case PRID_IMP_R3000:
505 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
506 if (cpu_has_confreg()) {
507 c->cputype = CPU_R3081E;
508 __cpu_name[cpu] = "R3081";
509 } else {
510 c->cputype = CPU_R3000A;
511 __cpu_name[cpu] = "R3000A";
512 }
513 break;
514 } else {
515 c->cputype = CPU_R3000;
516 __cpu_name[cpu] = "R3000";
517 }
518 c->isa_level = MIPS_CPU_ISA_I;
519 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
520 MIPS_CPU_NOFPUEX;
521 if (__cpu_has_fpu())
522 c->options |= MIPS_CPU_FPU;
523 c->tlbsize = 64;
524 break;
525 case PRID_IMP_R4000:
526 if (read_c0_config() & CONF_SC) {
527 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
528 c->cputype = CPU_R4400PC;
529 __cpu_name[cpu] = "R4400PC";
530 } else {
531 c->cputype = CPU_R4000PC;
532 __cpu_name[cpu] = "R4000PC";
533 }
534 } else {
535 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
536 c->cputype = CPU_R4400SC;
537 __cpu_name[cpu] = "R4400SC";
538 } else {
539 c->cputype = CPU_R4000SC;
540 __cpu_name[cpu] = "R4000SC";
541 }
542 }
543
544 c->isa_level = MIPS_CPU_ISA_III;
545 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
546 MIPS_CPU_WATCH | MIPS_CPU_VCE |
547 MIPS_CPU_LLSC;
548 c->tlbsize = 48;
549 break;
550 case PRID_IMP_VR41XX:
551 switch (c->processor_id & 0xf0) {
552 case PRID_REV_VR4111:
553 c->cputype = CPU_VR4111;
554 __cpu_name[cpu] = "NEC VR4111";
555 break;
556 case PRID_REV_VR4121:
557 c->cputype = CPU_VR4121;
558 __cpu_name[cpu] = "NEC VR4121";
559 break;
560 case PRID_REV_VR4122:
561 if ((c->processor_id & 0xf) < 0x3) {
562 c->cputype = CPU_VR4122;
563 __cpu_name[cpu] = "NEC VR4122";
564 } else {
565 c->cputype = CPU_VR4181A;
566 __cpu_name[cpu] = "NEC VR4181A";
567 }
568 break;
569 case PRID_REV_VR4130:
570 if ((c->processor_id & 0xf) < 0x4) {
571 c->cputype = CPU_VR4131;
572 __cpu_name[cpu] = "NEC VR4131";
573 } else {
574 c->cputype = CPU_VR4133;
575 __cpu_name[cpu] = "NEC VR4133";
576 }
577 break;
578 default:
579 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
580 c->cputype = CPU_VR41XX;
581 __cpu_name[cpu] = "NEC Vr41xx";
582 break;
583 }
584 c->isa_level = MIPS_CPU_ISA_III;
585 c->options = R4K_OPTS;
586 c->tlbsize = 32;
587 break;
588 case PRID_IMP_R4300:
589 c->cputype = CPU_R4300;
590 __cpu_name[cpu] = "R4300";
591 c->isa_level = MIPS_CPU_ISA_III;
592 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
593 MIPS_CPU_LLSC;
594 c->tlbsize = 32;
595 break;
596 case PRID_IMP_R4600:
597 c->cputype = CPU_R4600;
598 __cpu_name[cpu] = "R4600";
599 c->isa_level = MIPS_CPU_ISA_III;
600 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
601 MIPS_CPU_LLSC;
602 c->tlbsize = 48;
603 break;
604 #if 0
605 case PRID_IMP_R4650:
606 /*
607 * This processor doesn't have an MMU, so it's not
608 * "real easy" to run Linux on it. It is left purely
609 * for documentation. Commented out because it shares
610 * it's c0_prid id number with the TX3900.
611 */
612 c->cputype = CPU_R4650;
613 __cpu_name[cpu] = "R4650";
614 c->isa_level = MIPS_CPU_ISA_III;
615 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
616 c->tlbsize = 48;
617 break;
618 #endif
619 case PRID_IMP_TX39:
620 c->isa_level = MIPS_CPU_ISA_I;
621 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
622
623 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
624 c->cputype = CPU_TX3927;
625 __cpu_name[cpu] = "TX3927";
626 c->tlbsize = 64;
627 } else {
628 switch (c->processor_id & 0xff) {
629 case PRID_REV_TX3912:
630 c->cputype = CPU_TX3912;
631 __cpu_name[cpu] = "TX3912";
632 c->tlbsize = 32;
633 break;
634 case PRID_REV_TX3922:
635 c->cputype = CPU_TX3922;
636 __cpu_name[cpu] = "TX3922";
637 c->tlbsize = 64;
638 break;
639 }
640 }
641 break;
642 case PRID_IMP_R4700:
643 c->cputype = CPU_R4700;
644 __cpu_name[cpu] = "R4700";
645 c->isa_level = MIPS_CPU_ISA_III;
646 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
647 MIPS_CPU_LLSC;
648 c->tlbsize = 48;
649 break;
650 case PRID_IMP_TX49:
651 c->cputype = CPU_TX49XX;
652 __cpu_name[cpu] = "R49XX";
653 c->isa_level = MIPS_CPU_ISA_III;
654 c->options = R4K_OPTS | MIPS_CPU_LLSC;
655 if (!(c->processor_id & 0x08))
656 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
657 c->tlbsize = 48;
658 break;
659 case PRID_IMP_R5000:
660 c->cputype = CPU_R5000;
661 __cpu_name[cpu] = "R5000";
662 c->isa_level = MIPS_CPU_ISA_IV;
663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
664 MIPS_CPU_LLSC;
665 c->tlbsize = 48;
666 break;
667 case PRID_IMP_R5432:
668 c->cputype = CPU_R5432;
669 __cpu_name[cpu] = "R5432";
670 c->isa_level = MIPS_CPU_ISA_IV;
671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
672 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
673 c->tlbsize = 48;
674 break;
675 case PRID_IMP_R5500:
676 c->cputype = CPU_R5500;
677 __cpu_name[cpu] = "R5500";
678 c->isa_level = MIPS_CPU_ISA_IV;
679 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
680 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
681 c->tlbsize = 48;
682 break;
683 case PRID_IMP_NEVADA:
684 c->cputype = CPU_NEVADA;
685 __cpu_name[cpu] = "Nevada";
686 c->isa_level = MIPS_CPU_ISA_IV;
687 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
688 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
689 c->tlbsize = 48;
690 break;
691 case PRID_IMP_R6000:
692 c->cputype = CPU_R6000;
693 __cpu_name[cpu] = "R6000";
694 c->isa_level = MIPS_CPU_ISA_II;
695 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
696 MIPS_CPU_LLSC;
697 c->tlbsize = 32;
698 break;
699 case PRID_IMP_R6000A:
700 c->cputype = CPU_R6000A;
701 __cpu_name[cpu] = "R6000A";
702 c->isa_level = MIPS_CPU_ISA_II;
703 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
704 MIPS_CPU_LLSC;
705 c->tlbsize = 32;
706 break;
707 case PRID_IMP_RM7000:
708 c->cputype = CPU_RM7000;
709 __cpu_name[cpu] = "RM7000";
710 c->isa_level = MIPS_CPU_ISA_IV;
711 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
712 MIPS_CPU_LLSC;
713 /*
714 * Undocumented RM7000: Bit 29 in the info register of
715 * the RM7000 v2.0 indicates if the TLB has 48 or 64
716 * entries.
717 *
718 * 29 1 => 64 entry JTLB
719 * 0 => 48 entry JTLB
720 */
721 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
722 break;
723 case PRID_IMP_RM9000:
724 c->cputype = CPU_RM9000;
725 __cpu_name[cpu] = "RM9000";
726 c->isa_level = MIPS_CPU_ISA_IV;
727 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
728 MIPS_CPU_LLSC;
729 /*
730 * Bit 29 in the info register of the RM9000
731 * indicates if the TLB has 48 or 64 entries.
732 *
733 * 29 1 => 64 entry JTLB
734 * 0 => 48 entry JTLB
735 */
736 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
737 break;
738 case PRID_IMP_R8000:
739 c->cputype = CPU_R8000;
740 __cpu_name[cpu] = "RM8000";
741 c->isa_level = MIPS_CPU_ISA_IV;
742 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
743 MIPS_CPU_FPU | MIPS_CPU_32FPR |
744 MIPS_CPU_LLSC;
745 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
746 break;
747 case PRID_IMP_R10000:
748 c->cputype = CPU_R10000;
749 __cpu_name[cpu] = "R10000";
750 c->isa_level = MIPS_CPU_ISA_IV;
751 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
752 MIPS_CPU_FPU | MIPS_CPU_32FPR |
753 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
754 MIPS_CPU_LLSC;
755 c->tlbsize = 64;
756 break;
757 case PRID_IMP_R12000:
758 c->cputype = CPU_R12000;
759 __cpu_name[cpu] = "R12000";
760 c->isa_level = MIPS_CPU_ISA_IV;
761 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
762 MIPS_CPU_FPU | MIPS_CPU_32FPR |
763 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
764 MIPS_CPU_LLSC;
765 c->tlbsize = 64;
766 break;
767 case PRID_IMP_R14000:
768 c->cputype = CPU_R14000;
769 __cpu_name[cpu] = "R14000";
770 c->isa_level = MIPS_CPU_ISA_IV;
771 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
772 MIPS_CPU_FPU | MIPS_CPU_32FPR |
773 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
774 MIPS_CPU_LLSC;
775 c->tlbsize = 64;
776 break;
777 case PRID_IMP_LOONGSON2:
778 c->cputype = CPU_LOONGSON2;
779 __cpu_name[cpu] = "ICT Loongson-2";
780
781 switch (c->processor_id & PRID_REV_MASK) {
782 case PRID_REV_LOONGSON2E:
783 set_elf_platform(cpu, "loongson2e");
784 break;
785 case PRID_REV_LOONGSON2F:
786 set_elf_platform(cpu, "loongson2f");
787 break;
788 }
789
790 c->isa_level = MIPS_CPU_ISA_III;
791 c->options = R4K_OPTS |
792 MIPS_CPU_FPU | MIPS_CPU_LLSC |
793 MIPS_CPU_32FPR;
794 c->tlbsize = 64;
795 break;
796 case PRID_IMP_LOONGSON1:
797 decode_configs(c);
798
799 c->cputype = CPU_LOONGSON1;
800
801 switch (c->processor_id & PRID_REV_MASK) {
802 case PRID_REV_LOONGSON1B:
803 __cpu_name[cpu] = "Loongson 1B";
804 break;
805 }
806
807 break;
808 }
809 }
810
811 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
812 {
813 decode_configs(c);
814 switch (c->processor_id & 0xff00) {
815 case PRID_IMP_4KC:
816 c->cputype = CPU_4KC;
817 __cpu_name[cpu] = "MIPS 4Kc";
818 break;
819 case PRID_IMP_4KEC:
820 case PRID_IMP_4KECR2:
821 c->cputype = CPU_4KEC;
822 __cpu_name[cpu] = "MIPS 4KEc";
823 break;
824 case PRID_IMP_4KSC:
825 case PRID_IMP_4KSD:
826 c->cputype = CPU_4KSC;
827 __cpu_name[cpu] = "MIPS 4KSc";
828 break;
829 case PRID_IMP_5KC:
830 c->cputype = CPU_5KC;
831 __cpu_name[cpu] = "MIPS 5Kc";
832 break;
833 case PRID_IMP_5KE:
834 c->cputype = CPU_5KE;
835 __cpu_name[cpu] = "MIPS 5KE";
836 break;
837 case PRID_IMP_20KC:
838 c->cputype = CPU_20KC;
839 __cpu_name[cpu] = "MIPS 20Kc";
840 break;
841 case PRID_IMP_24K:
842 case PRID_IMP_24KE:
843 c->cputype = CPU_24K;
844 __cpu_name[cpu] = "MIPS 24Kc";
845 break;
846 case PRID_IMP_25KF:
847 c->cputype = CPU_25KF;
848 __cpu_name[cpu] = "MIPS 25Kc";
849 break;
850 case PRID_IMP_34K:
851 c->cputype = CPU_34K;
852 __cpu_name[cpu] = "MIPS 34Kc";
853 break;
854 case PRID_IMP_74K:
855 c->cputype = CPU_74K;
856 __cpu_name[cpu] = "MIPS 74Kc";
857 break;
858 case PRID_IMP_M14KC:
859 c->cputype = CPU_M14KC;
860 __cpu_name[cpu] = "MIPS M14Kc";
861 break;
862 case PRID_IMP_1004K:
863 c->cputype = CPU_1004K;
864 __cpu_name[cpu] = "MIPS 1004Kc";
865 break;
866 case PRID_IMP_1074K:
867 c->cputype = CPU_74K;
868 __cpu_name[cpu] = "MIPS 1074Kc";
869 break;
870 }
871
872 spram_config();
873 }
874
875 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
876 {
877 decode_configs(c);
878 switch (c->processor_id & 0xff00) {
879 case PRID_IMP_AU1_REV1:
880 case PRID_IMP_AU1_REV2:
881 c->cputype = CPU_ALCHEMY;
882 switch ((c->processor_id >> 24) & 0xff) {
883 case 0:
884 __cpu_name[cpu] = "Au1000";
885 break;
886 case 1:
887 __cpu_name[cpu] = "Au1500";
888 break;
889 case 2:
890 __cpu_name[cpu] = "Au1100";
891 break;
892 case 3:
893 __cpu_name[cpu] = "Au1550";
894 break;
895 case 4:
896 __cpu_name[cpu] = "Au1200";
897 if ((c->processor_id & 0xff) == 2)
898 __cpu_name[cpu] = "Au1250";
899 break;
900 case 5:
901 __cpu_name[cpu] = "Au1210";
902 break;
903 default:
904 __cpu_name[cpu] = "Au1xxx";
905 break;
906 }
907 break;
908 }
909 }
910
911 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
912 {
913 decode_configs(c);
914
915 switch (c->processor_id & 0xff00) {
916 case PRID_IMP_SB1:
917 c->cputype = CPU_SB1;
918 __cpu_name[cpu] = "SiByte SB1";
919 /* FPU in pass1 is known to have issues. */
920 if ((c->processor_id & 0xff) < 0x02)
921 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
922 break;
923 case PRID_IMP_SB1A:
924 c->cputype = CPU_SB1A;
925 __cpu_name[cpu] = "SiByte SB1A";
926 break;
927 }
928 }
929
930 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
931 {
932 decode_configs(c);
933 switch (c->processor_id & 0xff00) {
934 case PRID_IMP_SR71000:
935 c->cputype = CPU_SR71000;
936 __cpu_name[cpu] = "Sandcraft SR71000";
937 c->scache.ways = 8;
938 c->tlbsize = 64;
939 break;
940 }
941 }
942
943 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
944 {
945 decode_configs(c);
946 switch (c->processor_id & 0xff00) {
947 case PRID_IMP_PR4450:
948 c->cputype = CPU_PR4450;
949 __cpu_name[cpu] = "Philips PR4450";
950 c->isa_level = MIPS_CPU_ISA_M32R1;
951 break;
952 }
953 }
954
955 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
956 {
957 decode_configs(c);
958 switch (c->processor_id & 0xff00) {
959 case PRID_IMP_BMIPS32_REV4:
960 case PRID_IMP_BMIPS32_REV8:
961 c->cputype = CPU_BMIPS32;
962 __cpu_name[cpu] = "Broadcom BMIPS32";
963 set_elf_platform(cpu, "bmips32");
964 break;
965 case PRID_IMP_BMIPS3300:
966 case PRID_IMP_BMIPS3300_ALT:
967 case PRID_IMP_BMIPS3300_BUG:
968 c->cputype = CPU_BMIPS3300;
969 __cpu_name[cpu] = "Broadcom BMIPS3300";
970 set_elf_platform(cpu, "bmips3300");
971 break;
972 case PRID_IMP_BMIPS43XX: {
973 int rev = c->processor_id & 0xff;
974
975 if (rev >= PRID_REV_BMIPS4380_LO &&
976 rev <= PRID_REV_BMIPS4380_HI) {
977 c->cputype = CPU_BMIPS4380;
978 __cpu_name[cpu] = "Broadcom BMIPS4380";
979 set_elf_platform(cpu, "bmips4380");
980 } else {
981 c->cputype = CPU_BMIPS4350;
982 __cpu_name[cpu] = "Broadcom BMIPS4350";
983 set_elf_platform(cpu, "bmips4350");
984 }
985 break;
986 }
987 case PRID_IMP_BMIPS5000:
988 c->cputype = CPU_BMIPS5000;
989 __cpu_name[cpu] = "Broadcom BMIPS5000";
990 set_elf_platform(cpu, "bmips5000");
991 c->options |= MIPS_CPU_ULRI;
992 break;
993 }
994 }
995
996 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
997 {
998 decode_configs(c);
999 switch (c->processor_id & 0xff00) {
1000 case PRID_IMP_CAVIUM_CN38XX:
1001 case PRID_IMP_CAVIUM_CN31XX:
1002 case PRID_IMP_CAVIUM_CN30XX:
1003 c->cputype = CPU_CAVIUM_OCTEON;
1004 __cpu_name[cpu] = "Cavium Octeon";
1005 goto platform;
1006 case PRID_IMP_CAVIUM_CN58XX:
1007 case PRID_IMP_CAVIUM_CN56XX:
1008 case PRID_IMP_CAVIUM_CN50XX:
1009 case PRID_IMP_CAVIUM_CN52XX:
1010 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1011 __cpu_name[cpu] = "Cavium Octeon+";
1012 platform:
1013 set_elf_platform(cpu, "octeon");
1014 break;
1015 case PRID_IMP_CAVIUM_CN61XX:
1016 case PRID_IMP_CAVIUM_CN63XX:
1017 case PRID_IMP_CAVIUM_CN66XX:
1018 case PRID_IMP_CAVIUM_CN68XX:
1019 c->cputype = CPU_CAVIUM_OCTEON2;
1020 __cpu_name[cpu] = "Cavium Octeon II";
1021 set_elf_platform(cpu, "octeon2");
1022 break;
1023 default:
1024 printk(KERN_INFO "Unknown Octeon chip!\n");
1025 c->cputype = CPU_UNKNOWN;
1026 break;
1027 }
1028 }
1029
1030 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1031 {
1032 decode_configs(c);
1033 /* JZRISC does not implement the CP0 counter. */
1034 c->options &= ~MIPS_CPU_COUNTER;
1035 switch (c->processor_id & 0xff00) {
1036 case PRID_IMP_JZRISC:
1037 c->cputype = CPU_JZRISC;
1038 __cpu_name[cpu] = "Ingenic JZRISC";
1039 break;
1040 default:
1041 panic("Unknown Ingenic Processor ID!");
1042 break;
1043 }
1044 }
1045
1046 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1047 {
1048 decode_configs(c);
1049
1050 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1051 c->cputype = CPU_ALCHEMY;
1052 __cpu_name[cpu] = "Au1300";
1053 /* following stuff is not for Alchemy */
1054 return;
1055 }
1056
1057 c->options = (MIPS_CPU_TLB |
1058 MIPS_CPU_4KEX |
1059 MIPS_CPU_COUNTER |
1060 MIPS_CPU_DIVEC |
1061 MIPS_CPU_WATCH |
1062 MIPS_CPU_EJTAG |
1063 MIPS_CPU_LLSC);
1064
1065 switch (c->processor_id & 0xff00) {
1066 case PRID_IMP_NETLOGIC_XLP8XX:
1067 case PRID_IMP_NETLOGIC_XLP3XX:
1068 c->cputype = CPU_XLP;
1069 __cpu_name[cpu] = "Netlogic XLP";
1070 break;
1071
1072 case PRID_IMP_NETLOGIC_XLR732:
1073 case PRID_IMP_NETLOGIC_XLR716:
1074 case PRID_IMP_NETLOGIC_XLR532:
1075 case PRID_IMP_NETLOGIC_XLR308:
1076 case PRID_IMP_NETLOGIC_XLR532C:
1077 case PRID_IMP_NETLOGIC_XLR516C:
1078 case PRID_IMP_NETLOGIC_XLR508C:
1079 case PRID_IMP_NETLOGIC_XLR308C:
1080 c->cputype = CPU_XLR;
1081 __cpu_name[cpu] = "Netlogic XLR";
1082 break;
1083
1084 case PRID_IMP_NETLOGIC_XLS608:
1085 case PRID_IMP_NETLOGIC_XLS408:
1086 case PRID_IMP_NETLOGIC_XLS404:
1087 case PRID_IMP_NETLOGIC_XLS208:
1088 case PRID_IMP_NETLOGIC_XLS204:
1089 case PRID_IMP_NETLOGIC_XLS108:
1090 case PRID_IMP_NETLOGIC_XLS104:
1091 case PRID_IMP_NETLOGIC_XLS616B:
1092 case PRID_IMP_NETLOGIC_XLS608B:
1093 case PRID_IMP_NETLOGIC_XLS416B:
1094 case PRID_IMP_NETLOGIC_XLS412B:
1095 case PRID_IMP_NETLOGIC_XLS408B:
1096 case PRID_IMP_NETLOGIC_XLS404B:
1097 c->cputype = CPU_XLR;
1098 __cpu_name[cpu] = "Netlogic XLS";
1099 break;
1100
1101 default:
1102 pr_info("Unknown Netlogic chip id [%02x]!\n",
1103 c->processor_id);
1104 c->cputype = CPU_XLR;
1105 break;
1106 }
1107
1108 if (c->cputype == CPU_XLP) {
1109 c->isa_level = MIPS_CPU_ISA_M64R2;
1110 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1111 /* This will be updated again after all threads are woken up */
1112 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1113 } else {
1114 c->isa_level = MIPS_CPU_ISA_M64R1;
1115 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1116 }
1117 }
1118
1119 #ifdef CONFIG_64BIT
1120 /* For use by uaccess.h */
1121 u64 __ua_limit;
1122 EXPORT_SYMBOL(__ua_limit);
1123 #endif
1124
1125 const char *__cpu_name[NR_CPUS];
1126 const char *__elf_platform;
1127
1128 __cpuinit void cpu_probe(void)
1129 {
1130 struct cpuinfo_mips *c = &current_cpu_data;
1131 unsigned int cpu = smp_processor_id();
1132
1133 c->processor_id = PRID_IMP_UNKNOWN;
1134 c->fpu_id = FPIR_IMP_NONE;
1135 c->cputype = CPU_UNKNOWN;
1136
1137 c->processor_id = read_c0_prid();
1138 switch (c->processor_id & 0xff0000) {
1139 case PRID_COMP_LEGACY:
1140 cpu_probe_legacy(c, cpu);
1141 break;
1142 case PRID_COMP_MIPS:
1143 cpu_probe_mips(c, cpu);
1144 break;
1145 case PRID_COMP_ALCHEMY:
1146 cpu_probe_alchemy(c, cpu);
1147 break;
1148 case PRID_COMP_SIBYTE:
1149 cpu_probe_sibyte(c, cpu);
1150 break;
1151 case PRID_COMP_BROADCOM:
1152 cpu_probe_broadcom(c, cpu);
1153 break;
1154 case PRID_COMP_SANDCRAFT:
1155 cpu_probe_sandcraft(c, cpu);
1156 break;
1157 case PRID_COMP_NXP:
1158 cpu_probe_nxp(c, cpu);
1159 break;
1160 case PRID_COMP_CAVIUM:
1161 cpu_probe_cavium(c, cpu);
1162 break;
1163 case PRID_COMP_INGENIC:
1164 cpu_probe_ingenic(c, cpu);
1165 break;
1166 case PRID_COMP_NETLOGIC:
1167 cpu_probe_netlogic(c, cpu);
1168 break;
1169 }
1170
1171 BUG_ON(!__cpu_name[cpu]);
1172 BUG_ON(c->cputype == CPU_UNKNOWN);
1173
1174 /*
1175 * Platform code can force the cpu type to optimize code
1176 * generation. In that case be sure the cpu type is correctly
1177 * manually setup otherwise it could trigger some nasty bugs.
1178 */
1179 BUG_ON(current_cpu_type() != c->cputype);
1180
1181 if (mips_fpu_disabled)
1182 c->options &= ~MIPS_CPU_FPU;
1183
1184 if (mips_dsp_disabled)
1185 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1186
1187 if (c->options & MIPS_CPU_FPU) {
1188 c->fpu_id = cpu_get_fpu_id();
1189
1190 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1191 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1192 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1193 c->isa_level == MIPS_CPU_ISA_M64R2) {
1194 if (c->fpu_id & MIPS_FPIR_3D)
1195 c->ases |= MIPS_ASE_MIPS3D;
1196 }
1197 }
1198
1199 if (cpu_has_mips_r2) {
1200 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1201 /* R2 has Performance Counter Interrupt indicator */
1202 c->options |= MIPS_CPU_PCI;
1203 }
1204 else
1205 c->srsets = 1;
1206
1207 cpu_probe_vmbits(c);
1208
1209 #ifdef CONFIG_64BIT
1210 if (cpu == 0)
1211 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1212 #endif
1213 }
1214
1215 __cpuinit void cpu_report(void)
1216 {
1217 struct cpuinfo_mips *c = &current_cpu_data;
1218
1219 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1220 c->processor_id, cpu_name_string());
1221 if (c->options & MIPS_CPU_FPU)
1222 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1223 }
Linux kernel - Deliverables
This page took 0.058539 seconds and 5 git commands to generate.