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[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-type.h>
24 #include <asm/fpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
27 #include <asm/msa.h>
28 #include <asm/watch.h>
29 #include <asm/elf.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/spram.h>
32 #include <asm/uaccess.h>
33
34 static int mips_fpu_disabled;
35
36 static int __init fpu_disable(char *s)
37 {
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42 }
43
44 __setup("nofpu", fpu_disable);
45
46 int mips_dsp_disabled;
47
48 static int __init dsp_disable(char *s)
49 {
50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
51 mips_dsp_disabled = 1;
52
53 return 1;
54 }
55
56 __setup("nodsp", dsp_disable);
57
58 static int mips_htw_disabled;
59
60 static int __init htw_disable(char *s)
61 {
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68 }
69
70 __setup("nohtw", htw_disable);
71
72 static int mips_ftlb_disabled;
73 static int mips_has_ftlb_configured;
74
75 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
76
77 static int __init ftlb_disable(char *s)
78 {
79 unsigned int config4, mmuextdef;
80
81 /*
82 * If the core hasn't done any FTLB configuration, there is nothing
83 * for us to do here.
84 */
85 if (!mips_has_ftlb_configured)
86 return 1;
87
88 /* Disable it in the boot cpu */
89 set_ftlb_enable(&cpu_data[0], 0);
90
91 back_to_back_c0_hazard();
92
93 config4 = read_c0_config4();
94
95 /* Check that FTLB has been disabled */
96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
99 /* This should never happen */
100 pr_warn("FTLB could not be disabled!\n");
101 return 1;
102 }
103
104 mips_ftlb_disabled = 1;
105 mips_has_ftlb_configured = 0;
106
107 /*
108 * noftlb is mainly used for debug purposes so print
109 * an informative message instead of using pr_debug()
110 */
111 pr_info("FTLB has been disabled\n");
112
113 /*
114 * Some of these bits are duplicated in the decode_config4.
115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
116 * once FTLB has been disabled so undo what decode_config4 did.
117 */
118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
119 cpu_data[0].tlbsizeftlbsets;
120 cpu_data[0].tlbsizeftlbsets = 0;
121 cpu_data[0].tlbsizeftlbways = 0;
122
123 return 1;
124 }
125
126 __setup("noftlb", ftlb_disable);
127
128
129 static inline void check_errata(void)
130 {
131 struct cpuinfo_mips *c = &current_cpu_data;
132
133 switch (current_cpu_type()) {
134 case CPU_34K:
135 /*
136 * Erratum "RPS May Cause Incorrect Instruction Execution"
137 * This code only handles VPE0, any SMP/RTOS code
138 * making use of VPE1 will be responsable for that VPE.
139 */
140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
142 break;
143 default:
144 break;
145 }
146 }
147
148 void __init check_bugs32(void)
149 {
150 check_errata();
151 }
152
153 /*
154 * Probe whether cpu has config register by trying to play with
155 * alternate cache bit and see whether it matters.
156 * It's used by cpu_probe to distinguish between R3000A and R3081.
157 */
158 static inline int cpu_has_confreg(void)
159 {
160 #ifdef CONFIG_CPU_R3000
161 extern unsigned long r3k_cache_size(unsigned long);
162 unsigned long size1, size2;
163 unsigned long cfg = read_c0_conf();
164
165 size1 = r3k_cache_size(ST0_ISC);
166 write_c0_conf(cfg ^ R30XX_CONF_AC);
167 size2 = r3k_cache_size(ST0_ISC);
168 write_c0_conf(cfg);
169 return size1 != size2;
170 #else
171 return 0;
172 #endif
173 }
174
175 static inline void set_elf_platform(int cpu, const char *plat)
176 {
177 if (cpu == 0)
178 __elf_platform = plat;
179 }
180
181 /*
182 * Get the FPU Implementation/Revision.
183 */
184 static inline unsigned long cpu_get_fpu_id(void)
185 {
186 unsigned long tmp, fpu_id;
187
188 tmp = read_c0_status();
189 __enable_fpu(FPU_AS_IS);
190 fpu_id = read_32bit_cp1_register(CP1_REVISION);
191 write_c0_status(tmp);
192 return fpu_id;
193 }
194
195 /*
196 * Check the CPU has an FPU the official way.
197 */
198 static inline int __cpu_has_fpu(void)
199 {
200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
201 }
202
203 static inline unsigned long cpu_get_msa_id(void)
204 {
205 unsigned long status, msa_id;
206
207 status = read_c0_status();
208 __enable_fpu(FPU_64BIT);
209 enable_msa();
210 msa_id = read_msa_ir();
211 disable_msa();
212 write_c0_status(status);
213 return msa_id;
214 }
215
216 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
217 {
218 #ifdef __NEED_VMBITS_PROBE
219 write_c0_entryhi(0x3fffffffffffe000ULL);
220 back_to_back_c0_hazard();
221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
222 #endif
223 }
224
225 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
226 {
227 switch (isa) {
228 case MIPS_CPU_ISA_M64R2:
229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
230 case MIPS_CPU_ISA_M64R1:
231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
232 case MIPS_CPU_ISA_V:
233 c->isa_level |= MIPS_CPU_ISA_V;
234 case MIPS_CPU_ISA_IV:
235 c->isa_level |= MIPS_CPU_ISA_IV;
236 case MIPS_CPU_ISA_III:
237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
238 break;
239
240 /* R6 incompatible with everything else */
241 case MIPS_CPU_ISA_M64R6:
242 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
243 case MIPS_CPU_ISA_M32R6:
244 c->isa_level |= MIPS_CPU_ISA_M32R6;
245 /* Break here so we don't add incompatible ISAs */
246 break;
247 case MIPS_CPU_ISA_M32R2:
248 c->isa_level |= MIPS_CPU_ISA_M32R2;
249 case MIPS_CPU_ISA_M32R1:
250 c->isa_level |= MIPS_CPU_ISA_M32R1;
251 case MIPS_CPU_ISA_II:
252 c->isa_level |= MIPS_CPU_ISA_II;
253 break;
254 }
255 }
256
257 static char unknown_isa[] = KERN_ERR \
258 "Unsupported ISA type, c0.config0: %d.";
259
260 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
261 {
262
263 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
264
265 /*
266 * 0 = All TLBWR instructions go to FTLB
267 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
268 * FTLB and 1 goes to the VTLB.
269 * 2 = 7:1: As above with 7:1 ratio.
270 * 3 = 3:1: As above with 3:1 ratio.
271 *
272 * Use the linear midpoint as the probability threshold.
273 */
274 if (probability >= 12)
275 return 1;
276 else if (probability >= 6)
277 return 2;
278 else
279 /*
280 * So FTLB is less than 4 times bigger than VTLB.
281 * A 3:1 ratio can still be useful though.
282 */
283 return 3;
284 }
285
286 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
287 {
288 unsigned int config6;
289
290 /* It's implementation dependent how the FTLB can be enabled */
291 switch (c->cputype) {
292 case CPU_PROAPTIV:
293 case CPU_P5600:
294 /* proAptiv & related cores use Config6 to enable the FTLB */
295 config6 = read_c0_config6();
296 /* Clear the old probability value */
297 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
298 if (enable)
299 /* Enable FTLB */
300 write_c0_config6(config6 |
301 (calculate_ftlb_probability(c)
302 << MIPS_CONF6_FTLBP_SHIFT)
303 | MIPS_CONF6_FTLBEN);
304 else
305 /* Disable FTLB */
306 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
307 back_to_back_c0_hazard();
308 break;
309 }
310 }
311
312 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
313 {
314 unsigned int config0;
315 int isa;
316
317 config0 = read_c0_config();
318
319 /*
320 * Look for Standard TLB or Dual VTLB and FTLB
321 */
322 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
323 (((config0 & MIPS_CONF_MT) >> 7) == 4))
324 c->options |= MIPS_CPU_TLB;
325
326 isa = (config0 & MIPS_CONF_AT) >> 13;
327 switch (isa) {
328 case 0:
329 switch ((config0 & MIPS_CONF_AR) >> 10) {
330 case 0:
331 set_isa(c, MIPS_CPU_ISA_M32R1);
332 break;
333 case 1:
334 set_isa(c, MIPS_CPU_ISA_M32R2);
335 break;
336 case 2:
337 set_isa(c, MIPS_CPU_ISA_M32R6);
338 break;
339 default:
340 goto unknown;
341 }
342 break;
343 case 2:
344 switch ((config0 & MIPS_CONF_AR) >> 10) {
345 case 0:
346 set_isa(c, MIPS_CPU_ISA_M64R1);
347 break;
348 case 1:
349 set_isa(c, MIPS_CPU_ISA_M64R2);
350 break;
351 case 2:
352 set_isa(c, MIPS_CPU_ISA_M64R6);
353 break;
354 default:
355 goto unknown;
356 }
357 break;
358 default:
359 goto unknown;
360 }
361
362 return config0 & MIPS_CONF_M;
363
364 unknown:
365 panic(unknown_isa, config0);
366 }
367
368 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
369 {
370 unsigned int config1;
371
372 config1 = read_c0_config1();
373
374 if (config1 & MIPS_CONF1_MD)
375 c->ases |= MIPS_ASE_MDMX;
376 if (config1 & MIPS_CONF1_WR)
377 c->options |= MIPS_CPU_WATCH;
378 if (config1 & MIPS_CONF1_CA)
379 c->ases |= MIPS_ASE_MIPS16;
380 if (config1 & MIPS_CONF1_EP)
381 c->options |= MIPS_CPU_EJTAG;
382 if (config1 & MIPS_CONF1_FP) {
383 c->options |= MIPS_CPU_FPU;
384 c->options |= MIPS_CPU_32FPR;
385 }
386 if (cpu_has_tlb) {
387 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
388 c->tlbsizevtlb = c->tlbsize;
389 c->tlbsizeftlbsets = 0;
390 }
391
392 return config1 & MIPS_CONF_M;
393 }
394
395 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
396 {
397 unsigned int config2;
398
399 config2 = read_c0_config2();
400
401 if (config2 & MIPS_CONF2_SL)
402 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
403
404 return config2 & MIPS_CONF_M;
405 }
406
407 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
408 {
409 unsigned int config3;
410
411 config3 = read_c0_config3();
412
413 if (config3 & MIPS_CONF3_SM) {
414 c->ases |= MIPS_ASE_SMARTMIPS;
415 c->options |= MIPS_CPU_RIXI;
416 }
417 if (config3 & MIPS_CONF3_RXI)
418 c->options |= MIPS_CPU_RIXI;
419 if (config3 & MIPS_CONF3_DSP)
420 c->ases |= MIPS_ASE_DSP;
421 if (config3 & MIPS_CONF3_DSP2P)
422 c->ases |= MIPS_ASE_DSP2P;
423 if (config3 & MIPS_CONF3_VINT)
424 c->options |= MIPS_CPU_VINT;
425 if (config3 & MIPS_CONF3_VEIC)
426 c->options |= MIPS_CPU_VEIC;
427 if (config3 & MIPS_CONF3_MT)
428 c->ases |= MIPS_ASE_MIPSMT;
429 if (config3 & MIPS_CONF3_ULRI)
430 c->options |= MIPS_CPU_ULRI;
431 if (config3 & MIPS_CONF3_ISA)
432 c->options |= MIPS_CPU_MICROMIPS;
433 if (config3 & MIPS_CONF3_VZ)
434 c->ases |= MIPS_ASE_VZ;
435 if (config3 & MIPS_CONF3_SC)
436 c->options |= MIPS_CPU_SEGMENTS;
437 if (config3 & MIPS_CONF3_MSA)
438 c->ases |= MIPS_ASE_MSA;
439 /* Only tested on 32-bit cores */
440 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
441 c->htw_seq = 0;
442 c->options |= MIPS_CPU_HTW;
443 }
444 if (config3 & MIPS_CONF3_CDMM)
445 c->options |= MIPS_CPU_CDMM;
446
447 return config3 & MIPS_CONF_M;
448 }
449
450 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
451 {
452 unsigned int config4;
453 unsigned int newcf4;
454 unsigned int mmuextdef;
455 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
456
457 config4 = read_c0_config4();
458
459 if (cpu_has_tlb) {
460 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
461 c->options |= MIPS_CPU_TLBINV;
462 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
463 switch (mmuextdef) {
464 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
465 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
466 c->tlbsizevtlb = c->tlbsize;
467 break;
468 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
469 c->tlbsizevtlb +=
470 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
471 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
472 c->tlbsize = c->tlbsizevtlb;
473 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
474 /* fall through */
475 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
476 if (mips_ftlb_disabled)
477 break;
478 newcf4 = (config4 & ~ftlb_page) |
479 (page_size_ftlb(mmuextdef) <<
480 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
481 write_c0_config4(newcf4);
482 back_to_back_c0_hazard();
483 config4 = read_c0_config4();
484 if (config4 != newcf4) {
485 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
486 PAGE_SIZE, config4);
487 /* Switch FTLB off */
488 set_ftlb_enable(c, 0);
489 break;
490 }
491 c->tlbsizeftlbsets = 1 <<
492 ((config4 & MIPS_CONF4_FTLBSETS) >>
493 MIPS_CONF4_FTLBSETS_SHIFT);
494 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
495 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
496 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
497 mips_has_ftlb_configured = 1;
498 break;
499 }
500 }
501
502 c->kscratch_mask = (config4 >> 16) & 0xff;
503
504 return config4 & MIPS_CONF_M;
505 }
506
507 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
508 {
509 unsigned int config5;
510
511 config5 = read_c0_config5();
512 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
513 write_c0_config5(config5);
514
515 if (config5 & MIPS_CONF5_EVA)
516 c->options |= MIPS_CPU_EVA;
517 if (config5 & MIPS_CONF5_MRP)
518 c->options |= MIPS_CPU_MAAR;
519 if (config5 & MIPS_CONF5_LLB)
520 c->options |= MIPS_CPU_RW_LLB;
521
522 return config5 & MIPS_CONF_M;
523 }
524
525 static void decode_configs(struct cpuinfo_mips *c)
526 {
527 int ok;
528
529 /* MIPS32 or MIPS64 compliant CPU. */
530 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
531 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
532
533 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
534
535 /* Enable FTLB if present and not disabled */
536 set_ftlb_enable(c, !mips_ftlb_disabled);
537
538 ok = decode_config0(c); /* Read Config registers. */
539 BUG_ON(!ok); /* Arch spec violation! */
540 if (ok)
541 ok = decode_config1(c);
542 if (ok)
543 ok = decode_config2(c);
544 if (ok)
545 ok = decode_config3(c);
546 if (ok)
547 ok = decode_config4(c);
548 if (ok)
549 ok = decode_config5(c);
550
551 mips_probe_watch_registers(c);
552
553 if (cpu_has_rixi) {
554 /* Enable the RIXI exceptions */
555 set_c0_pagegrain(PG_IEC);
556 back_to_back_c0_hazard();
557 /* Verify the IEC bit is set */
558 if (read_c0_pagegrain() & PG_IEC)
559 c->options |= MIPS_CPU_RIXIEX;
560 }
561
562 #ifndef CONFIG_MIPS_CPS
563 if (cpu_has_mips_r2_r6) {
564 c->core = get_ebase_cpunum();
565 if (cpu_has_mipsmt)
566 c->core >>= fls(core_nvpes()) - 1;
567 }
568 #endif
569 }
570
571 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
572 | MIPS_CPU_COUNTER)
573
574 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
575 {
576 switch (c->processor_id & PRID_IMP_MASK) {
577 case PRID_IMP_R2000:
578 c->cputype = CPU_R2000;
579 __cpu_name[cpu] = "R2000";
580 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
581 MIPS_CPU_NOFPUEX;
582 if (__cpu_has_fpu())
583 c->options |= MIPS_CPU_FPU;
584 c->tlbsize = 64;
585 break;
586 case PRID_IMP_R3000:
587 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
588 if (cpu_has_confreg()) {
589 c->cputype = CPU_R3081E;
590 __cpu_name[cpu] = "R3081";
591 } else {
592 c->cputype = CPU_R3000A;
593 __cpu_name[cpu] = "R3000A";
594 }
595 } else {
596 c->cputype = CPU_R3000;
597 __cpu_name[cpu] = "R3000";
598 }
599 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
600 MIPS_CPU_NOFPUEX;
601 if (__cpu_has_fpu())
602 c->options |= MIPS_CPU_FPU;
603 c->tlbsize = 64;
604 break;
605 case PRID_IMP_R4000:
606 if (read_c0_config() & CONF_SC) {
607 if ((c->processor_id & PRID_REV_MASK) >=
608 PRID_REV_R4400) {
609 c->cputype = CPU_R4400PC;
610 __cpu_name[cpu] = "R4400PC";
611 } else {
612 c->cputype = CPU_R4000PC;
613 __cpu_name[cpu] = "R4000PC";
614 }
615 } else {
616 int cca = read_c0_config() & CONF_CM_CMASK;
617 int mc;
618
619 /*
620 * SC and MC versions can't be reliably told apart,
621 * but only the latter support coherent caching
622 * modes so assume the firmware has set the KSEG0
623 * coherency attribute reasonably (if uncached, we
624 * assume SC).
625 */
626 switch (cca) {
627 case CONF_CM_CACHABLE_CE:
628 case CONF_CM_CACHABLE_COW:
629 case CONF_CM_CACHABLE_CUW:
630 mc = 1;
631 break;
632 default:
633 mc = 0;
634 break;
635 }
636 if ((c->processor_id & PRID_REV_MASK) >=
637 PRID_REV_R4400) {
638 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
639 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
640 } else {
641 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
642 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
643 }
644 }
645
646 set_isa(c, MIPS_CPU_ISA_III);
647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
648 MIPS_CPU_WATCH | MIPS_CPU_VCE |
649 MIPS_CPU_LLSC;
650 c->tlbsize = 48;
651 break;
652 case PRID_IMP_VR41XX:
653 set_isa(c, MIPS_CPU_ISA_III);
654 c->options = R4K_OPTS;
655 c->tlbsize = 32;
656 switch (c->processor_id & 0xf0) {
657 case PRID_REV_VR4111:
658 c->cputype = CPU_VR4111;
659 __cpu_name[cpu] = "NEC VR4111";
660 break;
661 case PRID_REV_VR4121:
662 c->cputype = CPU_VR4121;
663 __cpu_name[cpu] = "NEC VR4121";
664 break;
665 case PRID_REV_VR4122:
666 if ((c->processor_id & 0xf) < 0x3) {
667 c->cputype = CPU_VR4122;
668 __cpu_name[cpu] = "NEC VR4122";
669 } else {
670 c->cputype = CPU_VR4181A;
671 __cpu_name[cpu] = "NEC VR4181A";
672 }
673 break;
674 case PRID_REV_VR4130:
675 if ((c->processor_id & 0xf) < 0x4) {
676 c->cputype = CPU_VR4131;
677 __cpu_name[cpu] = "NEC VR4131";
678 } else {
679 c->cputype = CPU_VR4133;
680 c->options |= MIPS_CPU_LLSC;
681 __cpu_name[cpu] = "NEC VR4133";
682 }
683 break;
684 default:
685 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
686 c->cputype = CPU_VR41XX;
687 __cpu_name[cpu] = "NEC Vr41xx";
688 break;
689 }
690 break;
691 case PRID_IMP_R4300:
692 c->cputype = CPU_R4300;
693 __cpu_name[cpu] = "R4300";
694 set_isa(c, MIPS_CPU_ISA_III);
695 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
696 MIPS_CPU_LLSC;
697 c->tlbsize = 32;
698 break;
699 case PRID_IMP_R4600:
700 c->cputype = CPU_R4600;
701 __cpu_name[cpu] = "R4600";
702 set_isa(c, MIPS_CPU_ISA_III);
703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 MIPS_CPU_LLSC;
705 c->tlbsize = 48;
706 break;
707 #if 0
708 case PRID_IMP_R4650:
709 /*
710 * This processor doesn't have an MMU, so it's not
711 * "real easy" to run Linux on it. It is left purely
712 * for documentation. Commented out because it shares
713 * it's c0_prid id number with the TX3900.
714 */
715 c->cputype = CPU_R4650;
716 __cpu_name[cpu] = "R4650";
717 set_isa(c, MIPS_CPU_ISA_III);
718 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
719 c->tlbsize = 48;
720 break;
721 #endif
722 case PRID_IMP_TX39:
723 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
724
725 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
726 c->cputype = CPU_TX3927;
727 __cpu_name[cpu] = "TX3927";
728 c->tlbsize = 64;
729 } else {
730 switch (c->processor_id & PRID_REV_MASK) {
731 case PRID_REV_TX3912:
732 c->cputype = CPU_TX3912;
733 __cpu_name[cpu] = "TX3912";
734 c->tlbsize = 32;
735 break;
736 case PRID_REV_TX3922:
737 c->cputype = CPU_TX3922;
738 __cpu_name[cpu] = "TX3922";
739 c->tlbsize = 64;
740 break;
741 }
742 }
743 break;
744 case PRID_IMP_R4700:
745 c->cputype = CPU_R4700;
746 __cpu_name[cpu] = "R4700";
747 set_isa(c, MIPS_CPU_ISA_III);
748 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
749 MIPS_CPU_LLSC;
750 c->tlbsize = 48;
751 break;
752 case PRID_IMP_TX49:
753 c->cputype = CPU_TX49XX;
754 __cpu_name[cpu] = "R49XX";
755 set_isa(c, MIPS_CPU_ISA_III);
756 c->options = R4K_OPTS | MIPS_CPU_LLSC;
757 if (!(c->processor_id & 0x08))
758 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
759 c->tlbsize = 48;
760 break;
761 case PRID_IMP_R5000:
762 c->cputype = CPU_R5000;
763 __cpu_name[cpu] = "R5000";
764 set_isa(c, MIPS_CPU_ISA_IV);
765 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
766 MIPS_CPU_LLSC;
767 c->tlbsize = 48;
768 break;
769 case PRID_IMP_R5432:
770 c->cputype = CPU_R5432;
771 __cpu_name[cpu] = "R5432";
772 set_isa(c, MIPS_CPU_ISA_IV);
773 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
774 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
775 c->tlbsize = 48;
776 break;
777 case PRID_IMP_R5500:
778 c->cputype = CPU_R5500;
779 __cpu_name[cpu] = "R5500";
780 set_isa(c, MIPS_CPU_ISA_IV);
781 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
782 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
783 c->tlbsize = 48;
784 break;
785 case PRID_IMP_NEVADA:
786 c->cputype = CPU_NEVADA;
787 __cpu_name[cpu] = "Nevada";
788 set_isa(c, MIPS_CPU_ISA_IV);
789 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
790 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
791 c->tlbsize = 48;
792 break;
793 case PRID_IMP_R6000:
794 c->cputype = CPU_R6000;
795 __cpu_name[cpu] = "R6000";
796 set_isa(c, MIPS_CPU_ISA_II);
797 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
798 MIPS_CPU_LLSC;
799 c->tlbsize = 32;
800 break;
801 case PRID_IMP_R6000A:
802 c->cputype = CPU_R6000A;
803 __cpu_name[cpu] = "R6000A";
804 set_isa(c, MIPS_CPU_ISA_II);
805 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
806 MIPS_CPU_LLSC;
807 c->tlbsize = 32;
808 break;
809 case PRID_IMP_RM7000:
810 c->cputype = CPU_RM7000;
811 __cpu_name[cpu] = "RM7000";
812 set_isa(c, MIPS_CPU_ISA_IV);
813 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
814 MIPS_CPU_LLSC;
815 /*
816 * Undocumented RM7000: Bit 29 in the info register of
817 * the RM7000 v2.0 indicates if the TLB has 48 or 64
818 * entries.
819 *
820 * 29 1 => 64 entry JTLB
821 * 0 => 48 entry JTLB
822 */
823 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
824 break;
825 case PRID_IMP_R8000:
826 c->cputype = CPU_R8000;
827 __cpu_name[cpu] = "RM8000";
828 set_isa(c, MIPS_CPU_ISA_IV);
829 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
830 MIPS_CPU_FPU | MIPS_CPU_32FPR |
831 MIPS_CPU_LLSC;
832 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
833 break;
834 case PRID_IMP_R10000:
835 c->cputype = CPU_R10000;
836 __cpu_name[cpu] = "R10000";
837 set_isa(c, MIPS_CPU_ISA_IV);
838 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
839 MIPS_CPU_FPU | MIPS_CPU_32FPR |
840 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
841 MIPS_CPU_LLSC;
842 c->tlbsize = 64;
843 break;
844 case PRID_IMP_R12000:
845 c->cputype = CPU_R12000;
846 __cpu_name[cpu] = "R12000";
847 set_isa(c, MIPS_CPU_ISA_IV);
848 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
849 MIPS_CPU_FPU | MIPS_CPU_32FPR |
850 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
851 MIPS_CPU_LLSC;
852 c->tlbsize = 64;
853 break;
854 case PRID_IMP_R14000:
855 if (((c->processor_id >> 4) & 0x0f) > 2) {
856 c->cputype = CPU_R16000;
857 __cpu_name[cpu] = "R16000";
858 } else {
859 c->cputype = CPU_R14000;
860 __cpu_name[cpu] = "R14000";
861 }
862 set_isa(c, MIPS_CPU_ISA_IV);
863 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
864 MIPS_CPU_FPU | MIPS_CPU_32FPR |
865 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
866 MIPS_CPU_LLSC;
867 c->tlbsize = 64;
868 break;
869 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
870 switch (c->processor_id & PRID_REV_MASK) {
871 case PRID_REV_LOONGSON2E:
872 c->cputype = CPU_LOONGSON2;
873 __cpu_name[cpu] = "ICT Loongson-2";
874 set_elf_platform(cpu, "loongson2e");
875 set_isa(c, MIPS_CPU_ISA_III);
876 break;
877 case PRID_REV_LOONGSON2F:
878 c->cputype = CPU_LOONGSON2;
879 __cpu_name[cpu] = "ICT Loongson-2";
880 set_elf_platform(cpu, "loongson2f");
881 set_isa(c, MIPS_CPU_ISA_III);
882 break;
883 case PRID_REV_LOONGSON3A:
884 c->cputype = CPU_LOONGSON3;
885 __cpu_name[cpu] = "ICT Loongson-3";
886 set_elf_platform(cpu, "loongson3a");
887 set_isa(c, MIPS_CPU_ISA_M64R1);
888 break;
889 case PRID_REV_LOONGSON3B_R1:
890 case PRID_REV_LOONGSON3B_R2:
891 c->cputype = CPU_LOONGSON3;
892 __cpu_name[cpu] = "ICT Loongson-3";
893 set_elf_platform(cpu, "loongson3b");
894 set_isa(c, MIPS_CPU_ISA_M64R1);
895 break;
896 }
897
898 c->options = R4K_OPTS |
899 MIPS_CPU_FPU | MIPS_CPU_LLSC |
900 MIPS_CPU_32FPR;
901 c->tlbsize = 64;
902 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
903 break;
904 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
905 decode_configs(c);
906
907 c->cputype = CPU_LOONGSON1;
908
909 switch (c->processor_id & PRID_REV_MASK) {
910 case PRID_REV_LOONGSON1B:
911 __cpu_name[cpu] = "Loongson 1B";
912 break;
913 }
914
915 break;
916 }
917 }
918
919 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
920 {
921 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
922 switch (c->processor_id & PRID_IMP_MASK) {
923 case PRID_IMP_QEMU_GENERIC:
924 c->writecombine = _CACHE_UNCACHED;
925 c->cputype = CPU_QEMU_GENERIC;
926 __cpu_name[cpu] = "MIPS GENERIC QEMU";
927 break;
928 case PRID_IMP_4KC:
929 c->cputype = CPU_4KC;
930 c->writecombine = _CACHE_UNCACHED;
931 __cpu_name[cpu] = "MIPS 4Kc";
932 break;
933 case PRID_IMP_4KEC:
934 case PRID_IMP_4KECR2:
935 c->cputype = CPU_4KEC;
936 c->writecombine = _CACHE_UNCACHED;
937 __cpu_name[cpu] = "MIPS 4KEc";
938 break;
939 case PRID_IMP_4KSC:
940 case PRID_IMP_4KSD:
941 c->cputype = CPU_4KSC;
942 c->writecombine = _CACHE_UNCACHED;
943 __cpu_name[cpu] = "MIPS 4KSc";
944 break;
945 case PRID_IMP_5KC:
946 c->cputype = CPU_5KC;
947 c->writecombine = _CACHE_UNCACHED;
948 __cpu_name[cpu] = "MIPS 5Kc";
949 break;
950 case PRID_IMP_5KE:
951 c->cputype = CPU_5KE;
952 c->writecombine = _CACHE_UNCACHED;
953 __cpu_name[cpu] = "MIPS 5KE";
954 break;
955 case PRID_IMP_20KC:
956 c->cputype = CPU_20KC;
957 c->writecombine = _CACHE_UNCACHED;
958 __cpu_name[cpu] = "MIPS 20Kc";
959 break;
960 case PRID_IMP_24K:
961 c->cputype = CPU_24K;
962 c->writecombine = _CACHE_UNCACHED;
963 __cpu_name[cpu] = "MIPS 24Kc";
964 break;
965 case PRID_IMP_24KE:
966 c->cputype = CPU_24K;
967 c->writecombine = _CACHE_UNCACHED;
968 __cpu_name[cpu] = "MIPS 24KEc";
969 break;
970 case PRID_IMP_25KF:
971 c->cputype = CPU_25KF;
972 c->writecombine = _CACHE_UNCACHED;
973 __cpu_name[cpu] = "MIPS 25Kc";
974 break;
975 case PRID_IMP_34K:
976 c->cputype = CPU_34K;
977 c->writecombine = _CACHE_UNCACHED;
978 __cpu_name[cpu] = "MIPS 34Kc";
979 break;
980 case PRID_IMP_74K:
981 c->cputype = CPU_74K;
982 c->writecombine = _CACHE_UNCACHED;
983 __cpu_name[cpu] = "MIPS 74Kc";
984 break;
985 case PRID_IMP_M14KC:
986 c->cputype = CPU_M14KC;
987 c->writecombine = _CACHE_UNCACHED;
988 __cpu_name[cpu] = "MIPS M14Kc";
989 break;
990 case PRID_IMP_M14KEC:
991 c->cputype = CPU_M14KEC;
992 c->writecombine = _CACHE_UNCACHED;
993 __cpu_name[cpu] = "MIPS M14KEc";
994 break;
995 case PRID_IMP_1004K:
996 c->cputype = CPU_1004K;
997 c->writecombine = _CACHE_UNCACHED;
998 __cpu_name[cpu] = "MIPS 1004Kc";
999 break;
1000 case PRID_IMP_1074K:
1001 c->cputype = CPU_1074K;
1002 c->writecombine = _CACHE_UNCACHED;
1003 __cpu_name[cpu] = "MIPS 1074Kc";
1004 break;
1005 case PRID_IMP_INTERAPTIV_UP:
1006 c->cputype = CPU_INTERAPTIV;
1007 __cpu_name[cpu] = "MIPS interAptiv";
1008 break;
1009 case PRID_IMP_INTERAPTIV_MP:
1010 c->cputype = CPU_INTERAPTIV;
1011 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1012 break;
1013 case PRID_IMP_PROAPTIV_UP:
1014 c->cputype = CPU_PROAPTIV;
1015 __cpu_name[cpu] = "MIPS proAptiv";
1016 break;
1017 case PRID_IMP_PROAPTIV_MP:
1018 c->cputype = CPU_PROAPTIV;
1019 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1020 break;
1021 case PRID_IMP_P5600:
1022 c->cputype = CPU_P5600;
1023 __cpu_name[cpu] = "MIPS P5600";
1024 break;
1025 case PRID_IMP_M5150:
1026 c->cputype = CPU_M5150;
1027 __cpu_name[cpu] = "MIPS M5150";
1028 break;
1029 }
1030
1031 decode_configs(c);
1032
1033 spram_config();
1034 }
1035
1036 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1037 {
1038 decode_configs(c);
1039 switch (c->processor_id & PRID_IMP_MASK) {
1040 case PRID_IMP_AU1_REV1:
1041 case PRID_IMP_AU1_REV2:
1042 c->cputype = CPU_ALCHEMY;
1043 switch ((c->processor_id >> 24) & 0xff) {
1044 case 0:
1045 __cpu_name[cpu] = "Au1000";
1046 break;
1047 case 1:
1048 __cpu_name[cpu] = "Au1500";
1049 break;
1050 case 2:
1051 __cpu_name[cpu] = "Au1100";
1052 break;
1053 case 3:
1054 __cpu_name[cpu] = "Au1550";
1055 break;
1056 case 4:
1057 __cpu_name[cpu] = "Au1200";
1058 if ((c->processor_id & PRID_REV_MASK) == 2)
1059 __cpu_name[cpu] = "Au1250";
1060 break;
1061 case 5:
1062 __cpu_name[cpu] = "Au1210";
1063 break;
1064 default:
1065 __cpu_name[cpu] = "Au1xxx";
1066 break;
1067 }
1068 break;
1069 }
1070 }
1071
1072 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1073 {
1074 decode_configs(c);
1075
1076 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1077 switch (c->processor_id & PRID_IMP_MASK) {
1078 case PRID_IMP_SB1:
1079 c->cputype = CPU_SB1;
1080 __cpu_name[cpu] = "SiByte SB1";
1081 /* FPU in pass1 is known to have issues. */
1082 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1083 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1084 break;
1085 case PRID_IMP_SB1A:
1086 c->cputype = CPU_SB1A;
1087 __cpu_name[cpu] = "SiByte SB1A";
1088 break;
1089 }
1090 }
1091
1092 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1093 {
1094 decode_configs(c);
1095 switch (c->processor_id & PRID_IMP_MASK) {
1096 case PRID_IMP_SR71000:
1097 c->cputype = CPU_SR71000;
1098 __cpu_name[cpu] = "Sandcraft SR71000";
1099 c->scache.ways = 8;
1100 c->tlbsize = 64;
1101 break;
1102 }
1103 }
1104
1105 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1106 {
1107 decode_configs(c);
1108 switch (c->processor_id & PRID_IMP_MASK) {
1109 case PRID_IMP_PR4450:
1110 c->cputype = CPU_PR4450;
1111 __cpu_name[cpu] = "Philips PR4450";
1112 set_isa(c, MIPS_CPU_ISA_M32R1);
1113 break;
1114 }
1115 }
1116
1117 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1118 {
1119 decode_configs(c);
1120 switch (c->processor_id & PRID_IMP_MASK) {
1121 case PRID_IMP_BMIPS32_REV4:
1122 case PRID_IMP_BMIPS32_REV8:
1123 c->cputype = CPU_BMIPS32;
1124 __cpu_name[cpu] = "Broadcom BMIPS32";
1125 set_elf_platform(cpu, "bmips32");
1126 break;
1127 case PRID_IMP_BMIPS3300:
1128 case PRID_IMP_BMIPS3300_ALT:
1129 case PRID_IMP_BMIPS3300_BUG:
1130 c->cputype = CPU_BMIPS3300;
1131 __cpu_name[cpu] = "Broadcom BMIPS3300";
1132 set_elf_platform(cpu, "bmips3300");
1133 break;
1134 case PRID_IMP_BMIPS43XX: {
1135 int rev = c->processor_id & PRID_REV_MASK;
1136
1137 if (rev >= PRID_REV_BMIPS4380_LO &&
1138 rev <= PRID_REV_BMIPS4380_HI) {
1139 c->cputype = CPU_BMIPS4380;
1140 __cpu_name[cpu] = "Broadcom BMIPS4380";
1141 set_elf_platform(cpu, "bmips4380");
1142 } else {
1143 c->cputype = CPU_BMIPS4350;
1144 __cpu_name[cpu] = "Broadcom BMIPS4350";
1145 set_elf_platform(cpu, "bmips4350");
1146 }
1147 break;
1148 }
1149 case PRID_IMP_BMIPS5000:
1150 case PRID_IMP_BMIPS5200:
1151 c->cputype = CPU_BMIPS5000;
1152 __cpu_name[cpu] = "Broadcom BMIPS5000";
1153 set_elf_platform(cpu, "bmips5000");
1154 c->options |= MIPS_CPU_ULRI;
1155 break;
1156 }
1157 }
1158
1159 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1160 {
1161 decode_configs(c);
1162 switch (c->processor_id & PRID_IMP_MASK) {
1163 case PRID_IMP_CAVIUM_CN38XX:
1164 case PRID_IMP_CAVIUM_CN31XX:
1165 case PRID_IMP_CAVIUM_CN30XX:
1166 c->cputype = CPU_CAVIUM_OCTEON;
1167 __cpu_name[cpu] = "Cavium Octeon";
1168 goto platform;
1169 case PRID_IMP_CAVIUM_CN58XX:
1170 case PRID_IMP_CAVIUM_CN56XX:
1171 case PRID_IMP_CAVIUM_CN50XX:
1172 case PRID_IMP_CAVIUM_CN52XX:
1173 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1174 __cpu_name[cpu] = "Cavium Octeon+";
1175 platform:
1176 set_elf_platform(cpu, "octeon");
1177 break;
1178 case PRID_IMP_CAVIUM_CN61XX:
1179 case PRID_IMP_CAVIUM_CN63XX:
1180 case PRID_IMP_CAVIUM_CN66XX:
1181 case PRID_IMP_CAVIUM_CN68XX:
1182 case PRID_IMP_CAVIUM_CNF71XX:
1183 c->cputype = CPU_CAVIUM_OCTEON2;
1184 __cpu_name[cpu] = "Cavium Octeon II";
1185 set_elf_platform(cpu, "octeon2");
1186 break;
1187 case PRID_IMP_CAVIUM_CN70XX:
1188 case PRID_IMP_CAVIUM_CN78XX:
1189 c->cputype = CPU_CAVIUM_OCTEON3;
1190 __cpu_name[cpu] = "Cavium Octeon III";
1191 set_elf_platform(cpu, "octeon3");
1192 break;
1193 default:
1194 printk(KERN_INFO "Unknown Octeon chip!\n");
1195 c->cputype = CPU_UNKNOWN;
1196 break;
1197 }
1198 }
1199
1200 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1201 {
1202 decode_configs(c);
1203 /* JZRISC does not implement the CP0 counter. */
1204 c->options &= ~MIPS_CPU_COUNTER;
1205 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1206 switch (c->processor_id & PRID_IMP_MASK) {
1207 case PRID_IMP_JZRISC:
1208 c->cputype = CPU_JZRISC;
1209 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1210 __cpu_name[cpu] = "Ingenic JZRISC";
1211 break;
1212 default:
1213 panic("Unknown Ingenic Processor ID!");
1214 break;
1215 }
1216 }
1217
1218 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1219 {
1220 decode_configs(c);
1221
1222 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1223 c->cputype = CPU_ALCHEMY;
1224 __cpu_name[cpu] = "Au1300";
1225 /* following stuff is not for Alchemy */
1226 return;
1227 }
1228
1229 c->options = (MIPS_CPU_TLB |
1230 MIPS_CPU_4KEX |
1231 MIPS_CPU_COUNTER |
1232 MIPS_CPU_DIVEC |
1233 MIPS_CPU_WATCH |
1234 MIPS_CPU_EJTAG |
1235 MIPS_CPU_LLSC);
1236
1237 switch (c->processor_id & PRID_IMP_MASK) {
1238 case PRID_IMP_NETLOGIC_XLP2XX:
1239 case PRID_IMP_NETLOGIC_XLP9XX:
1240 case PRID_IMP_NETLOGIC_XLP5XX:
1241 c->cputype = CPU_XLP;
1242 __cpu_name[cpu] = "Broadcom XLPII";
1243 break;
1244
1245 case PRID_IMP_NETLOGIC_XLP8XX:
1246 case PRID_IMP_NETLOGIC_XLP3XX:
1247 c->cputype = CPU_XLP;
1248 __cpu_name[cpu] = "Netlogic XLP";
1249 break;
1250
1251 case PRID_IMP_NETLOGIC_XLR732:
1252 case PRID_IMP_NETLOGIC_XLR716:
1253 case PRID_IMP_NETLOGIC_XLR532:
1254 case PRID_IMP_NETLOGIC_XLR308:
1255 case PRID_IMP_NETLOGIC_XLR532C:
1256 case PRID_IMP_NETLOGIC_XLR516C:
1257 case PRID_IMP_NETLOGIC_XLR508C:
1258 case PRID_IMP_NETLOGIC_XLR308C:
1259 c->cputype = CPU_XLR;
1260 __cpu_name[cpu] = "Netlogic XLR";
1261 break;
1262
1263 case PRID_IMP_NETLOGIC_XLS608:
1264 case PRID_IMP_NETLOGIC_XLS408:
1265 case PRID_IMP_NETLOGIC_XLS404:
1266 case PRID_IMP_NETLOGIC_XLS208:
1267 case PRID_IMP_NETLOGIC_XLS204:
1268 case PRID_IMP_NETLOGIC_XLS108:
1269 case PRID_IMP_NETLOGIC_XLS104:
1270 case PRID_IMP_NETLOGIC_XLS616B:
1271 case PRID_IMP_NETLOGIC_XLS608B:
1272 case PRID_IMP_NETLOGIC_XLS416B:
1273 case PRID_IMP_NETLOGIC_XLS412B:
1274 case PRID_IMP_NETLOGIC_XLS408B:
1275 case PRID_IMP_NETLOGIC_XLS404B:
1276 c->cputype = CPU_XLR;
1277 __cpu_name[cpu] = "Netlogic XLS";
1278 break;
1279
1280 default:
1281 pr_info("Unknown Netlogic chip id [%02x]!\n",
1282 c->processor_id);
1283 c->cputype = CPU_XLR;
1284 break;
1285 }
1286
1287 if (c->cputype == CPU_XLP) {
1288 set_isa(c, MIPS_CPU_ISA_M64R2);
1289 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1290 /* This will be updated again after all threads are woken up */
1291 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1292 } else {
1293 set_isa(c, MIPS_CPU_ISA_M64R1);
1294 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1295 }
1296 c->kscratch_mask = 0xf;
1297 }
1298
1299 #ifdef CONFIG_64BIT
1300 /* For use by uaccess.h */
1301 u64 __ua_limit;
1302 EXPORT_SYMBOL(__ua_limit);
1303 #endif
1304
1305 const char *__cpu_name[NR_CPUS];
1306 const char *__elf_platform;
1307
1308 void cpu_probe(void)
1309 {
1310 struct cpuinfo_mips *c = &current_cpu_data;
1311 unsigned int cpu = smp_processor_id();
1312
1313 c->processor_id = PRID_IMP_UNKNOWN;
1314 c->fpu_id = FPIR_IMP_NONE;
1315 c->cputype = CPU_UNKNOWN;
1316 c->writecombine = _CACHE_UNCACHED;
1317
1318 c->processor_id = read_c0_prid();
1319 switch (c->processor_id & PRID_COMP_MASK) {
1320 case PRID_COMP_LEGACY:
1321 cpu_probe_legacy(c, cpu);
1322 break;
1323 case PRID_COMP_MIPS:
1324 cpu_probe_mips(c, cpu);
1325 break;
1326 case PRID_COMP_ALCHEMY:
1327 cpu_probe_alchemy(c, cpu);
1328 break;
1329 case PRID_COMP_SIBYTE:
1330 cpu_probe_sibyte(c, cpu);
1331 break;
1332 case PRID_COMP_BROADCOM:
1333 cpu_probe_broadcom(c, cpu);
1334 break;
1335 case PRID_COMP_SANDCRAFT:
1336 cpu_probe_sandcraft(c, cpu);
1337 break;
1338 case PRID_COMP_NXP:
1339 cpu_probe_nxp(c, cpu);
1340 break;
1341 case PRID_COMP_CAVIUM:
1342 cpu_probe_cavium(c, cpu);
1343 break;
1344 case PRID_COMP_INGENIC:
1345 cpu_probe_ingenic(c, cpu);
1346 break;
1347 case PRID_COMP_NETLOGIC:
1348 cpu_probe_netlogic(c, cpu);
1349 break;
1350 }
1351
1352 BUG_ON(!__cpu_name[cpu]);
1353 BUG_ON(c->cputype == CPU_UNKNOWN);
1354
1355 /*
1356 * Platform code can force the cpu type to optimize code
1357 * generation. In that case be sure the cpu type is correctly
1358 * manually setup otherwise it could trigger some nasty bugs.
1359 */
1360 BUG_ON(current_cpu_type() != c->cputype);
1361
1362 if (mips_fpu_disabled)
1363 c->options &= ~MIPS_CPU_FPU;
1364
1365 if (mips_dsp_disabled)
1366 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1367
1368 if (mips_htw_disabled) {
1369 c->options &= ~MIPS_CPU_HTW;
1370 write_c0_pwctl(read_c0_pwctl() &
1371 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1372 }
1373
1374 if (c->options & MIPS_CPU_FPU) {
1375 c->fpu_id = cpu_get_fpu_id();
1376
1377 if (c->isa_level & cpu_has_mips_r) {
1378 if (c->fpu_id & MIPS_FPIR_3D)
1379 c->ases |= MIPS_ASE_MIPS3D;
1380 if (c->fpu_id & MIPS_FPIR_FREP)
1381 c->options |= MIPS_CPU_FRE;
1382 }
1383 }
1384
1385 if (cpu_has_mips_r2_r6) {
1386 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1387 /* R2 has Performance Counter Interrupt indicator */
1388 c->options |= MIPS_CPU_PCI;
1389 }
1390 else
1391 c->srsets = 1;
1392
1393 if (cpu_has_msa) {
1394 c->msa_id = cpu_get_msa_id();
1395 WARN(c->msa_id & MSA_IR_WRPF,
1396 "Vector register partitioning unimplemented!");
1397 }
1398
1399 cpu_probe_vmbits(c);
1400
1401 #ifdef CONFIG_64BIT
1402 if (cpu == 0)
1403 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1404 #endif
1405 }
1406
1407 void cpu_report(void)
1408 {
1409 struct cpuinfo_mips *c = &current_cpu_data;
1410
1411 pr_info("CPU%d revision is: %08x (%s)\n",
1412 smp_processor_id(), c->processor_id, cpu_name_string());
1413 if (c->options & MIPS_CPU_FPU)
1414 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1415 if (cpu_has_msa)
1416 pr_info("MSA revision is: %08x\n", c->msa_id);
1417 }
Linux kernel - Deliverables
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