2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
37 void (*cpu_wait
)(void);
38 EXPORT_SYMBOL(cpu_wait
);
40 static void r3081_wait(void)
42 unsigned long cfg
= read_c0_conf();
43 write_c0_conf(cfg
| R30XX_CONF_HALT
);
46 static void r39xx_wait(void)
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
54 extern void r4k_wait(void);
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void r4k_wait_irqoff(void)
67 __asm__(" .set push \n"
72 __asm__(" .globl __pastwait \n"
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
80 static void rm7k_wait_irqoff(void)
90 " mtc0 $1, $12 # stalls until W stage \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
102 static void au1k_wait(void)
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
115 : : "r" (au1k_wait
));
118 static int __initdata nowait
;
120 static int __init
wait_disable(char *s
)
127 __setup("nowait", wait_disable
);
129 static int __cpuinitdata mips_fpu_disabled
;
131 static int __init
fpu_disable(char *s
)
133 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
134 mips_fpu_disabled
= 1;
139 __setup("nofpu", fpu_disable
);
141 int __cpuinitdata mips_dsp_disabled
;
143 static int __init
dsp_disable(char *s
)
145 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
146 mips_dsp_disabled
= 1;
151 __setup("nodsp", dsp_disable
);
153 void __init
check_wait(void)
155 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
158 printk("Wait instruction disabled.\n");
162 switch (c
->cputype
) {
165 cpu_wait
= r3081_wait
;
168 cpu_wait
= r39xx_wait
;
171 /* case CPU_R4300: */
189 case CPU_CAVIUM_OCTEON
:
190 case CPU_CAVIUM_OCTEON_PLUS
:
191 case CPU_CAVIUM_OCTEON2
:
200 cpu_wait
= rm7k_wait_irqoff
;
208 if (read_c0_config7() & MIPS_CONF7_WII
)
209 cpu_wait
= r4k_wait_irqoff
;
214 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
215 cpu_wait
= r4k_wait_irqoff
;
219 cpu_wait
= r4k_wait_irqoff
;
222 cpu_wait
= au1k_wait
;
226 * WAIT on Rev1.0 has E1, E2, E3 and E16.
227 * WAIT on Rev2.0 and Rev3.0 has E16.
228 * Rev3.1 WAIT is nop, why bother
230 if ((c
->processor_id
& 0xff) <= 0x64)
234 * Another rev is incremeting c0_count at a reduced clock
235 * rate while in WAIT mode. So we basically have the choice
236 * between using the cp0 timer as clocksource or avoiding
237 * the WAIT instruction. Until more details are known,
238 * disable the use of WAIT for 20Kc entirely.
243 if ((c
->processor_id
& 0x00ff) >= 0x40)
251 static inline void check_errata(void)
253 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
255 switch (c
->cputype
) {
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/SMTC/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
262 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
270 void __init
check_bugs32(void)
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 static inline int cpu_has_confreg(void)
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1
, size2
;
285 unsigned long cfg
= read_c0_conf();
287 size1
= r3k_cache_size(ST0_ISC
);
288 write_c0_conf(cfg
^ R30XX_CONF_AC
);
289 size2
= r3k_cache_size(ST0_ISC
);
291 return size1
!= size2
;
297 static inline void set_elf_platform(int cpu
, const char *plat
)
300 __elf_platform
= plat
;
304 * Get the FPU Implementation/Revision.
306 static inline unsigned long cpu_get_fpu_id(void)
308 unsigned long tmp
, fpu_id
;
310 tmp
= read_c0_status();
312 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
313 write_c0_status(tmp
);
318 * Check the CPU has an FPU the official way.
320 static inline int __cpu_has_fpu(void)
322 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
325 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
327 #ifdef __NEED_VMBITS_PROBE
328 write_c0_entryhi(0x3fffffffffffe000ULL
);
329 back_to_back_c0_hazard();
330 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
334 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
337 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
339 unsigned int config0
;
342 config0
= read_c0_config();
344 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
345 c
->options
|= MIPS_CPU_TLB
;
346 isa
= (config0
& MIPS_CONF_AT
) >> 13;
349 switch ((config0
& MIPS_CONF_AR
) >> 10) {
351 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
354 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
361 switch ((config0
& MIPS_CONF_AR
) >> 10) {
363 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
366 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
376 return config0
& MIPS_CONF_M
;
379 panic(unknown_isa
, config0
);
382 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
384 unsigned int config1
;
386 config1
= read_c0_config1();
388 if (config1
& MIPS_CONF1_MD
)
389 c
->ases
|= MIPS_ASE_MDMX
;
390 if (config1
& MIPS_CONF1_WR
)
391 c
->options
|= MIPS_CPU_WATCH
;
392 if (config1
& MIPS_CONF1_CA
)
393 c
->ases
|= MIPS_ASE_MIPS16
;
394 if (config1
& MIPS_CONF1_EP
)
395 c
->options
|= MIPS_CPU_EJTAG
;
396 if (config1
& MIPS_CONF1_FP
) {
397 c
->options
|= MIPS_CPU_FPU
;
398 c
->options
|= MIPS_CPU_32FPR
;
401 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
403 return config1
& MIPS_CONF_M
;
406 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
408 unsigned int config2
;
410 config2
= read_c0_config2();
412 if (config2
& MIPS_CONF2_SL
)
413 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
415 return config2
& MIPS_CONF_M
;
418 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
420 unsigned int config3
;
422 config3
= read_c0_config3();
424 if (config3
& MIPS_CONF3_SM
) {
425 c
->ases
|= MIPS_ASE_SMARTMIPS
;
426 c
->options
|= MIPS_CPU_RIXI
;
428 if (config3
& MIPS_CONF3_RXI
)
429 c
->options
|= MIPS_CPU_RIXI
;
430 if (config3
& MIPS_CONF3_DSP
)
431 c
->ases
|= MIPS_ASE_DSP
;
432 if (config3
& MIPS_CONF3_DSP2P
)
433 c
->ases
|= MIPS_ASE_DSP2P
;
434 if (config3
& MIPS_CONF3_VINT
)
435 c
->options
|= MIPS_CPU_VINT
;
436 if (config3
& MIPS_CONF3_VEIC
)
437 c
->options
|= MIPS_CPU_VEIC
;
438 if (config3
& MIPS_CONF3_MT
)
439 c
->ases
|= MIPS_ASE_MIPSMT
;
440 if (config3
& MIPS_CONF3_ULRI
)
441 c
->options
|= MIPS_CPU_ULRI
;
443 return config3
& MIPS_CONF_M
;
446 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
448 unsigned int config4
;
450 config4
= read_c0_config4();
452 if ((config4
& MIPS_CONF4_MMUEXTDEF
) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
454 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
456 c
->kscratch_mask
= (config4
>> 16) & 0xff;
458 return config4
& MIPS_CONF_M
;
461 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
465 /* MIPS32 or MIPS64 compliant CPU. */
466 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
467 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
469 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
471 ok
= decode_config0(c
); /* Read Config registers. */
472 BUG_ON(!ok
); /* Arch spec violation! */
474 ok
= decode_config1(c
);
476 ok
= decode_config2(c
);
478 ok
= decode_config3(c
);
480 ok
= decode_config4(c
);
482 mips_probe_watch_registers(c
);
485 c
->core
= read_c0_ebase() & 0x3ff;
488 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
491 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
493 switch (c
->processor_id
& 0xff00) {
495 c
->cputype
= CPU_R2000
;
496 __cpu_name
[cpu
] = "R2000";
497 c
->isa_level
= MIPS_CPU_ISA_I
;
498 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
501 c
->options
|= MIPS_CPU_FPU
;
505 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
506 if (cpu_has_confreg()) {
507 c
->cputype
= CPU_R3081E
;
508 __cpu_name
[cpu
] = "R3081";
510 c
->cputype
= CPU_R3000A
;
511 __cpu_name
[cpu
] = "R3000A";
515 c
->cputype
= CPU_R3000
;
516 __cpu_name
[cpu
] = "R3000";
518 c
->isa_level
= MIPS_CPU_ISA_I
;
519 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
522 c
->options
|= MIPS_CPU_FPU
;
526 if (read_c0_config() & CONF_SC
) {
527 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
528 c
->cputype
= CPU_R4400PC
;
529 __cpu_name
[cpu
] = "R4400PC";
531 c
->cputype
= CPU_R4000PC
;
532 __cpu_name
[cpu
] = "R4000PC";
535 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
536 c
->cputype
= CPU_R4400SC
;
537 __cpu_name
[cpu
] = "R4400SC";
539 c
->cputype
= CPU_R4000SC
;
540 __cpu_name
[cpu
] = "R4000SC";
544 c
->isa_level
= MIPS_CPU_ISA_III
;
545 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
546 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
550 case PRID_IMP_VR41XX
:
551 switch (c
->processor_id
& 0xf0) {
552 case PRID_REV_VR4111
:
553 c
->cputype
= CPU_VR4111
;
554 __cpu_name
[cpu
] = "NEC VR4111";
556 case PRID_REV_VR4121
:
557 c
->cputype
= CPU_VR4121
;
558 __cpu_name
[cpu
] = "NEC VR4121";
560 case PRID_REV_VR4122
:
561 if ((c
->processor_id
& 0xf) < 0x3) {
562 c
->cputype
= CPU_VR4122
;
563 __cpu_name
[cpu
] = "NEC VR4122";
565 c
->cputype
= CPU_VR4181A
;
566 __cpu_name
[cpu
] = "NEC VR4181A";
569 case PRID_REV_VR4130
:
570 if ((c
->processor_id
& 0xf) < 0x4) {
571 c
->cputype
= CPU_VR4131
;
572 __cpu_name
[cpu
] = "NEC VR4131";
574 c
->cputype
= CPU_VR4133
;
575 __cpu_name
[cpu
] = "NEC VR4133";
579 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
580 c
->cputype
= CPU_VR41XX
;
581 __cpu_name
[cpu
] = "NEC Vr41xx";
584 c
->isa_level
= MIPS_CPU_ISA_III
;
585 c
->options
= R4K_OPTS
;
589 c
->cputype
= CPU_R4300
;
590 __cpu_name
[cpu
] = "R4300";
591 c
->isa_level
= MIPS_CPU_ISA_III
;
592 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
597 c
->cputype
= CPU_R4600
;
598 __cpu_name
[cpu
] = "R4600";
599 c
->isa_level
= MIPS_CPU_ISA_III
;
600 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
607 * This processor doesn't have an MMU, so it's not
608 * "real easy" to run Linux on it. It is left purely
609 * for documentation. Commented out because it shares
610 * it's c0_prid id number with the TX3900.
612 c
->cputype
= CPU_R4650
;
613 __cpu_name
[cpu
] = "R4650";
614 c
->isa_level
= MIPS_CPU_ISA_III
;
615 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
620 c
->isa_level
= MIPS_CPU_ISA_I
;
621 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
623 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
624 c
->cputype
= CPU_TX3927
;
625 __cpu_name
[cpu
] = "TX3927";
628 switch (c
->processor_id
& 0xff) {
629 case PRID_REV_TX3912
:
630 c
->cputype
= CPU_TX3912
;
631 __cpu_name
[cpu
] = "TX3912";
634 case PRID_REV_TX3922
:
635 c
->cputype
= CPU_TX3922
;
636 __cpu_name
[cpu
] = "TX3922";
643 c
->cputype
= CPU_R4700
;
644 __cpu_name
[cpu
] = "R4700";
645 c
->isa_level
= MIPS_CPU_ISA_III
;
646 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
651 c
->cputype
= CPU_TX49XX
;
652 __cpu_name
[cpu
] = "R49XX";
653 c
->isa_level
= MIPS_CPU_ISA_III
;
654 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
655 if (!(c
->processor_id
& 0x08))
656 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
660 c
->cputype
= CPU_R5000
;
661 __cpu_name
[cpu
] = "R5000";
662 c
->isa_level
= MIPS_CPU_ISA_IV
;
663 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
668 c
->cputype
= CPU_R5432
;
669 __cpu_name
[cpu
] = "R5432";
670 c
->isa_level
= MIPS_CPU_ISA_IV
;
671 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
672 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
676 c
->cputype
= CPU_R5500
;
677 __cpu_name
[cpu
] = "R5500";
678 c
->isa_level
= MIPS_CPU_ISA_IV
;
679 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
680 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
683 case PRID_IMP_NEVADA
:
684 c
->cputype
= CPU_NEVADA
;
685 __cpu_name
[cpu
] = "Nevada";
686 c
->isa_level
= MIPS_CPU_ISA_IV
;
687 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
688 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
692 c
->cputype
= CPU_R6000
;
693 __cpu_name
[cpu
] = "R6000";
694 c
->isa_level
= MIPS_CPU_ISA_II
;
695 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
699 case PRID_IMP_R6000A
:
700 c
->cputype
= CPU_R6000A
;
701 __cpu_name
[cpu
] = "R6000A";
702 c
->isa_level
= MIPS_CPU_ISA_II
;
703 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
707 case PRID_IMP_RM7000
:
708 c
->cputype
= CPU_RM7000
;
709 __cpu_name
[cpu
] = "RM7000";
710 c
->isa_level
= MIPS_CPU_ISA_IV
;
711 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
714 * Undocumented RM7000: Bit 29 in the info register of
715 * the RM7000 v2.0 indicates if the TLB has 48 or 64
718 * 29 1 => 64 entry JTLB
721 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
723 case PRID_IMP_RM9000
:
724 c
->cputype
= CPU_RM9000
;
725 __cpu_name
[cpu
] = "RM9000";
726 c
->isa_level
= MIPS_CPU_ISA_IV
;
727 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
730 * Bit 29 in the info register of the RM9000
731 * indicates if the TLB has 48 or 64 entries.
733 * 29 1 => 64 entry JTLB
736 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
739 c
->cputype
= CPU_R8000
;
740 __cpu_name
[cpu
] = "RM8000";
741 c
->isa_level
= MIPS_CPU_ISA_IV
;
742 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
743 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
745 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
747 case PRID_IMP_R10000
:
748 c
->cputype
= CPU_R10000
;
749 __cpu_name
[cpu
] = "R10000";
750 c
->isa_level
= MIPS_CPU_ISA_IV
;
751 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
752 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
753 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
757 case PRID_IMP_R12000
:
758 c
->cputype
= CPU_R12000
;
759 __cpu_name
[cpu
] = "R12000";
760 c
->isa_level
= MIPS_CPU_ISA_IV
;
761 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
762 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
763 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
767 case PRID_IMP_R14000
:
768 c
->cputype
= CPU_R14000
;
769 __cpu_name
[cpu
] = "R14000";
770 c
->isa_level
= MIPS_CPU_ISA_IV
;
771 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
772 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
773 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
777 case PRID_IMP_LOONGSON2
:
778 c
->cputype
= CPU_LOONGSON2
;
779 __cpu_name
[cpu
] = "ICT Loongson-2";
781 switch (c
->processor_id
& PRID_REV_MASK
) {
782 case PRID_REV_LOONGSON2E
:
783 set_elf_platform(cpu
, "loongson2e");
785 case PRID_REV_LOONGSON2F
:
786 set_elf_platform(cpu
, "loongson2f");
790 c
->isa_level
= MIPS_CPU_ISA_III
;
791 c
->options
= R4K_OPTS
|
792 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
796 case PRID_IMP_LOONGSON1
:
799 c
->cputype
= CPU_LOONGSON1
;
801 switch (c
->processor_id
& PRID_REV_MASK
) {
802 case PRID_REV_LOONGSON1B
:
803 __cpu_name
[cpu
] = "Loongson 1B";
811 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
814 switch (c
->processor_id
& 0xff00) {
816 c
->cputype
= CPU_4KC
;
817 __cpu_name
[cpu
] = "MIPS 4Kc";
820 case PRID_IMP_4KECR2
:
821 c
->cputype
= CPU_4KEC
;
822 __cpu_name
[cpu
] = "MIPS 4KEc";
826 c
->cputype
= CPU_4KSC
;
827 __cpu_name
[cpu
] = "MIPS 4KSc";
830 c
->cputype
= CPU_5KC
;
831 __cpu_name
[cpu
] = "MIPS 5Kc";
834 c
->cputype
= CPU_5KE
;
835 __cpu_name
[cpu
] = "MIPS 5KE";
838 c
->cputype
= CPU_20KC
;
839 __cpu_name
[cpu
] = "MIPS 20Kc";
843 c
->cputype
= CPU_24K
;
844 __cpu_name
[cpu
] = "MIPS 24Kc";
847 c
->cputype
= CPU_25KF
;
848 __cpu_name
[cpu
] = "MIPS 25Kc";
851 c
->cputype
= CPU_34K
;
852 __cpu_name
[cpu
] = "MIPS 34Kc";
855 c
->cputype
= CPU_74K
;
856 __cpu_name
[cpu
] = "MIPS 74Kc";
859 c
->cputype
= CPU_M14KC
;
860 __cpu_name
[cpu
] = "MIPS M14Kc";
863 c
->cputype
= CPU_1004K
;
864 __cpu_name
[cpu
] = "MIPS 1004Kc";
867 c
->cputype
= CPU_74K
;
868 __cpu_name
[cpu
] = "MIPS 1074Kc";
875 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
878 switch (c
->processor_id
& 0xff00) {
879 case PRID_IMP_AU1_REV1
:
880 case PRID_IMP_AU1_REV2
:
881 c
->cputype
= CPU_ALCHEMY
;
882 switch ((c
->processor_id
>> 24) & 0xff) {
884 __cpu_name
[cpu
] = "Au1000";
887 __cpu_name
[cpu
] = "Au1500";
890 __cpu_name
[cpu
] = "Au1100";
893 __cpu_name
[cpu
] = "Au1550";
896 __cpu_name
[cpu
] = "Au1200";
897 if ((c
->processor_id
& 0xff) == 2)
898 __cpu_name
[cpu
] = "Au1250";
901 __cpu_name
[cpu
] = "Au1210";
904 __cpu_name
[cpu
] = "Au1xxx";
911 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
915 switch (c
->processor_id
& 0xff00) {
917 c
->cputype
= CPU_SB1
;
918 __cpu_name
[cpu
] = "SiByte SB1";
919 /* FPU in pass1 is known to have issues. */
920 if ((c
->processor_id
& 0xff) < 0x02)
921 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
924 c
->cputype
= CPU_SB1A
;
925 __cpu_name
[cpu
] = "SiByte SB1A";
930 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
933 switch (c
->processor_id
& 0xff00) {
934 case PRID_IMP_SR71000
:
935 c
->cputype
= CPU_SR71000
;
936 __cpu_name
[cpu
] = "Sandcraft SR71000";
943 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
946 switch (c
->processor_id
& 0xff00) {
947 case PRID_IMP_PR4450
:
948 c
->cputype
= CPU_PR4450
;
949 __cpu_name
[cpu
] = "Philips PR4450";
950 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
955 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
958 switch (c
->processor_id
& 0xff00) {
959 case PRID_IMP_BMIPS32_REV4
:
960 case PRID_IMP_BMIPS32_REV8
:
961 c
->cputype
= CPU_BMIPS32
;
962 __cpu_name
[cpu
] = "Broadcom BMIPS32";
963 set_elf_platform(cpu
, "bmips32");
965 case PRID_IMP_BMIPS3300
:
966 case PRID_IMP_BMIPS3300_ALT
:
967 case PRID_IMP_BMIPS3300_BUG
:
968 c
->cputype
= CPU_BMIPS3300
;
969 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
970 set_elf_platform(cpu
, "bmips3300");
972 case PRID_IMP_BMIPS43XX
: {
973 int rev
= c
->processor_id
& 0xff;
975 if (rev
>= PRID_REV_BMIPS4380_LO
&&
976 rev
<= PRID_REV_BMIPS4380_HI
) {
977 c
->cputype
= CPU_BMIPS4380
;
978 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
979 set_elf_platform(cpu
, "bmips4380");
981 c
->cputype
= CPU_BMIPS4350
;
982 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
983 set_elf_platform(cpu
, "bmips4350");
987 case PRID_IMP_BMIPS5000
:
988 c
->cputype
= CPU_BMIPS5000
;
989 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
990 set_elf_platform(cpu
, "bmips5000");
991 c
->options
|= MIPS_CPU_ULRI
;
996 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
999 switch (c
->processor_id
& 0xff00) {
1000 case PRID_IMP_CAVIUM_CN38XX
:
1001 case PRID_IMP_CAVIUM_CN31XX
:
1002 case PRID_IMP_CAVIUM_CN30XX
:
1003 c
->cputype
= CPU_CAVIUM_OCTEON
;
1004 __cpu_name
[cpu
] = "Cavium Octeon";
1006 case PRID_IMP_CAVIUM_CN58XX
:
1007 case PRID_IMP_CAVIUM_CN56XX
:
1008 case PRID_IMP_CAVIUM_CN50XX
:
1009 case PRID_IMP_CAVIUM_CN52XX
:
1010 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1011 __cpu_name
[cpu
] = "Cavium Octeon+";
1013 set_elf_platform(cpu
, "octeon");
1015 case PRID_IMP_CAVIUM_CN61XX
:
1016 case PRID_IMP_CAVIUM_CN63XX
:
1017 case PRID_IMP_CAVIUM_CN66XX
:
1018 case PRID_IMP_CAVIUM_CN68XX
:
1019 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1020 __cpu_name
[cpu
] = "Cavium Octeon II";
1021 set_elf_platform(cpu
, "octeon2");
1024 printk(KERN_INFO
"Unknown Octeon chip!\n");
1025 c
->cputype
= CPU_UNKNOWN
;
1030 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1033 /* JZRISC does not implement the CP0 counter. */
1034 c
->options
&= ~MIPS_CPU_COUNTER
;
1035 switch (c
->processor_id
& 0xff00) {
1036 case PRID_IMP_JZRISC
:
1037 c
->cputype
= CPU_JZRISC
;
1038 __cpu_name
[cpu
] = "Ingenic JZRISC";
1041 panic("Unknown Ingenic Processor ID!");
1046 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1050 if ((c
->processor_id
& 0xff00) == PRID_IMP_NETLOGIC_AU13XX
) {
1051 c
->cputype
= CPU_ALCHEMY
;
1052 __cpu_name
[cpu
] = "Au1300";
1053 /* following stuff is not for Alchemy */
1057 c
->options
= (MIPS_CPU_TLB
|
1065 switch (c
->processor_id
& 0xff00) {
1066 case PRID_IMP_NETLOGIC_XLP8XX
:
1067 case PRID_IMP_NETLOGIC_XLP3XX
:
1068 c
->cputype
= CPU_XLP
;
1069 __cpu_name
[cpu
] = "Netlogic XLP";
1072 case PRID_IMP_NETLOGIC_XLR732
:
1073 case PRID_IMP_NETLOGIC_XLR716
:
1074 case PRID_IMP_NETLOGIC_XLR532
:
1075 case PRID_IMP_NETLOGIC_XLR308
:
1076 case PRID_IMP_NETLOGIC_XLR532C
:
1077 case PRID_IMP_NETLOGIC_XLR516C
:
1078 case PRID_IMP_NETLOGIC_XLR508C
:
1079 case PRID_IMP_NETLOGIC_XLR308C
:
1080 c
->cputype
= CPU_XLR
;
1081 __cpu_name
[cpu
] = "Netlogic XLR";
1084 case PRID_IMP_NETLOGIC_XLS608
:
1085 case PRID_IMP_NETLOGIC_XLS408
:
1086 case PRID_IMP_NETLOGIC_XLS404
:
1087 case PRID_IMP_NETLOGIC_XLS208
:
1088 case PRID_IMP_NETLOGIC_XLS204
:
1089 case PRID_IMP_NETLOGIC_XLS108
:
1090 case PRID_IMP_NETLOGIC_XLS104
:
1091 case PRID_IMP_NETLOGIC_XLS616B
:
1092 case PRID_IMP_NETLOGIC_XLS608B
:
1093 case PRID_IMP_NETLOGIC_XLS416B
:
1094 case PRID_IMP_NETLOGIC_XLS412B
:
1095 case PRID_IMP_NETLOGIC_XLS408B
:
1096 case PRID_IMP_NETLOGIC_XLS404B
:
1097 c
->cputype
= CPU_XLR
;
1098 __cpu_name
[cpu
] = "Netlogic XLS";
1102 pr_info("Unknown Netlogic chip id [%02x]!\n",
1104 c
->cputype
= CPU_XLR
;
1108 if (c
->cputype
== CPU_XLP
) {
1109 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
1110 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1111 /* This will be updated again after all threads are woken up */
1112 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1114 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
1115 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1120 /* For use by uaccess.h */
1122 EXPORT_SYMBOL(__ua_limit
);
1125 const char *__cpu_name
[NR_CPUS
];
1126 const char *__elf_platform
;
1128 __cpuinit
void cpu_probe(void)
1130 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1131 unsigned int cpu
= smp_processor_id();
1133 c
->processor_id
= PRID_IMP_UNKNOWN
;
1134 c
->fpu_id
= FPIR_IMP_NONE
;
1135 c
->cputype
= CPU_UNKNOWN
;
1137 c
->processor_id
= read_c0_prid();
1138 switch (c
->processor_id
& 0xff0000) {
1139 case PRID_COMP_LEGACY
:
1140 cpu_probe_legacy(c
, cpu
);
1142 case PRID_COMP_MIPS
:
1143 cpu_probe_mips(c
, cpu
);
1145 case PRID_COMP_ALCHEMY
:
1146 cpu_probe_alchemy(c
, cpu
);
1148 case PRID_COMP_SIBYTE
:
1149 cpu_probe_sibyte(c
, cpu
);
1151 case PRID_COMP_BROADCOM
:
1152 cpu_probe_broadcom(c
, cpu
);
1154 case PRID_COMP_SANDCRAFT
:
1155 cpu_probe_sandcraft(c
, cpu
);
1158 cpu_probe_nxp(c
, cpu
);
1160 case PRID_COMP_CAVIUM
:
1161 cpu_probe_cavium(c
, cpu
);
1163 case PRID_COMP_INGENIC
:
1164 cpu_probe_ingenic(c
, cpu
);
1166 case PRID_COMP_NETLOGIC
:
1167 cpu_probe_netlogic(c
, cpu
);
1171 BUG_ON(!__cpu_name
[cpu
]);
1172 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1175 * Platform code can force the cpu type to optimize code
1176 * generation. In that case be sure the cpu type is correctly
1177 * manually setup otherwise it could trigger some nasty bugs.
1179 BUG_ON(current_cpu_type() != c
->cputype
);
1181 if (mips_fpu_disabled
)
1182 c
->options
&= ~MIPS_CPU_FPU
;
1184 if (mips_dsp_disabled
)
1185 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1187 if (c
->options
& MIPS_CPU_FPU
) {
1188 c
->fpu_id
= cpu_get_fpu_id();
1190 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1191 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1192 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1193 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1194 if (c
->fpu_id
& MIPS_FPIR_3D
)
1195 c
->ases
|= MIPS_ASE_MIPS3D
;
1199 if (cpu_has_mips_r2
) {
1200 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1201 /* R2 has Performance Counter Interrupt indicator */
1202 c
->options
|= MIPS_CPU_PCI
;
1207 cpu_probe_vmbits(c
);
1211 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1215 __cpuinit
void cpu_report(void)
1217 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1219 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
1220 c
->processor_id
, cpu_name_string());
1221 if (c
->options
& MIPS_CPU_FPU
)
1222 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);