2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait
)(void) = NULL
;
34 static void r3081_wait(void)
36 unsigned long cfg
= read_c0_conf();
37 write_c0_conf(cfg
| R30XX_CONF_HALT
);
40 static void r39xx_wait(void)
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
49 * There is a race when WAIT instruction executed with interrupt
51 * But it is implementation-dependent wheter the pipelie restarts when
52 * a non-enabled interrupt is requested.
54 static void r4k_wait(void)
56 __asm__(" .set mips3 \n"
62 * This variant is preferable as it allows testing need_resched and going to
63 * sleep depending on the outcome atomically. Unfortunately the "It is
64 * implementation-dependent whether the pipeline restarts when a non-enabled
65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66 * using this version a gamble.
68 static void r4k_wait_irqoff(void)
72 __asm__(" .set mips3 \n"
79 * The RM7000 variant has to handle erratum 38. The workaround is to not
80 * have any pending stores when the WAIT instruction is executed.
82 static void rm7k_wait_irqoff(void)
92 " mtc0 $1, $12 # stalls until W stage \n"
94 " mtc0 $1, $12 # stalls until W stage \n"
99 /* The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter. */
103 static void au1k_wait(void)
105 /* using the wait instruction makes CP0 counter unusable */
106 __asm__(" .set mips3 \n"
107 " cache 0x14, 0(%0) \n"
108 " cache 0x14, 32(%0) \n"
117 : : "r" (au1k_wait
));
120 static int __initdata nowait
= 0;
122 static int __init
wait_disable(char *s
)
129 __setup("nowait", wait_disable
);
131 static inline void check_wait(void)
133 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
136 printk("Wait instruction disabled.\n");
140 switch (c
->cputype
) {
143 cpu_wait
= r3081_wait
;
146 cpu_wait
= r39xx_wait
;
149 /* case CPU_R4300: */
166 cpu_wait
= rm7k_wait_irqoff
;
172 if (read_c0_config7() & MIPS_CONF7_WII
)
173 cpu_wait
= r4k_wait_irqoff
;
178 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
179 cpu_wait
= r4k_wait_irqoff
;
183 cpu_wait
= r4k_wait_irqoff
;
191 cpu_wait
= au1k_wait
;
195 * WAIT on Rev1.0 has E1, E2, E3 and E16.
196 * WAIT on Rev2.0 and Rev3.0 has E16.
197 * Rev3.1 WAIT is nop, why bother
199 if ((c
->processor_id
& 0xff) <= 0x64)
203 * Another rev is incremeting c0_count at a reduced clock
204 * rate while in WAIT mode. So we basically have the choice
205 * between using the cp0 timer as clocksource or avoiding
206 * the WAIT instruction. Until more details are known,
207 * disable the use of WAIT for 20Kc entirely.
212 if ((c
->processor_id
& 0x00ff) >= 0x40)
220 static inline void check_errata(void)
222 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
224 switch (c
->cputype
) {
227 * Erratum "RPS May Cause Incorrect Instruction Execution"
228 * This code only handles VPE0, any SMP/SMTC/RTOS code
229 * making use of VPE1 will be responsable for that VPE.
231 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
232 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
239 void __init
check_bugs32(void)
246 * Probe whether cpu has config register by trying to play with
247 * alternate cache bit and see whether it matters.
248 * It's used by cpu_probe to distinguish between R3000A and R3081.
250 static inline int cpu_has_confreg(void)
252 #ifdef CONFIG_CPU_R3000
253 extern unsigned long r3k_cache_size(unsigned long);
254 unsigned long size1
, size2
;
255 unsigned long cfg
= read_c0_conf();
257 size1
= r3k_cache_size(ST0_ISC
);
258 write_c0_conf(cfg
^ R30XX_CONF_AC
);
259 size2
= r3k_cache_size(ST0_ISC
);
261 return size1
!= size2
;
268 * Get the FPU Implementation/Revision.
270 static inline unsigned long cpu_get_fpu_id(void)
272 unsigned long tmp
, fpu_id
;
274 tmp
= read_c0_status();
276 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
277 write_c0_status(tmp
);
282 * Check the CPU has an FPU the official way.
284 static inline int __cpu_has_fpu(void)
286 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
289 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
292 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
)
294 switch (c
->processor_id
& 0xff00) {
296 c
->cputype
= CPU_R2000
;
297 c
->isa_level
= MIPS_CPU_ISA_I
;
298 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
301 c
->options
|= MIPS_CPU_FPU
;
305 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
)
306 if (cpu_has_confreg())
307 c
->cputype
= CPU_R3081E
;
309 c
->cputype
= CPU_R3000A
;
311 c
->cputype
= CPU_R3000
;
312 c
->isa_level
= MIPS_CPU_ISA_I
;
313 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
316 c
->options
|= MIPS_CPU_FPU
;
320 if (read_c0_config() & CONF_SC
) {
321 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
322 c
->cputype
= CPU_R4400PC
;
324 c
->cputype
= CPU_R4000PC
;
326 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
327 c
->cputype
= CPU_R4400SC
;
329 c
->cputype
= CPU_R4000SC
;
332 c
->isa_level
= MIPS_CPU_ISA_III
;
333 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
334 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
338 case PRID_IMP_VR41XX
:
339 switch (c
->processor_id
& 0xf0) {
340 case PRID_REV_VR4111
:
341 c
->cputype
= CPU_VR4111
;
343 case PRID_REV_VR4121
:
344 c
->cputype
= CPU_VR4121
;
346 case PRID_REV_VR4122
:
347 if ((c
->processor_id
& 0xf) < 0x3)
348 c
->cputype
= CPU_VR4122
;
350 c
->cputype
= CPU_VR4181A
;
352 case PRID_REV_VR4130
:
353 if ((c
->processor_id
& 0xf) < 0x4)
354 c
->cputype
= CPU_VR4131
;
356 c
->cputype
= CPU_VR4133
;
359 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
360 c
->cputype
= CPU_VR41XX
;
363 c
->isa_level
= MIPS_CPU_ISA_III
;
364 c
->options
= R4K_OPTS
;
368 c
->cputype
= CPU_R4300
;
369 c
->isa_level
= MIPS_CPU_ISA_III
;
370 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
375 c
->cputype
= CPU_R4600
;
376 c
->isa_level
= MIPS_CPU_ISA_III
;
377 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
384 * This processor doesn't have an MMU, so it's not
385 * "real easy" to run Linux on it. It is left purely
386 * for documentation. Commented out because it shares
387 * it's c0_prid id number with the TX3900.
389 c
->cputype
= CPU_R4650
;
390 c
->isa_level
= MIPS_CPU_ISA_III
;
391 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
396 c
->isa_level
= MIPS_CPU_ISA_I
;
397 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
399 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
400 c
->cputype
= CPU_TX3927
;
403 switch (c
->processor_id
& 0xff) {
404 case PRID_REV_TX3912
:
405 c
->cputype
= CPU_TX3912
;
408 case PRID_REV_TX3922
:
409 c
->cputype
= CPU_TX3922
;
413 c
->cputype
= CPU_UNKNOWN
;
419 c
->cputype
= CPU_R4700
;
420 c
->isa_level
= MIPS_CPU_ISA_III
;
421 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
426 c
->cputype
= CPU_TX49XX
;
427 c
->isa_level
= MIPS_CPU_ISA_III
;
428 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
429 if (!(c
->processor_id
& 0x08))
430 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
434 c
->cputype
= CPU_R5000
;
435 c
->isa_level
= MIPS_CPU_ISA_IV
;
436 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
441 c
->cputype
= CPU_R5432
;
442 c
->isa_level
= MIPS_CPU_ISA_IV
;
443 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
444 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
448 c
->cputype
= CPU_R5500
;
449 c
->isa_level
= MIPS_CPU_ISA_IV
;
450 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
451 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
454 case PRID_IMP_NEVADA
:
455 c
->cputype
= CPU_NEVADA
;
456 c
->isa_level
= MIPS_CPU_ISA_IV
;
457 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
458 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
462 c
->cputype
= CPU_R6000
;
463 c
->isa_level
= MIPS_CPU_ISA_II
;
464 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
468 case PRID_IMP_R6000A
:
469 c
->cputype
= CPU_R6000A
;
470 c
->isa_level
= MIPS_CPU_ISA_II
;
471 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
475 case PRID_IMP_RM7000
:
476 c
->cputype
= CPU_RM7000
;
477 c
->isa_level
= MIPS_CPU_ISA_IV
;
478 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
481 * Undocumented RM7000: Bit 29 in the info register of
482 * the RM7000 v2.0 indicates if the TLB has 48 or 64
485 * 29 1 => 64 entry JTLB
488 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
490 case PRID_IMP_RM9000
:
491 c
->cputype
= CPU_RM9000
;
492 c
->isa_level
= MIPS_CPU_ISA_IV
;
493 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
496 * Bit 29 in the info register of the RM9000
497 * indicates if the TLB has 48 or 64 entries.
499 * 29 1 => 64 entry JTLB
502 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
505 c
->cputype
= CPU_R8000
;
506 c
->isa_level
= MIPS_CPU_ISA_IV
;
507 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
508 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
510 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
512 case PRID_IMP_R10000
:
513 c
->cputype
= CPU_R10000
;
514 c
->isa_level
= MIPS_CPU_ISA_IV
;
515 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
516 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
517 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
521 case PRID_IMP_R12000
:
522 c
->cputype
= CPU_R12000
;
523 c
->isa_level
= MIPS_CPU_ISA_IV
;
524 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
525 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
526 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
530 case PRID_IMP_R14000
:
531 c
->cputype
= CPU_R14000
;
532 c
->isa_level
= MIPS_CPU_ISA_IV
;
533 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
534 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
535 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
539 case PRID_IMP_LOONGSON2
:
540 c
->cputype
= CPU_LOONGSON2
;
541 c
->isa_level
= MIPS_CPU_ISA_III
;
542 c
->options
= R4K_OPTS
|
543 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
550 static char unknown_isa
[] __initdata
= KERN_ERR \
551 "Unsupported ISA type, c0.config0: %d.";
553 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
555 unsigned int config0
;
558 config0
= read_c0_config();
560 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
561 c
->options
|= MIPS_CPU_TLB
;
562 isa
= (config0
& MIPS_CONF_AT
) >> 13;
565 switch ((config0
& MIPS_CONF_AR
) >> 10) {
567 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
570 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
577 switch ((config0
& MIPS_CONF_AR
) >> 10) {
579 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
582 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
592 return config0
& MIPS_CONF_M
;
595 panic(unknown_isa
, config0
);
598 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
600 unsigned int config1
;
602 config1
= read_c0_config1();
604 if (config1
& MIPS_CONF1_MD
)
605 c
->ases
|= MIPS_ASE_MDMX
;
606 if (config1
& MIPS_CONF1_WR
)
607 c
->options
|= MIPS_CPU_WATCH
;
608 if (config1
& MIPS_CONF1_CA
)
609 c
->ases
|= MIPS_ASE_MIPS16
;
610 if (config1
& MIPS_CONF1_EP
)
611 c
->options
|= MIPS_CPU_EJTAG
;
612 if (config1
& MIPS_CONF1_FP
) {
613 c
->options
|= MIPS_CPU_FPU
;
614 c
->options
|= MIPS_CPU_32FPR
;
617 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
619 return config1
& MIPS_CONF_M
;
622 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
624 unsigned int config2
;
626 config2
= read_c0_config2();
628 if (config2
& MIPS_CONF2_SL
)
629 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
631 return config2
& MIPS_CONF_M
;
634 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
636 unsigned int config3
;
638 config3
= read_c0_config3();
640 if (config3
& MIPS_CONF3_SM
)
641 c
->ases
|= MIPS_ASE_SMARTMIPS
;
642 if (config3
& MIPS_CONF3_DSP
)
643 c
->ases
|= MIPS_ASE_DSP
;
644 if (config3
& MIPS_CONF3_VINT
)
645 c
->options
|= MIPS_CPU_VINT
;
646 if (config3
& MIPS_CONF3_VEIC
)
647 c
->options
|= MIPS_CPU_VEIC
;
648 if (config3
& MIPS_CONF3_MT
)
649 c
->ases
|= MIPS_ASE_MIPSMT
;
650 if (config3
& MIPS_CONF3_ULRI
)
651 c
->options
|= MIPS_CPU_ULRI
;
653 return config3
& MIPS_CONF_M
;
656 static void __init
decode_configs(struct cpuinfo_mips
*c
)
658 /* MIPS32 or MIPS64 compliant CPU. */
659 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
660 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
662 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
664 /* Read Config registers. */
665 if (!decode_config0(c
))
666 return; /* actually worth a panic() */
667 if (!decode_config1(c
))
669 if (!decode_config2(c
))
671 if (!decode_config3(c
))
675 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
)
678 switch (c
->processor_id
& 0xff00) {
680 c
->cputype
= CPU_4KC
;
683 c
->cputype
= CPU_4KEC
;
685 case PRID_IMP_4KECR2
:
686 c
->cputype
= CPU_4KEC
;
690 c
->cputype
= CPU_4KSC
;
693 c
->cputype
= CPU_5KC
;
696 c
->cputype
= CPU_20KC
;
700 c
->cputype
= CPU_24K
;
703 c
->cputype
= CPU_25KF
;
706 c
->cputype
= CPU_34K
;
709 c
->cputype
= CPU_74K
;
714 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
)
717 switch (c
->processor_id
& 0xff00) {
718 case PRID_IMP_AU1_REV1
:
719 case PRID_IMP_AU1_REV2
:
720 switch ((c
->processor_id
>> 24) & 0xff) {
722 c
->cputype
= CPU_AU1000
;
725 c
->cputype
= CPU_AU1500
;
728 c
->cputype
= CPU_AU1100
;
731 c
->cputype
= CPU_AU1550
;
734 c
->cputype
= CPU_AU1200
;
737 panic("Unknown Au Core!");
744 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
)
749 * For historical reasons the SB1 comes with it's own variant of
750 * cache code which eventually will be folded into c-r4k.c. Until
751 * then we pretend it's got it's own cache architecture.
753 c
->options
&= ~MIPS_CPU_4K_CACHE
;
754 c
->options
|= MIPS_CPU_SB1_CACHE
;
756 switch (c
->processor_id
& 0xff00) {
758 c
->cputype
= CPU_SB1
;
759 /* FPU in pass1 is known to have issues. */
760 if ((c
->processor_id
& 0xff) < 0x02)
761 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
764 c
->cputype
= CPU_SB1A
;
769 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
)
772 switch (c
->processor_id
& 0xff00) {
773 case PRID_IMP_SR71000
:
774 c
->cputype
= CPU_SR71000
;
781 static inline void cpu_probe_philips(struct cpuinfo_mips
*c
)
784 switch (c
->processor_id
& 0xff00) {
785 case PRID_IMP_PR4450
:
786 c
->cputype
= CPU_PR4450
;
787 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
790 panic("Unknown Philips Core!"); /* REVISIT: die? */
796 __init
void cpu_probe(void)
798 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
800 c
->processor_id
= PRID_IMP_UNKNOWN
;
801 c
->fpu_id
= FPIR_IMP_NONE
;
802 c
->cputype
= CPU_UNKNOWN
;
804 c
->processor_id
= read_c0_prid();
805 switch (c
->processor_id
& 0xff0000) {
806 case PRID_COMP_LEGACY
:
812 case PRID_COMP_ALCHEMY
:
813 cpu_probe_alchemy(c
);
815 case PRID_COMP_SIBYTE
:
818 case PRID_COMP_SANDCRAFT
:
819 cpu_probe_sandcraft(c
);
821 case PRID_COMP_PHILIPS
:
822 cpu_probe_philips(c
);
825 c
->cputype
= CPU_UNKNOWN
;
827 if (c
->options
& MIPS_CPU_FPU
) {
828 c
->fpu_id
= cpu_get_fpu_id();
830 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
831 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
832 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
833 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
834 if (c
->fpu_id
& MIPS_FPIR_3D
)
835 c
->ases
|= MIPS_ASE_MIPS3D
;
840 __init
void cpu_report(void)
842 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
844 printk("CPU revision is: %08x\n", c
->processor_id
);
845 if (c
->options
& MIPS_CPU_FPU
)
846 printk("FPU revision is: %08x\n", c
->fpu_id
);
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