2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
30 static int __cpuinitdata mips_fpu_disabled
;
32 static int __init
fpu_disable(char *s
)
34 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
35 mips_fpu_disabled
= 1;
40 __setup("nofpu", fpu_disable
);
42 int __cpuinitdata mips_dsp_disabled
;
44 static int __init
dsp_disable(char *s
)
46 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
47 mips_dsp_disabled
= 1;
52 __setup("nodsp", dsp_disable
);
54 static inline void check_errata(void)
56 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
61 * Erratum "RPS May Cause Incorrect Instruction Execution"
62 * This code only handles VPE0, any SMP/SMTC/RTOS code
63 * making use of VPE1 will be responsable for that VPE.
65 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
66 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
73 void __init
check_bugs32(void)
79 * Probe whether cpu has config register by trying to play with
80 * alternate cache bit and see whether it matters.
81 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 static inline int cpu_has_confreg(void)
85 #ifdef CONFIG_CPU_R3000
86 extern unsigned long r3k_cache_size(unsigned long);
87 unsigned long size1
, size2
;
88 unsigned long cfg
= read_c0_conf();
90 size1
= r3k_cache_size(ST0_ISC
);
91 write_c0_conf(cfg
^ R30XX_CONF_AC
);
92 size2
= r3k_cache_size(ST0_ISC
);
94 return size1
!= size2
;
100 static inline void set_elf_platform(int cpu
, const char *plat
)
103 __elf_platform
= plat
;
107 * Get the FPU Implementation/Revision.
109 static inline unsigned long cpu_get_fpu_id(void)
111 unsigned long tmp
, fpu_id
;
113 tmp
= read_c0_status();
115 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
116 write_c0_status(tmp
);
121 * Check the CPU has an FPU the official way.
123 static inline int __cpu_has_fpu(void)
125 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
128 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
130 #ifdef __NEED_VMBITS_PROBE
131 write_c0_entryhi(0x3fffffffffffe000ULL
);
132 back_to_back_c0_hazard();
133 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
137 static void __cpuinit
set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
140 case MIPS_CPU_ISA_M64R2
:
141 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
142 case MIPS_CPU_ISA_M64R1
:
143 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
145 c
->isa_level
|= MIPS_CPU_ISA_V
;
146 case MIPS_CPU_ISA_IV
:
147 c
->isa_level
|= MIPS_CPU_ISA_IV
;
148 case MIPS_CPU_ISA_III
:
149 c
->isa_level
|= MIPS_CPU_ISA_I
| MIPS_CPU_ISA_II
|
153 case MIPS_CPU_ISA_M32R2
:
154 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
155 case MIPS_CPU_ISA_M32R1
:
156 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
157 case MIPS_CPU_ISA_II
:
158 c
->isa_level
|= MIPS_CPU_ISA_II
;
160 c
->isa_level
|= MIPS_CPU_ISA_I
;
165 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
166 "Unsupported ISA type, c0.config0: %d.";
168 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
170 unsigned int config0
;
173 config0
= read_c0_config();
175 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
176 c
->options
|= MIPS_CPU_TLB
;
177 isa
= (config0
& MIPS_CONF_AT
) >> 13;
180 switch ((config0
& MIPS_CONF_AR
) >> 10) {
182 set_isa(c
, MIPS_CPU_ISA_M32R1
);
185 set_isa(c
, MIPS_CPU_ISA_M32R2
);
192 switch ((config0
& MIPS_CONF_AR
) >> 10) {
194 set_isa(c
, MIPS_CPU_ISA_M64R1
);
197 set_isa(c
, MIPS_CPU_ISA_M64R2
);
207 return config0
& MIPS_CONF_M
;
210 panic(unknown_isa
, config0
);
213 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
215 unsigned int config1
;
217 config1
= read_c0_config1();
219 if (config1
& MIPS_CONF1_MD
)
220 c
->ases
|= MIPS_ASE_MDMX
;
221 if (config1
& MIPS_CONF1_WR
)
222 c
->options
|= MIPS_CPU_WATCH
;
223 if (config1
& MIPS_CONF1_CA
)
224 c
->ases
|= MIPS_ASE_MIPS16
;
225 if (config1
& MIPS_CONF1_EP
)
226 c
->options
|= MIPS_CPU_EJTAG
;
227 if (config1
& MIPS_CONF1_FP
) {
228 c
->options
|= MIPS_CPU_FPU
;
229 c
->options
|= MIPS_CPU_32FPR
;
232 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
234 return config1
& MIPS_CONF_M
;
237 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
239 unsigned int config2
;
241 config2
= read_c0_config2();
243 if (config2
& MIPS_CONF2_SL
)
244 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
246 return config2
& MIPS_CONF_M
;
249 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
251 unsigned int config3
;
253 config3
= read_c0_config3();
255 if (config3
& MIPS_CONF3_SM
) {
256 c
->ases
|= MIPS_ASE_SMARTMIPS
;
257 c
->options
|= MIPS_CPU_RIXI
;
259 if (config3
& MIPS_CONF3_RXI
)
260 c
->options
|= MIPS_CPU_RIXI
;
261 if (config3
& MIPS_CONF3_DSP
)
262 c
->ases
|= MIPS_ASE_DSP
;
263 if (config3
& MIPS_CONF3_DSP2P
)
264 c
->ases
|= MIPS_ASE_DSP2P
;
265 if (config3
& MIPS_CONF3_VINT
)
266 c
->options
|= MIPS_CPU_VINT
;
267 if (config3
& MIPS_CONF3_VEIC
)
268 c
->options
|= MIPS_CPU_VEIC
;
269 if (config3
& MIPS_CONF3_MT
)
270 c
->ases
|= MIPS_ASE_MIPSMT
;
271 if (config3
& MIPS_CONF3_ULRI
)
272 c
->options
|= MIPS_CPU_ULRI
;
273 if (config3
& MIPS_CONF3_ISA
)
274 c
->options
|= MIPS_CPU_MICROMIPS
;
275 #ifdef CONFIG_CPU_MICROMIPS
276 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE
);
278 if (config3
& MIPS_CONF3_VZ
)
279 c
->ases
|= MIPS_ASE_VZ
;
281 return config3
& MIPS_CONF_M
;
284 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
286 unsigned int config4
;
288 config4
= read_c0_config4();
290 if ((config4
& MIPS_CONF4_MMUEXTDEF
) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
292 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
294 c
->kscratch_mask
= (config4
>> 16) & 0xff;
296 return config4
& MIPS_CONF_M
;
299 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
303 /* MIPS32 or MIPS64 compliant CPU. */
304 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
305 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
307 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
309 ok
= decode_config0(c
); /* Read Config registers. */
310 BUG_ON(!ok
); /* Arch spec violation! */
312 ok
= decode_config1(c
);
314 ok
= decode_config2(c
);
316 ok
= decode_config3(c
);
318 ok
= decode_config4(c
);
320 mips_probe_watch_registers(c
);
323 c
->core
= read_c0_ebase() & 0x3ff;
326 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
329 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
331 switch (c
->processor_id
& 0xff00) {
333 c
->cputype
= CPU_R2000
;
334 __cpu_name
[cpu
] = "R2000";
335 set_isa(c
, MIPS_CPU_ISA_I
);
336 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
339 c
->options
|= MIPS_CPU_FPU
;
343 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
344 if (cpu_has_confreg()) {
345 c
->cputype
= CPU_R3081E
;
346 __cpu_name
[cpu
] = "R3081";
348 c
->cputype
= CPU_R3000A
;
349 __cpu_name
[cpu
] = "R3000A";
352 c
->cputype
= CPU_R3000
;
353 __cpu_name
[cpu
] = "R3000";
355 set_isa(c
, MIPS_CPU_ISA_I
);
356 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
359 c
->options
|= MIPS_CPU_FPU
;
363 if (read_c0_config() & CONF_SC
) {
364 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
365 c
->cputype
= CPU_R4400PC
;
366 __cpu_name
[cpu
] = "R4400PC";
368 c
->cputype
= CPU_R4000PC
;
369 __cpu_name
[cpu
] = "R4000PC";
372 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
373 c
->cputype
= CPU_R4400SC
;
374 __cpu_name
[cpu
] = "R4400SC";
376 c
->cputype
= CPU_R4000SC
;
377 __cpu_name
[cpu
] = "R4000SC";
381 set_isa(c
, MIPS_CPU_ISA_III
);
382 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
383 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
387 case PRID_IMP_VR41XX
:
388 set_isa(c
, MIPS_CPU_ISA_III
);
389 c
->options
= R4K_OPTS
;
391 switch (c
->processor_id
& 0xf0) {
392 case PRID_REV_VR4111
:
393 c
->cputype
= CPU_VR4111
;
394 __cpu_name
[cpu
] = "NEC VR4111";
396 case PRID_REV_VR4121
:
397 c
->cputype
= CPU_VR4121
;
398 __cpu_name
[cpu
] = "NEC VR4121";
400 case PRID_REV_VR4122
:
401 if ((c
->processor_id
& 0xf) < 0x3) {
402 c
->cputype
= CPU_VR4122
;
403 __cpu_name
[cpu
] = "NEC VR4122";
405 c
->cputype
= CPU_VR4181A
;
406 __cpu_name
[cpu
] = "NEC VR4181A";
409 case PRID_REV_VR4130
:
410 if ((c
->processor_id
& 0xf) < 0x4) {
411 c
->cputype
= CPU_VR4131
;
412 __cpu_name
[cpu
] = "NEC VR4131";
414 c
->cputype
= CPU_VR4133
;
415 c
->options
|= MIPS_CPU_LLSC
;
416 __cpu_name
[cpu
] = "NEC VR4133";
420 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
421 c
->cputype
= CPU_VR41XX
;
422 __cpu_name
[cpu
] = "NEC Vr41xx";
427 c
->cputype
= CPU_R4300
;
428 __cpu_name
[cpu
] = "R4300";
429 set_isa(c
, MIPS_CPU_ISA_III
);
430 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
435 c
->cputype
= CPU_R4600
;
436 __cpu_name
[cpu
] = "R4600";
437 set_isa(c
, MIPS_CPU_ISA_III
);
438 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
445 * This processor doesn't have an MMU, so it's not
446 * "real easy" to run Linux on it. It is left purely
447 * for documentation. Commented out because it shares
448 * it's c0_prid id number with the TX3900.
450 c
->cputype
= CPU_R4650
;
451 __cpu_name
[cpu
] = "R4650";
452 set_isa(c
, MIPS_CPU_ISA_III
);
453 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
458 set_isa(c
, MIPS_CPU_ISA_I
);
459 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
461 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
462 c
->cputype
= CPU_TX3927
;
463 __cpu_name
[cpu
] = "TX3927";
466 switch (c
->processor_id
& 0xff) {
467 case PRID_REV_TX3912
:
468 c
->cputype
= CPU_TX3912
;
469 __cpu_name
[cpu
] = "TX3912";
472 case PRID_REV_TX3922
:
473 c
->cputype
= CPU_TX3922
;
474 __cpu_name
[cpu
] = "TX3922";
481 c
->cputype
= CPU_R4700
;
482 __cpu_name
[cpu
] = "R4700";
483 set_isa(c
, MIPS_CPU_ISA_III
);
484 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
489 c
->cputype
= CPU_TX49XX
;
490 __cpu_name
[cpu
] = "R49XX";
491 set_isa(c
, MIPS_CPU_ISA_III
);
492 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
493 if (!(c
->processor_id
& 0x08))
494 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
498 c
->cputype
= CPU_R5000
;
499 __cpu_name
[cpu
] = "R5000";
500 set_isa(c
, MIPS_CPU_ISA_IV
);
501 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
506 c
->cputype
= CPU_R5432
;
507 __cpu_name
[cpu
] = "R5432";
508 set_isa(c
, MIPS_CPU_ISA_IV
);
509 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
510 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
514 c
->cputype
= CPU_R5500
;
515 __cpu_name
[cpu
] = "R5500";
516 set_isa(c
, MIPS_CPU_ISA_IV
);
517 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
518 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
521 case PRID_IMP_NEVADA
:
522 c
->cputype
= CPU_NEVADA
;
523 __cpu_name
[cpu
] = "Nevada";
524 set_isa(c
, MIPS_CPU_ISA_IV
);
525 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
526 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
530 c
->cputype
= CPU_R6000
;
531 __cpu_name
[cpu
] = "R6000";
532 set_isa(c
, MIPS_CPU_ISA_II
);
533 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
537 case PRID_IMP_R6000A
:
538 c
->cputype
= CPU_R6000A
;
539 __cpu_name
[cpu
] = "R6000A";
540 set_isa(c
, MIPS_CPU_ISA_II
);
541 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
545 case PRID_IMP_RM7000
:
546 c
->cputype
= CPU_RM7000
;
547 __cpu_name
[cpu
] = "RM7000";
548 set_isa(c
, MIPS_CPU_ISA_IV
);
549 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
552 * Undocumented RM7000: Bit 29 in the info register of
553 * the RM7000 v2.0 indicates if the TLB has 48 or 64
556 * 29 1 => 64 entry JTLB
559 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
561 case PRID_IMP_RM9000
:
562 c
->cputype
= CPU_RM9000
;
563 __cpu_name
[cpu
] = "RM9000";
564 set_isa(c
, MIPS_CPU_ISA_IV
);
565 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
568 * Bit 29 in the info register of the RM9000
569 * indicates if the TLB has 48 or 64 entries.
571 * 29 1 => 64 entry JTLB
574 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
577 c
->cputype
= CPU_R8000
;
578 __cpu_name
[cpu
] = "RM8000";
579 set_isa(c
, MIPS_CPU_ISA_IV
);
580 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
581 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
583 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
585 case PRID_IMP_R10000
:
586 c
->cputype
= CPU_R10000
;
587 __cpu_name
[cpu
] = "R10000";
588 set_isa(c
, MIPS_CPU_ISA_IV
);
589 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
590 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
591 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
595 case PRID_IMP_R12000
:
596 c
->cputype
= CPU_R12000
;
597 __cpu_name
[cpu
] = "R12000";
598 set_isa(c
, MIPS_CPU_ISA_IV
);
599 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
600 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
601 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
605 case PRID_IMP_R14000
:
606 c
->cputype
= CPU_R14000
;
607 __cpu_name
[cpu
] = "R14000";
608 set_isa(c
, MIPS_CPU_ISA_IV
);
609 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
610 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
611 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
615 case PRID_IMP_LOONGSON2
:
616 c
->cputype
= CPU_LOONGSON2
;
617 __cpu_name
[cpu
] = "ICT Loongson-2";
619 switch (c
->processor_id
& PRID_REV_MASK
) {
620 case PRID_REV_LOONGSON2E
:
621 set_elf_platform(cpu
, "loongson2e");
623 case PRID_REV_LOONGSON2F
:
624 set_elf_platform(cpu
, "loongson2f");
628 set_isa(c
, MIPS_CPU_ISA_III
);
629 c
->options
= R4K_OPTS
|
630 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
634 case PRID_IMP_LOONGSON1
:
637 c
->cputype
= CPU_LOONGSON1
;
639 switch (c
->processor_id
& PRID_REV_MASK
) {
640 case PRID_REV_LOONGSON1B
:
641 __cpu_name
[cpu
] = "Loongson 1B";
649 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
652 switch (c
->processor_id
& 0xff00) {
654 c
->cputype
= CPU_4KC
;
655 __cpu_name
[cpu
] = "MIPS 4Kc";
658 case PRID_IMP_4KECR2
:
659 c
->cputype
= CPU_4KEC
;
660 __cpu_name
[cpu
] = "MIPS 4KEc";
664 c
->cputype
= CPU_4KSC
;
665 __cpu_name
[cpu
] = "MIPS 4KSc";
668 c
->cputype
= CPU_5KC
;
669 __cpu_name
[cpu
] = "MIPS 5Kc";
672 c
->cputype
= CPU_5KE
;
673 __cpu_name
[cpu
] = "MIPS 5KE";
676 c
->cputype
= CPU_20KC
;
677 __cpu_name
[cpu
] = "MIPS 20Kc";
680 c
->cputype
= CPU_24K
;
681 __cpu_name
[cpu
] = "MIPS 24Kc";
684 c
->cputype
= CPU_24K
;
685 __cpu_name
[cpu
] = "MIPS 24KEc";
688 c
->cputype
= CPU_25KF
;
689 __cpu_name
[cpu
] = "MIPS 25Kc";
692 c
->cputype
= CPU_34K
;
693 __cpu_name
[cpu
] = "MIPS 34Kc";
696 c
->cputype
= CPU_74K
;
697 __cpu_name
[cpu
] = "MIPS 74Kc";
700 c
->cputype
= CPU_M14KC
;
701 __cpu_name
[cpu
] = "MIPS M14Kc";
703 case PRID_IMP_M14KEC
:
704 c
->cputype
= CPU_M14KEC
;
705 __cpu_name
[cpu
] = "MIPS M14KEc";
708 c
->cputype
= CPU_1004K
;
709 __cpu_name
[cpu
] = "MIPS 1004Kc";
712 c
->cputype
= CPU_74K
;
713 __cpu_name
[cpu
] = "MIPS 1074Kc";
720 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
723 switch (c
->processor_id
& 0xff00) {
724 case PRID_IMP_AU1_REV1
:
725 case PRID_IMP_AU1_REV2
:
726 c
->cputype
= CPU_ALCHEMY
;
727 switch ((c
->processor_id
>> 24) & 0xff) {
729 __cpu_name
[cpu
] = "Au1000";
732 __cpu_name
[cpu
] = "Au1500";
735 __cpu_name
[cpu
] = "Au1100";
738 __cpu_name
[cpu
] = "Au1550";
741 __cpu_name
[cpu
] = "Au1200";
742 if ((c
->processor_id
& 0xff) == 2)
743 __cpu_name
[cpu
] = "Au1250";
746 __cpu_name
[cpu
] = "Au1210";
749 __cpu_name
[cpu
] = "Au1xxx";
756 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
760 switch (c
->processor_id
& 0xff00) {
762 c
->cputype
= CPU_SB1
;
763 __cpu_name
[cpu
] = "SiByte SB1";
764 /* FPU in pass1 is known to have issues. */
765 if ((c
->processor_id
& 0xff) < 0x02)
766 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
769 c
->cputype
= CPU_SB1A
;
770 __cpu_name
[cpu
] = "SiByte SB1A";
775 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
778 switch (c
->processor_id
& 0xff00) {
779 case PRID_IMP_SR71000
:
780 c
->cputype
= CPU_SR71000
;
781 __cpu_name
[cpu
] = "Sandcraft SR71000";
788 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
791 switch (c
->processor_id
& 0xff00) {
792 case PRID_IMP_PR4450
:
793 c
->cputype
= CPU_PR4450
;
794 __cpu_name
[cpu
] = "Philips PR4450";
795 set_isa(c
, MIPS_CPU_ISA_M32R1
);
800 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
803 switch (c
->processor_id
& 0xff00) {
804 case PRID_IMP_BMIPS32_REV4
:
805 case PRID_IMP_BMIPS32_REV8
:
806 c
->cputype
= CPU_BMIPS32
;
807 __cpu_name
[cpu
] = "Broadcom BMIPS32";
808 set_elf_platform(cpu
, "bmips32");
810 case PRID_IMP_BMIPS3300
:
811 case PRID_IMP_BMIPS3300_ALT
:
812 case PRID_IMP_BMIPS3300_BUG
:
813 c
->cputype
= CPU_BMIPS3300
;
814 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
815 set_elf_platform(cpu
, "bmips3300");
817 case PRID_IMP_BMIPS43XX
: {
818 int rev
= c
->processor_id
& 0xff;
820 if (rev
>= PRID_REV_BMIPS4380_LO
&&
821 rev
<= PRID_REV_BMIPS4380_HI
) {
822 c
->cputype
= CPU_BMIPS4380
;
823 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
824 set_elf_platform(cpu
, "bmips4380");
826 c
->cputype
= CPU_BMIPS4350
;
827 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
828 set_elf_platform(cpu
, "bmips4350");
832 case PRID_IMP_BMIPS5000
:
833 c
->cputype
= CPU_BMIPS5000
;
834 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
835 set_elf_platform(cpu
, "bmips5000");
836 c
->options
|= MIPS_CPU_ULRI
;
841 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
844 switch (c
->processor_id
& 0xff00) {
845 case PRID_IMP_CAVIUM_CN38XX
:
846 case PRID_IMP_CAVIUM_CN31XX
:
847 case PRID_IMP_CAVIUM_CN30XX
:
848 c
->cputype
= CPU_CAVIUM_OCTEON
;
849 __cpu_name
[cpu
] = "Cavium Octeon";
851 case PRID_IMP_CAVIUM_CN58XX
:
852 case PRID_IMP_CAVIUM_CN56XX
:
853 case PRID_IMP_CAVIUM_CN50XX
:
854 case PRID_IMP_CAVIUM_CN52XX
:
855 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
856 __cpu_name
[cpu
] = "Cavium Octeon+";
858 set_elf_platform(cpu
, "octeon");
860 case PRID_IMP_CAVIUM_CN61XX
:
861 case PRID_IMP_CAVIUM_CN63XX
:
862 case PRID_IMP_CAVIUM_CN66XX
:
863 case PRID_IMP_CAVIUM_CN68XX
:
864 c
->cputype
= CPU_CAVIUM_OCTEON2
;
865 __cpu_name
[cpu
] = "Cavium Octeon II";
866 set_elf_platform(cpu
, "octeon2");
869 printk(KERN_INFO
"Unknown Octeon chip!\n");
870 c
->cputype
= CPU_UNKNOWN
;
875 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
878 /* JZRISC does not implement the CP0 counter. */
879 c
->options
&= ~MIPS_CPU_COUNTER
;
880 switch (c
->processor_id
& 0xff00) {
881 case PRID_IMP_JZRISC
:
882 c
->cputype
= CPU_JZRISC
;
883 __cpu_name
[cpu
] = "Ingenic JZRISC";
886 panic("Unknown Ingenic Processor ID!");
891 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
895 if ((c
->processor_id
& 0xff00) == PRID_IMP_NETLOGIC_AU13XX
) {
896 c
->cputype
= CPU_ALCHEMY
;
897 __cpu_name
[cpu
] = "Au1300";
898 /* following stuff is not for Alchemy */
902 c
->options
= (MIPS_CPU_TLB
|
910 switch (c
->processor_id
& 0xff00) {
911 case PRID_IMP_NETLOGIC_XLP8XX
:
912 case PRID_IMP_NETLOGIC_XLP3XX
:
913 c
->cputype
= CPU_XLP
;
914 __cpu_name
[cpu
] = "Netlogic XLP";
917 case PRID_IMP_NETLOGIC_XLR732
:
918 case PRID_IMP_NETLOGIC_XLR716
:
919 case PRID_IMP_NETLOGIC_XLR532
:
920 case PRID_IMP_NETLOGIC_XLR308
:
921 case PRID_IMP_NETLOGIC_XLR532C
:
922 case PRID_IMP_NETLOGIC_XLR516C
:
923 case PRID_IMP_NETLOGIC_XLR508C
:
924 case PRID_IMP_NETLOGIC_XLR308C
:
925 c
->cputype
= CPU_XLR
;
926 __cpu_name
[cpu
] = "Netlogic XLR";
929 case PRID_IMP_NETLOGIC_XLS608
:
930 case PRID_IMP_NETLOGIC_XLS408
:
931 case PRID_IMP_NETLOGIC_XLS404
:
932 case PRID_IMP_NETLOGIC_XLS208
:
933 case PRID_IMP_NETLOGIC_XLS204
:
934 case PRID_IMP_NETLOGIC_XLS108
:
935 case PRID_IMP_NETLOGIC_XLS104
:
936 case PRID_IMP_NETLOGIC_XLS616B
:
937 case PRID_IMP_NETLOGIC_XLS608B
:
938 case PRID_IMP_NETLOGIC_XLS416B
:
939 case PRID_IMP_NETLOGIC_XLS412B
:
940 case PRID_IMP_NETLOGIC_XLS408B
:
941 case PRID_IMP_NETLOGIC_XLS404B
:
942 c
->cputype
= CPU_XLR
;
943 __cpu_name
[cpu
] = "Netlogic XLS";
947 pr_info("Unknown Netlogic chip id [%02x]!\n",
949 c
->cputype
= CPU_XLR
;
953 if (c
->cputype
== CPU_XLP
) {
954 set_isa(c
, MIPS_CPU_ISA_M64R2
);
955 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
956 /* This will be updated again after all threads are woken up */
957 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
959 set_isa(c
, MIPS_CPU_ISA_M64R1
);
960 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
965 /* For use by uaccess.h */
967 EXPORT_SYMBOL(__ua_limit
);
970 const char *__cpu_name
[NR_CPUS
];
971 const char *__elf_platform
;
973 __cpuinit
void cpu_probe(void)
975 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
976 unsigned int cpu
= smp_processor_id();
978 c
->processor_id
= PRID_IMP_UNKNOWN
;
979 c
->fpu_id
= FPIR_IMP_NONE
;
980 c
->cputype
= CPU_UNKNOWN
;
982 c
->processor_id
= read_c0_prid();
983 switch (c
->processor_id
& 0xff0000) {
984 case PRID_COMP_LEGACY
:
985 cpu_probe_legacy(c
, cpu
);
988 cpu_probe_mips(c
, cpu
);
990 case PRID_COMP_ALCHEMY
:
991 cpu_probe_alchemy(c
, cpu
);
993 case PRID_COMP_SIBYTE
:
994 cpu_probe_sibyte(c
, cpu
);
996 case PRID_COMP_BROADCOM
:
997 cpu_probe_broadcom(c
, cpu
);
999 case PRID_COMP_SANDCRAFT
:
1000 cpu_probe_sandcraft(c
, cpu
);
1003 cpu_probe_nxp(c
, cpu
);
1005 case PRID_COMP_CAVIUM
:
1006 cpu_probe_cavium(c
, cpu
);
1008 case PRID_COMP_INGENIC
:
1009 cpu_probe_ingenic(c
, cpu
);
1011 case PRID_COMP_NETLOGIC
:
1012 cpu_probe_netlogic(c
, cpu
);
1016 BUG_ON(!__cpu_name
[cpu
]);
1017 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1020 * Platform code can force the cpu type to optimize code
1021 * generation. In that case be sure the cpu type is correctly
1022 * manually setup otherwise it could trigger some nasty bugs.
1024 BUG_ON(current_cpu_type() != c
->cputype
);
1026 if (mips_fpu_disabled
)
1027 c
->options
&= ~MIPS_CPU_FPU
;
1029 if (mips_dsp_disabled
)
1030 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1032 if (c
->options
& MIPS_CPU_FPU
) {
1033 c
->fpu_id
= cpu_get_fpu_id();
1035 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M32R2
|
1036 MIPS_CPU_ISA_M64R1
| MIPS_CPU_ISA_M64R2
)) {
1037 if (c
->fpu_id
& MIPS_FPIR_3D
)
1038 c
->ases
|= MIPS_ASE_MIPS3D
;
1042 if (cpu_has_mips_r2
) {
1043 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1044 /* R2 has Performance Counter Interrupt indicator */
1045 c
->options
|= MIPS_CPU_PCI
;
1050 cpu_probe_vmbits(c
);
1054 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1058 __cpuinit
void cpu_report(void)
1060 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1062 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
1063 c
->processor_id
, cpu_name_string());
1064 if (c
->options
& MIPS_CPU_FPU
)
1065 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);