arch/mips/kernel/i8259.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   7  *
   8  * Copyright (C) 1992 Linus Torvalds
   9  * Copyright (C) 1994 - 2000 Ralf Baechle
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/sysdev.h>
  18
  19 #include <asm/i8259.h>
  20 #include <asm/io.h>
  21
  22 /*
  23  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  24  * present in the majority of PC/AT boxes.
  25  * plus some generic x86 specific things if generic specifics makes
  26  * any sense at all.
  27  * this file should become arch/i386/kernel/irq.c when the old irq.c
  28  * moves to arch independent land
  29  */
  30
  31 static int i8259A_auto_eoi = -1;
  32 DEFINE_SPINLOCK(i8259A_lock);
  33 /* some platforms call this... */
  34 void mask_and_ack_8259A(unsigned int);
  35
  36 static struct irq_chip i8259A_chip = {
  37         .name           = "XT-PIC",
  38         .mask           = disable_8259A_irq,
  39         .unmask         = enable_8259A_irq,
  40         .mask_ack       = mask_and_ack_8259A,
  41 };
  42
  43 /*
  44  * 8259A PIC functions to handle ISA devices:
  45  */
  46
  47 /*
  48  * This contains the irq mask for both 8259A irq controllers,
  49  */
  50 static unsigned int cached_irq_mask = 0xffff;
  51
  52 #define cached_master_mask      (cached_irq_mask)
  53 #define cached_slave_mask       (cached_irq_mask >> 8)
  54
  55 void disable_8259A_irq(unsigned int irq)
  56 {
  57         unsigned int mask;
  58         unsigned long flags;
  59
  60         irq -= I8259A_IRQ_BASE;
  61         mask = 1 << irq;
  62         spin_lock_irqsave(&i8259A_lock, flags);
  63         cached_irq_mask |= mask;
  64         if (irq & 8)
  65                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  66         else
  67                 outb(cached_master_mask, PIC_MASTER_IMR);
  68         spin_unlock_irqrestore(&i8259A_lock, flags);
  69 }
  70
  71 void enable_8259A_irq(unsigned int irq)
  72 {
  73         unsigned int mask;
  74         unsigned long flags;
  75
  76         irq -= I8259A_IRQ_BASE;
  77         mask = ~(1 << irq);
  78         spin_lock_irqsave(&i8259A_lock, flags);
  79         cached_irq_mask &= mask;
  80         if (irq & 8)
  81                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  82         else
  83                 outb(cached_master_mask, PIC_MASTER_IMR);
  84         spin_unlock_irqrestore(&i8259A_lock, flags);
  85 }
  86
  87 int i8259A_irq_pending(unsigned int irq)
  88 {
  89         unsigned int mask;
  90         unsigned long flags;
  91         int ret;
  92
  93         irq -= I8259A_IRQ_BASE;
  94         mask = 1 << irq;
  95         spin_lock_irqsave(&i8259A_lock, flags);
  96         if (irq < 8)
  97                 ret = inb(PIC_MASTER_CMD) & mask;
  98         else
  99                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
 100         spin_unlock_irqrestore(&i8259A_lock, flags);
 101
 102         return ret;
 103 }
 104
 105 void make_8259A_irq(unsigned int irq)
 106 {
 107         disable_irq_nosync(irq);
 108         set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
 109         enable_irq(irq);
 110 }
 111
 112 /*
 113  * This function assumes to be called rarely. Switching between
 114  * 8259A registers is slow.
 115  * This has to be protected by the irq controller spinlock
 116  * before being called.
 117  */
 118 static inline int i8259A_irq_real(unsigned int irq)
 119 {
 120         int value;
 121         int irqmask = 1 << irq;
 122
 123         if (irq < 8) {
 124                 outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
 125                 value = inb(PIC_MASTER_CMD) & irqmask;
 126                 outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
 127                 return value;
 128         }
 129         outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
 130         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 131         outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
 132         return value;
 133 }
 134
 135 /*
 136  * Careful! The 8259A is a fragile beast, it pretty
 137  * much _has_ to be done exactly like this (mask it
 138  * first, _then_ send the EOI, and the order of EOI
 139  * to the two 8259s is important!
 140  */
 141 void mask_and_ack_8259A(unsigned int irq)
 142 {
 143         unsigned int irqmask;
 144         unsigned long flags;
 145
 146         irq -= I8259A_IRQ_BASE;
 147         irqmask = 1 << irq;
 148         spin_lock_irqsave(&i8259A_lock, flags);
 149         /*
 150          * Lightweight spurious IRQ detection. We do not want
 151          * to overdo spurious IRQ handling - it's usually a sign
 152          * of hardware problems, so we only do the checks we can
 153          * do without slowing down good hardware unnecessarily.
 154          *
 155          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 156          * usually resulting from the 8259A-1|2 PICs) occur
 157          * even if the IRQ is masked in the 8259A. Thus we
 158          * can check spurious 8259A IRQs without doing the
 159          * quite slow i8259A_irq_real() call for every IRQ.
 160          * This does not cover 100% of spurious interrupts,
 161          * but should be enough to warn the user that there
 162          * is something bad going on ...
 163          */
 164         if (cached_irq_mask & irqmask)
 165                 goto spurious_8259A_irq;
 166         cached_irq_mask |= irqmask;
 167
 168 handle_real_irq:
 169         if (irq & 8) {
 170                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 171                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 172                 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
 173                 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
 174         } else {
 175                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 176                 outb(cached_master_mask, PIC_MASTER_IMR);
 177                 outb(0x60+irq,PIC_MASTER_CMD);  /* 'Specific EOI to master */
 178         }
 179 #ifdef CONFIG_MIPS_MT_SMTC
 180         if (irq_hwmask[irq] & ST0_IM)
 181                 set_c0_status(irq_hwmask[irq] & ST0_IM);
 182 #endif /* CONFIG_MIPS_MT_SMTC */
 183         spin_unlock_irqrestore(&i8259A_lock, flags);
 184         return;
 185
 186 spurious_8259A_irq:
 187         /*
 188          * this is the slow path - should happen rarely.
 189          */
 190         if (i8259A_irq_real(irq))
 191                 /*
 192                  * oops, the IRQ _is_ in service according to the
 193                  * 8259A - not spurious, go handle it.
 194                  */
 195                 goto handle_real_irq;
 196
 197         {
 198                 static int spurious_irq_mask;
 199                 /*
 200                  * At this point we can be sure the IRQ is spurious,
 201                  * lets ACK and report it. [once per IRQ]
 202                  */
 203                 if (!(spurious_irq_mask & irqmask)) {
 204                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 205                         spurious_irq_mask |= irqmask;
 206                 }
 207                 atomic_inc(&irq_err_count);
 208                 /*
 209                  * Theoretically we do not have to handle this IRQ,
 210                  * but in Linux this does not cause problems and is
 211                  * simpler for us.
 212                  */
 213                 goto handle_real_irq;
 214         }
 215 }
 216
 217 static int i8259A_resume(struct sys_device *dev)
 218 {
 219         if (i8259A_auto_eoi >= 0)
 220                 init_8259A(i8259A_auto_eoi);
 221         return 0;
 222 }
 223
 224 static int i8259A_shutdown(struct sys_device *dev)
 225 {
 226         /* Put the i8259A into a quiescent state that
 227          * the kernel initialization code can get it
 228          * out of.
 229          */
 230         if (i8259A_auto_eoi >= 0) {
 231                 outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 232                 outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 233         }
 234         return 0;
 235 }
 236
 237 static struct sysdev_class i8259_sysdev_class = {
 238         set_kset_name("i8259"),
 239         .resume = i8259A_resume,
 240         .shutdown = i8259A_shutdown,
 241 };
 242
 243 static struct sys_device device_i8259A = {
 244         .id     = 0,
 245         .cls    = &i8259_sysdev_class,
 246 };
 247
 248 static int __init i8259A_init_sysfs(void)
 249 {
 250         int error = sysdev_class_register(&i8259_sysdev_class);
 251         if (!error)
 252                 error = sysdev_register(&device_i8259A);
 253         return error;
 254 }
 255
 256 device_initcall(i8259A_init_sysfs);
 257
 258 void init_8259A(int auto_eoi)
 259 {
 260         unsigned long flags;
 261
 262         i8259A_auto_eoi = auto_eoi;
 263
 264         spin_lock_irqsave(&i8259A_lock, flags);
 265
 266         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 267         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 268
 269         /*
 270          * outb_p - this has to work on a wide range of PC hardware.
 271          */
 272         outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
 273         outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);    /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
 274         outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
 275         if (auto_eoi)   /* master does Auto EOI */
 276                 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 277         else            /* master expects normal EOI */
 278                 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 279
 280         outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
 281         outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);     /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
 282         outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
 283         outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
 284         if (auto_eoi)
 285                 /*
 286                  * In AEOI mode we just have to mask the interrupt
 287                  * when acking.
 288                  */
 289                 i8259A_chip.mask_ack = disable_8259A_irq;
 290         else
 291                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 292
 293         udelay(100);            /* wait for 8259A to initialize */
 294
 295         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 296         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 297
 298         spin_unlock_irqrestore(&i8259A_lock, flags);
 299 }
 300
 301 /*
 302  * IRQ2 is cascade interrupt to second interrupt controller
 303  */
 304 static struct irqaction irq2 = {
 305         no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
 306 };
 307
 308 static struct resource pic1_io_resource = {
 309         .name = "pic1",
 310         .start = PIC_MASTER_CMD,
 311         .end = PIC_MASTER_IMR,
 312         .flags = IORESOURCE_BUSY
 313 };
 314
 315 static struct resource pic2_io_resource = {
 316         .name = "pic2",
 317         .start = PIC_SLAVE_CMD,
 318         .end = PIC_SLAVE_IMR,
 319         .flags = IORESOURCE_BUSY
 320 };
 321
 322 /*
 323  * On systems with i8259-style interrupt controllers we assume for
 324  * driver compatibility reasons interrupts 0 - 15 to be the i8259
 325  * interrupts even if the hardware uses a different interrupt numbering.
 326  */
 327 void __init init_i8259_irqs (void)
 328 {
 329         int i;
 330
 331         insert_resource(&ioport_resource, &pic1_io_resource);
 332         insert_resource(&ioport_resource, &pic2_io_resource);
 333
 334         init_8259A(0);
 335
 336         for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++)
 337                 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
 338
 339         setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
 340 }