arch/mips/kernel/i8259.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   7  *
   8  * Copyright (C) 1992 Linus Torvalds
   9  * Copyright (C) 1994 - 2000 Ralf Baechle
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/sysdev.h>
  18
  19 #include <asm/i8259.h>
  20 #include <asm/io.h>
  21
  22 /*
  23  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  24  * present in the majority of PC/AT boxes.
  25  * plus some generic x86 specific things if generic specifics makes
  26  * any sense at all.
  27  * this file should become arch/i386/kernel/irq.c when the old irq.c
  28  * moves to arch independent land
  29  */
  30
  31 static int i8259A_auto_eoi;
  32 DEFINE_SPINLOCK(i8259A_lock);
  33 /* some platforms call this... */
  34 void mask_and_ack_8259A(unsigned int);
  35
  36 static struct irq_chip i8259A_chip = {
  37         .name           = "XT-PIC",
  38         .mask           = disable_8259A_irq,
  39         .unmask         = enable_8259A_irq,
  40         .mask_ack       = mask_and_ack_8259A,
  41 };
  42
  43 /*
  44  * 8259A PIC functions to handle ISA devices:
  45  */
  46
  47 /*
  48  * This contains the irq mask for both 8259A irq controllers,
  49  */
  50 static unsigned int cached_irq_mask = 0xffff;
  51
  52 #define cached_master_mask      (cached_irq_mask)
  53 #define cached_slave_mask       (cached_irq_mask >> 8)
  54
  55 void disable_8259A_irq(unsigned int irq)
  56 {
  57         unsigned int mask = 1 << irq;
  58         unsigned long flags;
  59
  60         spin_lock_irqsave(&i8259A_lock, flags);
  61         cached_irq_mask |= mask;
  62         if (irq & 8)
  63                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  64         else
  65                 outb(cached_master_mask, PIC_MASTER_IMR);
  66         spin_unlock_irqrestore(&i8259A_lock, flags);
  67 }
  68
  69 void enable_8259A_irq(unsigned int irq)
  70 {
  71         unsigned int mask = ~(1 << irq);
  72         unsigned long flags;
  73
  74         spin_lock_irqsave(&i8259A_lock, flags);
  75         cached_irq_mask &= mask;
  76         if (irq & 8)
  77                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  78         else
  79                 outb(cached_master_mask, PIC_MASTER_IMR);
  80         spin_unlock_irqrestore(&i8259A_lock, flags);
  81 }
  82
  83 int i8259A_irq_pending(unsigned int irq)
  84 {
  85         unsigned int mask = 1 << irq;
  86         unsigned long flags;
  87         int ret;
  88
  89         spin_lock_irqsave(&i8259A_lock, flags);
  90         if (irq < 8)
  91                 ret = inb(PIC_MASTER_CMD) & mask;
  92         else
  93                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
  94         spin_unlock_irqrestore(&i8259A_lock, flags);
  95
  96         return ret;
  97 }
  98
  99 void make_8259A_irq(unsigned int irq)
 100 {
 101         disable_irq_nosync(irq);
 102         set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
 103         enable_irq(irq);
 104 }
 105
 106 /*
 107  * This function assumes to be called rarely. Switching between
 108  * 8259A registers is slow.
 109  * This has to be protected by the irq controller spinlock
 110  * before being called.
 111  */
 112 static inline int i8259A_irq_real(unsigned int irq)
 113 {
 114         int value;
 115         int irqmask = 1 << irq;
 116
 117         if (irq < 8) {
 118                 outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
 119                 value = inb(PIC_MASTER_CMD) & irqmask;
 120                 outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
 121                 return value;
 122         }
 123         outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
 124         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 125         outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
 126         return value;
 127 }
 128
 129 /*
 130  * Careful! The 8259A is a fragile beast, it pretty
 131  * much _has_ to be done exactly like this (mask it
 132  * first, _then_ send the EOI, and the order of EOI
 133  * to the two 8259s is important!
 134  */
 135 void mask_and_ack_8259A(unsigned int irq)
 136 {
 137         unsigned int irqmask = 1 << irq;
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&i8259A_lock, flags);
 141         /*
 142          * Lightweight spurious IRQ detection. We do not want
 143          * to overdo spurious IRQ handling - it's usually a sign
 144          * of hardware problems, so we only do the checks we can
 145          * do without slowing down good hardware unnecessarily.
 146          *
 147          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 148          * usually resulting from the 8259A-1|2 PICs) occur
 149          * even if the IRQ is masked in the 8259A. Thus we
 150          * can check spurious 8259A IRQs without doing the
 151          * quite slow i8259A_irq_real() call for every IRQ.
 152          * This does not cover 100% of spurious interrupts,
 153          * but should be enough to warn the user that there
 154          * is something bad going on ...
 155          */
 156         if (cached_irq_mask & irqmask)
 157                 goto spurious_8259A_irq;
 158         cached_irq_mask |= irqmask;
 159
 160 handle_real_irq:
 161         if (irq & 8) {
 162                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 163                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 164                 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
 165                 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
 166         } else {
 167                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 168                 outb(cached_master_mask, PIC_MASTER_IMR);
 169                 outb(0x60+irq,PIC_MASTER_CMD);  /* 'Specific EOI to master */
 170         }
 171 #ifdef CONFIG_MIPS_MT_SMTC
 172         if (irq_hwmask[irq] & ST0_IM)
 173                 set_c0_status(irq_hwmask[irq] & ST0_IM);
 174 #endif /* CONFIG_MIPS_MT_SMTC */
 175         spin_unlock_irqrestore(&i8259A_lock, flags);
 176         return;
 177
 178 spurious_8259A_irq:
 179         /*
 180          * this is the slow path - should happen rarely.
 181          */
 182         if (i8259A_irq_real(irq))
 183                 /*
 184                  * oops, the IRQ _is_ in service according to the
 185                  * 8259A - not spurious, go handle it.
 186                  */
 187                 goto handle_real_irq;
 188
 189         {
 190                 static int spurious_irq_mask;
 191                 /*
 192                  * At this point we can be sure the IRQ is spurious,
 193                  * lets ACK and report it. [once per IRQ]
 194                  */
 195                 if (!(spurious_irq_mask & irqmask)) {
 196                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 197                         spurious_irq_mask |= irqmask;
 198                 }
 199                 atomic_inc(&irq_err_count);
 200                 /*
 201                  * Theoretically we do not have to handle this IRQ,
 202                  * but in Linux this does not cause problems and is
 203                  * simpler for us.
 204                  */
 205                 goto handle_real_irq;
 206         }
 207 }
 208
 209 static int i8259A_resume(struct sys_device *dev)
 210 {
 211         init_8259A(i8259A_auto_eoi);
 212         return 0;
 213 }
 214
 215 static int i8259A_shutdown(struct sys_device *dev)
 216 {
 217         /* Put the i8259A into a quiescent state that
 218          * the kernel initialization code can get it
 219          * out of.
 220          */
 221         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 222         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 223         return 0;
 224 }
 225
 226 static struct sysdev_class i8259_sysdev_class = {
 227         set_kset_name("i8259"),
 228         .resume = i8259A_resume,
 229         .shutdown = i8259A_shutdown,
 230 };
 231
 232 static struct sys_device device_i8259A = {
 233         .id     = 0,
 234         .cls    = &i8259_sysdev_class,
 235 };
 236
 237 static int __init i8259A_init_sysfs(void)
 238 {
 239         int error = sysdev_class_register(&i8259_sysdev_class);
 240         if (!error)
 241                 error = sysdev_register(&device_i8259A);
 242         return error;
 243 }
 244
 245 device_initcall(i8259A_init_sysfs);
 246
 247 void __init init_8259A(int auto_eoi)
 248 {
 249         unsigned long flags;
 250
 251         i8259A_auto_eoi = auto_eoi;
 252
 253         spin_lock_irqsave(&i8259A_lock, flags);
 254
 255         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 256         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 257
 258         /*
 259          * outb_p - this has to work on a wide range of PC hardware.
 260          */
 261         outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
 262         outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);    /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
 263         outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
 264         if (auto_eoi)   /* master does Auto EOI */
 265                 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 266         else            /* master expects normal EOI */
 267                 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 268
 269         outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
 270         outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);     /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
 271         outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
 272         outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
 273         if (auto_eoi)
 274                 /*
 275                  * In AEOI mode we just have to mask the interrupt
 276                  * when acking.
 277                  */
 278                 i8259A_chip.mask_ack = disable_8259A_irq;
 279         else
 280                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 281
 282         udelay(100);            /* wait for 8259A to initialize */
 283
 284         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 285         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 286
 287         spin_unlock_irqrestore(&i8259A_lock, flags);
 288 }
 289
 290 /*
 291  * IRQ2 is cascade interrupt to second interrupt controller
 292  */
 293 static struct irqaction irq2 = {
 294         no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
 295 };
 296
 297 static struct resource pic1_io_resource = {
 298         .name = "pic1",
 299         .start = PIC_MASTER_CMD,
 300         .end = PIC_MASTER_IMR,
 301         .flags = IORESOURCE_BUSY
 302 };
 303
 304 static struct resource pic2_io_resource = {
 305         .name = "pic2",
 306         .start = PIC_SLAVE_CMD,
 307         .end = PIC_SLAVE_IMR,
 308         .flags = IORESOURCE_BUSY
 309 };
 310
 311 /*
 312  * On systems with i8259-style interrupt controllers we assume for
 313  * driver compatibility reasons interrupts 0 - 15 to be the i8259
 314  * interrupts even if the hardware uses a different interrupt numbering.
 315  */
 316 void __init init_i8259_irqs (void)
 317 {
 318         int i;
 319
 320         request_resource(&ioport_resource, &pic1_io_resource);
 321         request_resource(&ioport_resource, &pic2_io_resource);
 322
 323         init_8259A(0);
 324
 325         for (i = 0; i < 16; i++)
 326                 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
 327
 328         setup_irq(PIC_CASCADE_IR, &irq2);
 329 }