2 * Copyright (c) 2004 MIPS Inc
3 * Author: chris@mips.com
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <asm/ptrace.h>
14 #include <linux/sched.h>
15 #include <linux/kernel_stat.h>
18 #include <asm/msc01_ic.h>
20 static unsigned long _icctrl_msc
;
21 #define MSC01_IC_REG_BASE _icctrl_msc
23 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
24 #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
26 static unsigned int irq_base
;
28 /* mask off an interrupt */
29 static inline void mask_msc_irq(unsigned int irq
)
31 if (irq
< (irq_base
+ 32))
32 MSCIC_WRITE(MSC01_IC_DISL
, 1<<(irq
- irq_base
));
34 MSCIC_WRITE(MSC01_IC_DISH
, 1<<(irq
- irq_base
- 32));
37 /* unmask an interrupt */
38 static inline void unmask_msc_irq(unsigned int irq
)
40 if (irq
< (irq_base
+ 32))
41 MSCIC_WRITE(MSC01_IC_ENAL
, 1<<(irq
- irq_base
));
43 MSCIC_WRITE(MSC01_IC_ENAH
, 1<<(irq
- irq_base
- 32));
47 * Enables the IRQ on SOC-it
49 static void enable_msc_irq(unsigned int irq
)
55 * Initialize the IRQ on SOC-it
57 static unsigned int startup_msc_irq(unsigned int irq
)
64 * Disables the IRQ on SOC-it
66 static void disable_msc_irq(unsigned int irq
)
72 * Masks and ACKs an IRQ
74 static void level_mask_and_ack_msc_irq(unsigned int irq
)
78 MSCIC_WRITE(MSC01_IC_EOI
, 0);
79 #ifdef CONFIG_MIPS_MT_SMTC
80 /* This actually needs to be a call into platform code */
81 if (irq_hwmask
[irq
] & ST0_IM
)
82 set_c0_status(irq_hwmask
[irq
] & ST0_IM
);
83 #endif /* CONFIG_MIPS_MT_SMTC */
87 * Masks and ACKs an IRQ
89 static void edge_mask_and_ack_msc_irq(unsigned int irq
)
93 MSCIC_WRITE(MSC01_IC_EOI
, 0);
96 MSCIC_READ(MSC01_IC_SUP
+irq
*8, r
);
97 MSCIC_WRITE(MSC01_IC_SUP
+irq
*8, r
| ~MSC01_IC_SUP_EDGE_BIT
);
98 MSCIC_WRITE(MSC01_IC_SUP
+irq
*8, r
);
100 #ifdef CONFIG_MIPS_MT_SMTC
101 if (irq_hwmask
[irq
] & ST0_IM
)
102 set_c0_status(irq_hwmask
[irq
] & ST0_IM
);
103 #endif /* CONFIG_MIPS_MT_SMTC */
109 static void end_msc_irq(unsigned int irq
)
111 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
116 * Interrupt handler for interrupts coming from SOC-it.
118 void ll_msc_irq(struct pt_regs
*regs
)
122 /* read the interrupt vector register */
123 MSCIC_READ(MSC01_IC_VEC
, irq
);
125 do_IRQ(irq
+ irq_base
, regs
);
127 /* Ignore spurious interrupt */
132 msc_bind_eic_interrupt (unsigned int irq
, unsigned int set
)
134 MSCIC_WRITE(MSC01_IC_RAMW
,
135 (irq
<<MSC01_IC_RAMW_ADDR_SHF
) | (set
<<MSC01_IC_RAMW_DATA_SHF
));
138 #define shutdown_msc_irq disable_msc_irq
140 struct hw_interrupt_type msc_levelirq_type
= {
141 .typename
= "SOC-it-Level",
142 .startup
= startup_msc_irq
,
143 .shutdown
= shutdown_msc_irq
,
144 .enable
= enable_msc_irq
,
145 .disable
= disable_msc_irq
,
146 .ack
= level_mask_and_ack_msc_irq
,
150 struct hw_interrupt_type msc_edgeirq_type
= {
151 .typename
= "SOC-it-Edge",
152 .startup
=startup_msc_irq
,
153 .shutdown
= shutdown_msc_irq
,
154 .enable
= enable_msc_irq
,
155 .disable
= disable_msc_irq
,
156 .ack
= edge_mask_and_ack_msc_irq
,
161 void __init
init_msc_irqs(unsigned int base
, msc_irqmap_t
*imp
, int nirq
)
163 extern void (*board_bind_eic_interrupt
)(unsigned int irq
, unsigned int regset
);
165 _icctrl_msc
= (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE
, 0x40000);
167 /* Reset interrupt controller - initialises all registers to 0 */
168 MSCIC_WRITE(MSC01_IC_RST
, MSC01_IC_RST_RST_BIT
);
170 board_bind_eic_interrupt
= &msc_bind_eic_interrupt
;
172 for (; nirq
>= 0; nirq
--, imp
++) {
175 switch (imp
->im_type
) {
177 irq_desc
[base
+n
].handler
= &msc_edgeirq_type
;
179 MSCIC_WRITE(MSC01_IC_SUP
+n
*8, MSC01_IC_SUP_EDGE_BIT
);
181 MSCIC_WRITE(MSC01_IC_SUP
+n
*8, MSC01_IC_SUP_EDGE_BIT
| imp
->im_lvl
);
183 case MSC01_IRQ_LEVEL
:
184 irq_desc
[base
+n
].handler
= &msc_levelirq_type
;
186 MSCIC_WRITE(MSC01_IC_SUP
+n
*8, 0);
188 MSCIC_WRITE(MSC01_IC_SUP
+n
*8, imp
->im_lvl
);
194 MSCIC_WRITE(MSC01_IC_GENA
, MSC01_IC_GENA_GENA_BIT
); /* Enable interrupt generation */