2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * SMP support for BMIPS
11 #include <linux/init.h>
12 #include <linux/sched.h>
14 #include <linux/delay.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/spinlock.h>
18 #include <linux/init.h>
19 #include <linux/cpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/reboot.h>
23 #include <linux/compiler.h>
24 #include <linux/linkage.h>
25 #include <linux/bug.h>
26 #include <linux/kernel.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
31 #include <asm/bootinfo.h>
33 #include <asm/cacheflush.h>
34 #include <asm/tlbflush.h>
35 #include <asm/mipsregs.h>
36 #include <asm/bmips.h>
37 #include <asm/traps.h>
38 #include <asm/barrier.h>
40 static int __maybe_unused max_cpus
= 1;
42 /* these may be configured by the platform code */
43 int bmips_smp_enabled
= 1;
45 cpumask_t bmips_booted_mask
;
49 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
50 unsigned long bmips_smp_boot_sp
;
51 unsigned long bmips_smp_boot_gp
;
53 static void bmips_send_ipi_single(int cpu
, unsigned int action
);
54 static irqreturn_t
bmips_ipi_interrupt(int irq
, void *dev_id
);
56 /* SW interrupts 0,1 are used for interprocessor signaling */
57 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
58 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
60 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
61 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
62 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
63 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
65 static void __init
bmips_smp_setup(void)
69 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
70 /* arbitration priority */
71 clear_c0_brcm_cmt_ctrl(0x30);
73 /* NBK and weak order flags */
74 set_c0_brcm_config_0(0x30000);
77 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
78 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
79 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
81 change_c0_brcm_cmt_intr(0xf8018000,
82 (0x02 << 27) | (0x03 << 15));
84 /* single core, 2 threads (2 pipelines) */
86 #elif defined(CONFIG_CPU_BMIPS5000)
87 /* enable raceless SW interrupts */
88 set_c0_brcm_config(0x03 << 22);
90 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
91 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
93 /* N cores, 2 threads per core */
94 max_cpus
= (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
96 /* clear any pending SW interrupts */
97 for (i
= 0; i
< max_cpus
; i
++) {
98 write_c0_brcm_action(ACTION_CLR_IPI(i
, 0));
99 write_c0_brcm_action(ACTION_CLR_IPI(i
, 1));
103 if (!bmips_smp_enabled
)
106 /* this can be overridden by the BSP */
107 if (!board_ebase_setup
)
108 board_ebase_setup
= &bmips_ebase_setup
;
110 for (i
= 0; i
< max_cpus
; i
++) {
111 __cpu_number_map
[i
] = 1;
112 __cpu_logical_map
[i
] = 1;
113 set_cpu_possible(i
, 1);
114 set_cpu_present(i
, 1);
119 * IPI IRQ setup - runs on CPU0
121 static void bmips_prepare_cpus(unsigned int max_cpus
)
123 if (request_irq(IPI0_IRQ
, bmips_ipi_interrupt
, IRQF_PERCPU
,
125 panic("Can't request IPI0 interrupt\n");
126 if (request_irq(IPI1_IRQ
, bmips_ipi_interrupt
, IRQF_PERCPU
,
128 panic("Can't request IPI1 interrupt\n");
132 * Tell the hardware to boot CPUx - runs on CPU0
134 static void bmips_boot_secondary(int cpu
, struct task_struct
*idle
)
136 bmips_smp_boot_sp
= __KSTK_TOS(idle
);
137 bmips_smp_boot_gp
= (unsigned long)task_thread_info(idle
);
141 * Initial boot sequence for secondary CPU:
142 * bmips_reset_nmi_vec @ a000_0000 ->
144 * plat_wired_tlb_setup (cached function call; optional) ->
145 * start_secondary (cached jump)
147 * Warm restart sequence:
148 * play_dead WAIT loop ->
149 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
150 * eret to play_dead ->
151 * bmips_secondary_reentry ->
155 pr_info("SMP: Booting CPU%d...\n", cpu
);
157 if (cpumask_test_cpu(cpu
, &bmips_booted_mask
))
158 bmips_send_ipi_single(cpu
, 0);
160 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
161 set_c0_brcm_cmt_ctrl(0x01);
162 #elif defined(CONFIG_CPU_BMIPS5000)
164 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu
));
167 * core N thread 0 was already booted; just
170 bmips_write_zscm_reg(0x210, 0xc0000000);
172 bmips_write_zscm_reg(0x210, 0x00);
175 cpumask_set_cpu(cpu
, &bmips_booted_mask
);
180 * Early setup - runs on secondary CPU after cache probe
182 static void bmips_init_secondary(void)
184 /* move NMI vector to kseg0, in case XKS01 is enabled */
186 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
187 void __iomem
*cbr
= BMIPS_GET_CBR();
188 unsigned long old_vec
;
190 old_vec
= __raw_readl(cbr
+ BMIPS_RELO_VECTOR_CONTROL_1
);
191 __raw_writel(old_vec
& ~0x20000000, cbr
+ BMIPS_RELO_VECTOR_CONTROL_1
);
193 clear_c0_cause(smp_processor_id() ? C_SW1
: C_SW0
);
194 #elif defined(CONFIG_CPU_BMIPS5000)
195 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
196 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
198 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
201 /* make sure there won't be a timer interrupt for a little while */
202 write_c0_compare(read_c0_count() + mips_hpt_frequency
/ HZ
);
205 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ1
| IE_IRQ5
| ST0_IE
);
210 * Late setup - runs on secondary CPU before entering the idle loop
212 static void bmips_smp_finish(void)
214 pr_info("SMP: CPU%d is running\n", smp_processor_id());
218 * Runs on CPU0 after all CPUs have been booted
220 static void bmips_cpus_done(void)
224 #if defined(CONFIG_CPU_BMIPS5000)
227 * BMIPS5000 raceless IPIs
229 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
230 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
231 * IPI1 is used for SMP_CALL_FUNCTION
234 static void bmips_send_ipi_single(int cpu
, unsigned int action
)
236 write_c0_brcm_action(ACTION_SET_IPI(cpu
, action
== SMP_CALL_FUNCTION
));
239 static irqreturn_t
bmips_ipi_interrupt(int irq
, void *dev_id
)
241 int action
= irq
- IPI0_IRQ
;
243 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action
));
248 smp_call_function_interrupt();
256 * BMIPS43xx racey IPIs
258 * We use one inbound SW IRQ for each CPU.
260 * A spinlock must be held in order to keep CPUx from accidentally clearing
261 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
262 * same spinlock is used to protect the action masks.
265 static DEFINE_SPINLOCK(ipi_lock
);
266 static DEFINE_PER_CPU(int, ipi_action_mask
);
268 static void bmips_send_ipi_single(int cpu
, unsigned int action
)
272 spin_lock_irqsave(&ipi_lock
, flags
);
273 set_c0_cause(cpu
? C_SW1
: C_SW0
);
274 per_cpu(ipi_action_mask
, cpu
) |= action
;
276 spin_unlock_irqrestore(&ipi_lock
, flags
);
279 static irqreturn_t
bmips_ipi_interrupt(int irq
, void *dev_id
)
282 int action
, cpu
= irq
- IPI0_IRQ
;
284 spin_lock_irqsave(&ipi_lock
, flags
);
285 action
= __get_cpu_var(ipi_action_mask
);
286 per_cpu(ipi_action_mask
, cpu
) = 0;
287 clear_c0_cause(cpu
? C_SW1
: C_SW0
);
288 spin_unlock_irqrestore(&ipi_lock
, flags
);
290 if (action
& SMP_RESCHEDULE_YOURSELF
)
292 if (action
& SMP_CALL_FUNCTION
)
293 smp_call_function_interrupt();
298 #endif /* BMIPS type */
300 static void bmips_send_ipi_mask(const struct cpumask
*mask
,
305 for_each_cpu(i
, mask
)
306 bmips_send_ipi_single(i
, action
);
309 #ifdef CONFIG_HOTPLUG_CPU
311 static int bmips_cpu_disable(void)
313 unsigned int cpu
= smp_processor_id();
318 pr_info("SMP: CPU%d is offline\n", cpu
);
320 set_cpu_online(cpu
, false);
321 cpu_clear(cpu
, cpu_callin_map
);
323 local_flush_tlb_all();
324 local_flush_icache_range(0, ~0);
329 static void bmips_cpu_die(unsigned int cpu
)
333 void __ref
play_dead(void)
337 /* flush data cache */
338 _dma_cache_wback_inv(0, ~0);
341 * Wakeup is on SW0 or SW1; disable everything else
342 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
343 * IRQ handlers; this clears ST0_IE and returns immediately.
345 clear_c0_cause(CAUSEF_IV
| C_SW0
| C_SW1
);
346 change_c0_status(IE_IRQ5
| IE_IRQ1
| IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
,
347 IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
);
348 irq_disable_hazard();
351 * wait for SW interrupt from bmips_boot_secondary(), then jump
352 * back to start_secondary()
354 __asm__
__volatile__(
356 " j bmips_secondary_reentry\n"
360 #endif /* CONFIG_HOTPLUG_CPU */
362 struct plat_smp_ops bmips_smp_ops
= {
363 .smp_setup
= bmips_smp_setup
,
364 .prepare_cpus
= bmips_prepare_cpus
,
365 .boot_secondary
= bmips_boot_secondary
,
366 .smp_finish
= bmips_smp_finish
,
367 .init_secondary
= bmips_init_secondary
,
368 .cpus_done
= bmips_cpus_done
,
369 .send_ipi_single
= bmips_send_ipi_single
,
370 .send_ipi_mask
= bmips_send_ipi_mask
,
371 #ifdef CONFIG_HOTPLUG_CPU
372 .cpu_disable
= bmips_cpu_disable
,
373 .cpu_die
= bmips_cpu_die
,
377 #endif /* CONFIG_SMP */
379 /***********************************************************************
380 * BMIPS vector relocation
381 * This is primarily used for SMP boot, but it is applicable to some
382 * UP BMIPS systems as well.
383 ***********************************************************************/
385 static void __cpuinit
bmips_wr_vec(unsigned long dst
, char *start
, char *end
)
387 memcpy((void *)dst
, start
, end
- start
);
388 dma_cache_wback((unsigned long)start
, end
- start
);
389 local_flush_icache_range(dst
, dst
+ (end
- start
));
390 instruction_hazard();
393 static inline void __cpuinit
bmips_nmi_handler_setup(void)
395 bmips_wr_vec(BMIPS_NMI_RESET_VEC
, &bmips_reset_nmi_vec
,
396 &bmips_reset_nmi_vec_end
);
397 bmips_wr_vec(BMIPS_WARM_RESTART_VEC
, &bmips_smp_int_vec
,
398 &bmips_smp_int_vec_end
);
401 void __cpuinit
bmips_ebase_setup(void)
403 unsigned long new_ebase
= ebase
;
404 void __iomem __maybe_unused
*cbr
;
406 BUG_ON(ebase
!= CKSEG0
);
408 #if defined(CONFIG_CPU_BMIPS4350)
410 * BMIPS4350 cannot relocate the normal vectors, but it
411 * can relocate the BEV=1 vectors. So CPU1 starts up at
412 * the relocated BEV=1, IV=0 general exception vector @
415 * set_uncached_handler() is used here because:
416 * - CPU1 will run this from uncached space
417 * - None of the cacheflush functions are set up yet
419 set_uncached_handler(BMIPS_WARM_RESTART_VEC
- CKSEG0
,
420 &bmips_smp_int_vec
, 0x80);
423 #elif defined(CONFIG_CPU_BMIPS4380)
425 * 0x8000_0000: reset/NMI (initially in kseg1)
426 * 0x8000_0400: normal vectors
428 new_ebase
= 0x80000400;
429 cbr
= BMIPS_GET_CBR();
430 __raw_writel(0x80080800, cbr
+ BMIPS_RELO_VECTOR_CONTROL_0
);
431 __raw_writel(0xa0080800, cbr
+ BMIPS_RELO_VECTOR_CONTROL_1
);
432 #elif defined(CONFIG_CPU_BMIPS5000)
434 * 0x8000_0000: reset/NMI (initially in kseg1)
435 * 0x8000_1000: normal vectors
437 new_ebase
= 0x80001000;
438 write_c0_brcm_bootvec(0xa0088008);
439 write_c0_ebase(new_ebase
);
441 bmips_write_zscm_reg(0xa0, 0xa008a008);
445 board_nmi_handler_setup
= &bmips_nmi_handler_setup
;
449 asmlinkage
void __weak
plat_wired_tlb_setup(void)
452 * Called when starting/restarting a secondary CPU.
453 * Kernel stacks and other important data might only be accessible
454 * once the wired entries are present.