2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
45 extern asmlinkage
void handle_int(void);
46 extern asmlinkage
void handle_tlbm(void);
47 extern asmlinkage
void handle_tlbl(void);
48 extern asmlinkage
void handle_tlbs(void);
49 extern asmlinkage
void handle_adel(void);
50 extern asmlinkage
void handle_ades(void);
51 extern asmlinkage
void handle_ibe(void);
52 extern asmlinkage
void handle_dbe(void);
53 extern asmlinkage
void handle_sys(void);
54 extern asmlinkage
void handle_bp(void);
55 extern asmlinkage
void handle_ri(void);
56 extern asmlinkage
void handle_cpu(void);
57 extern asmlinkage
void handle_ov(void);
58 extern asmlinkage
void handle_tr(void);
59 extern asmlinkage
void handle_fpe(void);
60 extern asmlinkage
void handle_mdmx(void);
61 extern asmlinkage
void handle_watch(void);
62 extern asmlinkage
void handle_mt(void);
63 extern asmlinkage
void handle_dsp(void);
64 extern asmlinkage
void handle_mcheck(void);
65 extern asmlinkage
void handle_reserved(void);
67 extern int fpu_emulator_cop1Handler(struct pt_regs
*xcp
,
68 struct mips_fpu_soft_struct
*ctx
);
70 void (*board_be_init
)(void);
71 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
72 void (*board_nmi_handler_setup
)(void);
73 void (*board_ejtag_handler_setup
)(void);
74 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
77 * These constant is for searching for possible module text segments.
78 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
80 #define MODULE_RANGE (8*1024*1024)
83 * This routine abuses get_user()/put_user() to reference pointers
84 * with at least a bit of error checking ...
86 void show_stack(struct task_struct
*task
, unsigned long *sp
)
88 const int field
= 2 * sizeof(unsigned long);
93 if (task
&& task
!= current
)
94 sp
= (unsigned long *) task
->thread
.reg29
;
96 sp
= (unsigned long *) &sp
;
101 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
102 if (i
&& ((i
% (64 / field
)) == 0))
109 if (__get_user(stackdata
, sp
++)) {
110 printk(" (Bad stack address)");
114 printk(" %0*lx", field
, stackdata
);
120 void show_trace(struct task_struct
*task
, unsigned long *stack
)
122 const int field
= 2 * sizeof(unsigned long);
126 if (task
&& task
!= current
)
127 stack
= (unsigned long *) task
->thread
.reg29
;
129 stack
= (unsigned long *) &stack
;
132 printk("Call Trace:");
133 #ifdef CONFIG_KALLSYMS
136 while (!kstack_end(stack
)) {
138 if (__kernel_text_address(addr
)) {
139 printk(" [<%0*lx>] ", field
, addr
);
140 print_symbol("%s\n", addr
);
147 * The architecture-independent dump_stack generator
149 void dump_stack(void)
153 show_trace(current
, &stack
);
156 EXPORT_SYMBOL(dump_stack
);
158 void show_code(unsigned int *pc
)
164 for(i
= -3 ; i
< 6 ; i
++) {
166 if (__get_user(insn
, pc
+ i
)) {
167 printk(" (Bad address in epc)\n");
170 printk("%c%08x%c", (i
?' ':'<'), insn
, (i
?' ':'>'));
174 void show_regs(struct pt_regs
*regs
)
176 const int field
= 2 * sizeof(unsigned long);
177 unsigned int cause
= regs
->cp0_cause
;
180 printk("Cpu %d\n", smp_processor_id());
183 * Saved main processor registers
185 for (i
= 0; i
< 32; ) {
189 printk(" %0*lx", field
, 0UL);
190 else if (i
== 26 || i
== 27)
191 printk(" %*s", field
, "");
193 printk(" %0*lx", field
, regs
->regs
[i
]);
200 printk("Hi : %0*lx\n", field
, regs
->hi
);
201 printk("Lo : %0*lx\n", field
, regs
->lo
);
204 * Saved cp0 registers
206 printk("epc : %0*lx ", field
, regs
->cp0_epc
);
207 print_symbol("%s ", regs
->cp0_epc
);
208 printk(" %s\n", print_tainted());
209 printk("ra : %0*lx ", field
, regs
->regs
[31]);
210 print_symbol("%s\n", regs
->regs
[31]);
212 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
214 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_I
) {
215 if (regs
->cp0_status
& ST0_KUO
)
217 if (regs
->cp0_status
& ST0_IEO
)
219 if (regs
->cp0_status
& ST0_KUP
)
221 if (regs
->cp0_status
& ST0_IEP
)
223 if (regs
->cp0_status
& ST0_KUC
)
225 if (regs
->cp0_status
& ST0_IEC
)
228 if (regs
->cp0_status
& ST0_KX
)
230 if (regs
->cp0_status
& ST0_SX
)
232 if (regs
->cp0_status
& ST0_UX
)
234 switch (regs
->cp0_status
& ST0_KSU
) {
239 printk("SUPERVISOR ");
248 if (regs
->cp0_status
& ST0_ERL
)
250 if (regs
->cp0_status
& ST0_EXL
)
252 if (regs
->cp0_status
& ST0_IE
)
257 printk("Cause : %08x\n", cause
);
259 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
260 if (1 <= cause
&& cause
<= 5)
261 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
263 printk("PrId : %08x\n", read_c0_prid());
266 void show_registers(struct pt_regs
*regs
)
270 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
271 current
->comm
, current
->pid
, current_thread_info(), current
);
272 show_stack(current
, (long *) regs
->regs
[29]);
273 show_trace(current
, (long *) regs
->regs
[29]);
274 show_code((unsigned int *) regs
->cp0_epc
);
278 static DEFINE_SPINLOCK(die_lock
);
280 NORET_TYPE
void ATTRIB_NORET
die(const char * str
, struct pt_regs
* regs
)
282 static int die_counter
;
285 spin_lock_irq(&die_lock
);
286 printk("%s[#%d]:\n", str
, ++die_counter
);
287 show_registers(regs
);
288 spin_unlock_irq(&die_lock
);
292 extern const struct exception_table_entry __start___dbe_table
[];
293 extern const struct exception_table_entry __stop___dbe_table
[];
295 void __declare_dbe_table(void)
297 __asm__
__volatile__(
298 ".section\t__dbe_table,\"a\"\n\t"
303 /* Given an address, look for it in the exception tables. */
304 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
306 const struct exception_table_entry
*e
;
308 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
310 e
= search_module_dbetables(addr
);
314 asmlinkage
void do_be(struct pt_regs
*regs
)
316 const int field
= 2 * sizeof(unsigned long);
317 const struct exception_table_entry
*fixup
= NULL
;
318 int data
= regs
->cp0_cause
& 4;
319 int action
= MIPS_BE_FATAL
;
321 /* XXX For now. Fixme, this searches the wrong table ... */
322 if (data
&& !user_mode(regs
))
323 fixup
= search_dbe_tables(exception_epc(regs
));
326 action
= MIPS_BE_FIXUP
;
328 if (board_be_handler
)
329 action
= board_be_handler(regs
, fixup
!= 0);
332 case MIPS_BE_DISCARD
:
336 regs
->cp0_epc
= fixup
->nextinsn
;
345 * Assume it would be too dangerous to continue ...
347 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
348 data
? "Data" : "Instruction",
349 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
350 die_if_kernel("Oops", regs
);
351 force_sig(SIGBUS
, current
);
354 static inline int get_insn_opcode(struct pt_regs
*regs
, unsigned int *opcode
)
356 unsigned int __user
*epc
;
358 epc
= (unsigned int __user
*) regs
->cp0_epc
+
359 ((regs
->cp0_cause
& CAUSEF_BD
) != 0);
360 if (!get_user(*opcode
, epc
))
363 force_sig(SIGSEGV
, current
);
371 #define OPCODE 0xfc000000
372 #define BASE 0x03e00000
373 #define RT 0x001f0000
374 #define OFFSET 0x0000ffff
375 #define LL 0xc0000000
376 #define SC 0xe0000000
377 #define SPEC3 0x7c000000
378 #define RD 0x0000f800
379 #define FUNC 0x0000003f
380 #define RDHWR 0x0000003b
383 * The ll_bit is cleared by r*_switch.S
386 unsigned long ll_bit
;
388 static struct task_struct
*ll_task
= NULL
;
390 static inline void simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
392 unsigned long value
, __user
*vaddr
;
397 * analyse the ll instruction that just caused a ri exception
398 * and put the referenced address to addr.
401 /* sign extend offset */
402 offset
= opcode
& OFFSET
;
406 vaddr
= (unsigned long __user
*)
407 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
409 if ((unsigned long)vaddr
& 3) {
413 if (get_user(value
, vaddr
)) {
420 if (ll_task
== NULL
|| ll_task
== current
) {
429 compute_return_epc(regs
);
431 regs
->regs
[(opcode
& RT
) >> 16] = value
;
436 force_sig(signal
, current
);
439 static inline void simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
441 unsigned long __user
*vaddr
;
447 * analyse the sc instruction that just caused a ri exception
448 * and put the referenced address to addr.
451 /* sign extend offset */
452 offset
= opcode
& OFFSET
;
456 vaddr
= (unsigned long __user
*)
457 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
458 reg
= (opcode
& RT
) >> 16;
460 if ((unsigned long)vaddr
& 3) {
467 if (ll_bit
== 0 || ll_task
!= current
) {
468 compute_return_epc(regs
);
476 if (put_user(regs
->regs
[reg
], vaddr
)) {
481 compute_return_epc(regs
);
487 force_sig(signal
, current
);
491 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
492 * opcodes are supposed to result in coprocessor unusable exceptions if
493 * executed on ll/sc-less processors. That's the theory. In practice a
494 * few processors such as NEC's VR4100 throw reserved instruction exceptions
495 * instead, so we're doing the emulation thing in both exception handlers.
497 static inline int simulate_llsc(struct pt_regs
*regs
)
501 if (unlikely(get_insn_opcode(regs
, &opcode
)))
504 if ((opcode
& OPCODE
) == LL
) {
505 simulate_ll(regs
, opcode
);
508 if ((opcode
& OPCODE
) == SC
) {
509 simulate_sc(regs
, opcode
);
513 return -EFAULT
; /* Strange things going on ... */
517 * Simulate trapping 'rdhwr' instructions to provide user accessible
518 * registers not implemented in hardware. The only current use of this
519 * is the thread area pointer.
521 static inline int simulate_rdhwr(struct pt_regs
*regs
)
523 struct thread_info
*ti
= task_thread_info(current
);
526 if (unlikely(get_insn_opcode(regs
, &opcode
)))
529 if (unlikely(compute_return_epc(regs
)))
532 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
533 int rd
= (opcode
& RD
) >> 11;
534 int rt
= (opcode
& RT
) >> 16;
537 regs
->regs
[rt
] = ti
->tp_value
;
548 asmlinkage
void do_ov(struct pt_regs
*regs
)
552 die_if_kernel("Integer overflow", regs
);
554 info
.si_code
= FPE_INTOVF
;
555 info
.si_signo
= SIGFPE
;
557 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
558 force_sig_info(SIGFPE
, &info
, current
);
562 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
564 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
566 if (fcr31
& FPU_CSR_UNI_X
) {
571 #ifdef CONFIG_PREEMPT
572 if (!is_fpu_owner()) {
573 /* We might lose fpu before disabling preempt... */
575 BUG_ON(!used_math());
580 * Unimplemented operation exception. If we've got the full
581 * software emulator on-board, let's use it...
583 * Force FPU to dump state into task/thread context. We're
584 * moving a lot of data here for what is probably a single
585 * instruction, but the alternative is to pre-decode the FP
586 * register operands before invoking the emulator, which seems
587 * a bit extreme for what should be an infrequent event.
590 /* Ensure 'resume' not overwrite saved fp context again. */
595 /* Run the emulator */
596 sig
= fpu_emulator_cop1Handler (regs
,
597 ¤t
->thread
.fpu
.soft
);
601 own_fpu(); /* Using the FPU again. */
603 * We can't allow the emulated instruction to leave any of
604 * the cause bit set in $fcr31.
606 current
->thread
.fpu
.soft
.fcr31
&= ~FPU_CSR_ALL_X
;
608 /* Restore the hardware register state */
613 /* If something went wrong, signal */
615 force_sig(sig
, current
);
620 force_sig(SIGFPE
, current
);
623 asmlinkage
void do_bp(struct pt_regs
*regs
)
625 unsigned int opcode
, bcode
;
628 die_if_kernel("Break instruction in kernel code", regs
);
630 if (get_insn_opcode(regs
, &opcode
))
634 * There is the ancient bug in the MIPS assemblers that the break
635 * code starts left to bit 16 instead to bit 6 in the opcode.
636 * Gas is bug-compatible, but not always, grrr...
637 * We handle both cases with a simple heuristics. --macro
639 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
640 if (bcode
< (1 << 10))
644 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
645 * insns, even for break codes that indicate arithmetic failures.
647 * But should we continue the brokenness??? --macro
650 case BRK_OVERFLOW
<< 10:
651 case BRK_DIVZERO
<< 10:
652 if (bcode
== (BRK_DIVZERO
<< 10))
653 info
.si_code
= FPE_INTDIV
;
655 info
.si_code
= FPE_INTOVF
;
656 info
.si_signo
= SIGFPE
;
658 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
659 force_sig_info(SIGFPE
, &info
, current
);
662 force_sig(SIGTRAP
, current
);
666 asmlinkage
void do_tr(struct pt_regs
*regs
)
668 unsigned int opcode
, tcode
= 0;
671 die_if_kernel("Trap instruction in kernel code", regs
);
673 if (get_insn_opcode(regs
, &opcode
))
676 /* Immediate versions don't provide a code. */
677 if (!(opcode
& OPCODE
))
678 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
681 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
682 * insns, even for trap codes that indicate arithmetic failures.
684 * But should we continue the brokenness??? --macro
689 if (tcode
== BRK_DIVZERO
)
690 info
.si_code
= FPE_INTDIV
;
692 info
.si_code
= FPE_INTOVF
;
693 info
.si_signo
= SIGFPE
;
695 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
696 force_sig_info(SIGFPE
, &info
, current
);
699 force_sig(SIGTRAP
, current
);
703 asmlinkage
void do_ri(struct pt_regs
*regs
)
705 die_if_kernel("Reserved instruction in kernel code", regs
);
708 if (!simulate_llsc(regs
))
711 if (!simulate_rdhwr(regs
))
714 force_sig(SIGILL
, current
);
717 asmlinkage
void do_cpu(struct pt_regs
*regs
)
721 die_if_kernel("do_cpu invoked from kernel context!", regs
);
723 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
728 if (!simulate_llsc(regs
))
731 if (!simulate_rdhwr(regs
))
740 if (used_math()) { /* Using the FPU again. */
742 } else { /* First time FPU user. */
750 int sig
= fpu_emulator_cop1Handler(regs
,
751 ¤t
->thread
.fpu
.soft
);
753 force_sig(sig
, current
);
763 force_sig(SIGILL
, current
);
766 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
768 force_sig(SIGILL
, current
);
771 asmlinkage
void do_watch(struct pt_regs
*regs
)
774 * We use the watch exception where available to detect stack
779 panic("Caught WATCH exception - probably caused by stack overflow.");
782 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
787 * Some chips may have other causes of machine check (e.g. SB1
790 panic("Caught Machine Check exception - %scaused by multiple "
791 "matching entries in the TLB.",
792 (regs
->cp0_status
& ST0_TS
) ? "" : "not ");
795 asmlinkage
void do_mt(struct pt_regs
*regs
)
797 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
799 force_sig(SIGILL
, current
);
803 asmlinkage
void do_dsp(struct pt_regs
*regs
)
806 panic("Unexpected DSP exception\n");
808 force_sig(SIGILL
, current
);
811 asmlinkage
void do_reserved(struct pt_regs
*regs
)
814 * Game over - no way to handle this if it ever occurs. Most probably
815 * caused by a new unknown cpu type or after another deadly
816 * hard/software error.
819 panic("Caught reserved exception %ld - should not happen.",
820 (regs
->cp0_cause
& 0x7f) >> 2);
823 asmlinkage
void do_default_vi(struct pt_regs
*regs
)
826 panic("Caught unexpected vectored interrupt.");
830 * Some MIPS CPUs can enable/disable for cache parity detection, but do
833 static inline void parity_protection_init(void)
835 switch (current_cpu_data
.cputype
) {
838 write_c0_ecc(0x80000000);
839 back_to_back_c0_hazard();
840 /* Set the PE bit (bit 31) in the c0_errctl register. */
841 printk(KERN_INFO
"Cache parity protection %sabled\n",
842 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
846 /* Clear the DE bit (bit 16) in the c0_status register. */
847 printk(KERN_INFO
"Enable cache parity protection for "
848 "MIPS 20KC/25KF CPUs.\n");
849 clear_c0_status(ST0_DE
);
856 asmlinkage
void cache_parity_error(void)
858 const int field
= 2 * sizeof(unsigned long);
859 unsigned int reg_val
;
861 /* For the moment, report the problem and hang. */
862 printk("Cache error exception:\n");
863 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
864 reg_val
= read_c0_cacheerr();
865 printk("c0_cacheerr == %08x\n", reg_val
);
867 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
868 reg_val
& (1<<30) ? "secondary" : "primary",
869 reg_val
& (1<<31) ? "data" : "insn");
870 printk("Error bits: %s%s%s%s%s%s%s\n",
871 reg_val
& (1<<29) ? "ED " : "",
872 reg_val
& (1<<28) ? "ET " : "",
873 reg_val
& (1<<26) ? "EE " : "",
874 reg_val
& (1<<25) ? "EB " : "",
875 reg_val
& (1<<24) ? "EI " : "",
876 reg_val
& (1<<23) ? "E1 " : "",
877 reg_val
& (1<<22) ? "E0 " : "");
878 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
880 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
881 if (reg_val
& (1<<22))
882 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
884 if (reg_val
& (1<<23))
885 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
888 panic("Can't handle the cache error!");
892 * SDBBP EJTAG debug exception handler.
893 * We skip the instruction and return to the next instruction.
895 void ejtag_exception_handler(struct pt_regs
*regs
)
897 const int field
= 2 * sizeof(unsigned long);
898 unsigned long depc
, old_epc
;
901 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
902 depc
= read_c0_depc();
903 debug
= read_c0_debug();
904 printk("c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
905 if (debug
& 0x80000000) {
907 * In branch delay slot.
908 * We cheat a little bit here and use EPC to calculate the
909 * debug return address (DEPC). EPC is restored after the
912 old_epc
= regs
->cp0_epc
;
913 regs
->cp0_epc
= depc
;
914 __compute_return_epc(regs
);
915 depc
= regs
->cp0_epc
;
916 regs
->cp0_epc
= old_epc
;
922 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
923 write_c0_debug(debug
| 0x100);
928 * NMI exception handler.
930 void nmi_exception_handler(struct pt_regs
*regs
)
932 printk("NMI taken!!!!\n");
937 #define VECTORSPACING 0x100 /* for EI/VI mode */
940 unsigned long exception_handlers
[32];
941 unsigned long vi_handlers
[64];
944 * As a side effect of the way this is implemented we're limited
945 * to interrupt handlers in the address range from
946 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
948 void *set_except_vector(int n
, void *addr
)
950 unsigned long handler
= (unsigned long) addr
;
951 unsigned long old_handler
= exception_handlers
[n
];
953 exception_handlers
[n
] = handler
;
954 if (n
== 0 && cpu_has_divec
) {
955 *(volatile u32
*)(ebase
+ 0x200) = 0x08000000 |
956 (0x03ffffff & (handler
>> 2));
957 flush_icache_range(ebase
+ 0x200, ebase
+ 0x204);
959 return (void *)old_handler
;
962 #ifdef CONFIG_CPU_MIPSR2
964 * MIPSR2 shadow register set allocation
968 static struct shadow_registers
{
970 * Number of shadow register sets supported
972 unsigned long sr_supported
;
974 * Bitmap of allocated shadow registers
976 unsigned long sr_allocated
;
979 void mips_srs_init(void)
981 #ifdef CONFIG_CPU_MIPSR2_SRS
982 shadow_registers
.sr_supported
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
983 printk(KERN_INFO
"%d MIPSR2 register sets available\n",
984 shadow_registers
.sr_supported
);
986 shadow_registers
.sr_allocated
= 1; /* Set 0 used by kernel */
989 int mips_srs_max(void)
991 return shadow_registers
.sr_supported
;
994 int mips_srs_alloc(void)
996 struct shadow_registers
*sr
= &shadow_registers
;
1000 set
= find_first_zero_bit(&sr
->sr_allocated
, sr
->sr_supported
);
1001 if (set
>= sr
->sr_supported
)
1004 if (test_and_set_bit(set
, &sr
->sr_allocated
))
1010 void mips_srs_free (int set
)
1012 struct shadow_registers
*sr
= &shadow_registers
;
1014 clear_bit(set
, &sr
->sr_allocated
);
1017 static void *set_vi_srs_handler(int n
, void *addr
, int srs
)
1019 unsigned long handler
;
1020 unsigned long old_handler
= vi_handlers
[n
];
1024 if (!cpu_has_veic
&& !cpu_has_vint
)
1028 handler
= (unsigned long) do_default_vi
;
1032 handler
= (unsigned long) addr
;
1033 vi_handlers
[n
] = (unsigned long) addr
;
1035 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1037 if (srs
>= mips_srs_max())
1038 panic("Shadow register set %d not supported", srs
);
1041 if (board_bind_eic_interrupt
)
1042 board_bind_eic_interrupt (n
, srs
);
1044 else if (cpu_has_vint
) {
1045 /* SRSMap is only defined if shadow sets are implemented */
1046 if (mips_srs_max() > 1)
1047 change_c0_srsmap (0xf << n
*4, srs
<< n
*4);
1052 * If no shadow set is selected then use the default handler
1053 * that does normal register saving and a standard interrupt exit
1056 extern char except_vec_vi
, except_vec_vi_lui
;
1057 extern char except_vec_vi_ori
, except_vec_vi_end
;
1058 const int handler_len
= &except_vec_vi_end
- &except_vec_vi
;
1059 const int lui_offset
= &except_vec_vi_lui
- &except_vec_vi
;
1060 const int ori_offset
= &except_vec_vi_ori
- &except_vec_vi
;
1062 if (handler_len
> VECTORSPACING
) {
1064 * Sigh... panicing won't help as the console
1065 * is probably not configured :(
1067 panic ("VECTORSPACING too small");
1070 memcpy (b
, &except_vec_vi
, handler_len
);
1071 w
= (u32
*)(b
+ lui_offset
);
1072 *w
= (*w
& 0xffff0000) | (((u32
)handler
>> 16) & 0xffff);
1073 w
= (u32
*)(b
+ ori_offset
);
1074 *w
= (*w
& 0xffff0000) | ((u32
)handler
& 0xffff);
1075 flush_icache_range((unsigned long)b
, (unsigned long)(b
+handler_len
));
1079 * In other cases jump directly to the interrupt handler
1081 * It is the handlers responsibility to save registers if required
1082 * (eg hi/lo) and return from the exception using "eret"
1085 *w
++ = 0x08000000 | (((u32
)handler
>> 2) & 0x03fffff); /* j handler */
1087 flush_icache_range((unsigned long)b
, (unsigned long)(b
+8));
1090 return (void *)old_handler
;
1093 void *set_vi_handler (int n
, void *addr
)
1095 return set_vi_srs_handler(n
, addr
, 0);
1100 * This is used by native signal handling
1102 asmlinkage
int (*save_fp_context
)(struct sigcontext
*sc
);
1103 asmlinkage
int (*restore_fp_context
)(struct sigcontext
*sc
);
1105 extern asmlinkage
int _save_fp_context(struct sigcontext
*sc
);
1106 extern asmlinkage
int _restore_fp_context(struct sigcontext
*sc
);
1108 extern asmlinkage
int fpu_emulator_save_context(struct sigcontext
*sc
);
1109 extern asmlinkage
int fpu_emulator_restore_context(struct sigcontext
*sc
);
1111 static inline void signal_init(void)
1114 save_fp_context
= _save_fp_context
;
1115 restore_fp_context
= _restore_fp_context
;
1117 save_fp_context
= fpu_emulator_save_context
;
1118 restore_fp_context
= fpu_emulator_restore_context
;
1122 #ifdef CONFIG_MIPS32_COMPAT
1125 * This is used by 32-bit signal stuff on the 64-bit kernel
1127 asmlinkage
int (*save_fp_context32
)(struct sigcontext32
*sc
);
1128 asmlinkage
int (*restore_fp_context32
)(struct sigcontext32
*sc
);
1130 extern asmlinkage
int _save_fp_context32(struct sigcontext32
*sc
);
1131 extern asmlinkage
int _restore_fp_context32(struct sigcontext32
*sc
);
1133 extern asmlinkage
int fpu_emulator_save_context32(struct sigcontext32
*sc
);
1134 extern asmlinkage
int fpu_emulator_restore_context32(struct sigcontext32
*sc
);
1136 static inline void signal32_init(void)
1139 save_fp_context32
= _save_fp_context32
;
1140 restore_fp_context32
= _restore_fp_context32
;
1142 save_fp_context32
= fpu_emulator_save_context32
;
1143 restore_fp_context32
= fpu_emulator_restore_context32
;
1148 extern void cpu_cache_init(void);
1149 extern void tlb_init(void);
1150 extern void flush_tlb_handlers(void);
1152 void __init
per_cpu_trap_init(void)
1154 unsigned int cpu
= smp_processor_id();
1155 unsigned int status_set
= ST0_CU0
;
1158 * Disable coprocessors and select 32-bit or 64-bit addressing
1159 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1160 * flag that some firmware may have left set and the TS bit (for
1161 * IP27). Set XX for ISA IV code to work.
1164 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1166 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_IV
)
1167 status_set
|= ST0_XX
;
1168 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1172 set_c0_status(ST0_MX
);
1174 #ifdef CONFIG_CPU_MIPSR2
1175 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1179 * Interrupt handling.
1181 if (cpu_has_veic
|| cpu_has_vint
) {
1182 write_c0_ebase (ebase
);
1183 /* Setting vector spacing enables EI/VI mode */
1184 change_c0_intctl (0x3e0, VECTORSPACING
);
1186 if (cpu_has_divec
) {
1187 if (cpu_has_mipsmt
) {
1188 unsigned int vpflags
= dvpe();
1189 set_c0_cause(CAUSEF_IV
);
1192 set_c0_cause(CAUSEF_IV
);
1195 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1196 TLBMISS_HANDLER_SETUP();
1198 atomic_inc(&init_mm
.mm_count
);
1199 current
->active_mm
= &init_mm
;
1200 BUG_ON(current
->mm
);
1201 enter_lazy_tlb(&init_mm
, current
);
1207 /* Install CPU exception handler */
1208 void __init
set_handler (unsigned long offset
, void *addr
, unsigned long size
)
1210 memcpy((void *)(ebase
+ offset
), addr
, size
);
1211 flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1214 /* Install uncached CPU exception handler */
1215 void __init
set_uncached_handler (unsigned long offset
, void *addr
, unsigned long size
)
1218 unsigned long uncached_ebase
= KSEG1ADDR(ebase
);
1221 unsigned long uncached_ebase
= TO_UNCAC(ebase
);
1224 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1227 void __init
trap_init(void)
1229 extern char except_vec3_generic
, except_vec3_r4000
;
1230 extern char except_vec4
;
1233 if (cpu_has_veic
|| cpu_has_vint
)
1234 ebase
= (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING
*64);
1238 #ifdef CONFIG_CPU_MIPSR2
1242 per_cpu_trap_init();
1245 * Copy the generic exception handlers to their final destination.
1246 * This will be overriden later as suitable for a particular
1249 set_handler(0x180, &except_vec3_generic
, 0x80);
1252 * Setup default vectors
1254 for (i
= 0; i
<= 31; i
++)
1255 set_except_vector(i
, handle_reserved
);
1258 * Copy the EJTAG debug exception vector handler code to it's final
1261 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
1262 board_ejtag_handler_setup ();
1265 * Only some CPUs have the watch exceptions.
1268 set_except_vector(23, handle_watch
);
1271 * Initialise interrupt handlers
1273 if (cpu_has_veic
|| cpu_has_vint
) {
1274 int nvec
= cpu_has_veic
? 64 : 8;
1275 for (i
= 0; i
< nvec
; i
++)
1276 set_vi_handler(i
, NULL
);
1278 else if (cpu_has_divec
)
1279 set_handler(0x200, &except_vec4
, 0x8);
1282 * Some CPUs can enable/disable for cache parity detection, but does
1283 * it different ways.
1285 parity_protection_init();
1288 * The Data Bus Errors / Instruction Bus Errors are signaled
1289 * by external hardware. Therefore these two exceptions
1290 * may have board specific handlers.
1295 set_except_vector(0, handle_int
);
1296 set_except_vector(1, handle_tlbm
);
1297 set_except_vector(2, handle_tlbl
);
1298 set_except_vector(3, handle_tlbs
);
1300 set_except_vector(4, handle_adel
);
1301 set_except_vector(5, handle_ades
);
1303 set_except_vector(6, handle_ibe
);
1304 set_except_vector(7, handle_dbe
);
1306 set_except_vector(8, handle_sys
);
1307 set_except_vector(9, handle_bp
);
1308 set_except_vector(10, handle_ri
);
1309 set_except_vector(11, handle_cpu
);
1310 set_except_vector(12, handle_ov
);
1311 set_except_vector(13, handle_tr
);
1313 if (current_cpu_data
.cputype
== CPU_R6000
||
1314 current_cpu_data
.cputype
== CPU_R6000A
) {
1316 * The R6000 is the only R-series CPU that features a machine
1317 * check exception (similar to the R4000 cache error) and
1318 * unaligned ldc1/sdc1 exception. The handlers have not been
1319 * written yet. Well, anyway there is no R6000 machine on the
1320 * current list of targets for Linux/MIPS.
1321 * (Duh, crap, there is someone with a triple R6k machine)
1323 //set_except_vector(14, handle_mc);
1324 //set_except_vector(15, handle_ndc);
1328 if (board_nmi_handler_setup
)
1329 board_nmi_handler_setup();
1331 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1332 set_except_vector(15, handle_fpe
);
1334 set_except_vector(22, handle_mdmx
);
1337 set_except_vector(24, handle_mcheck
);
1340 set_except_vector(25, handle_mt
);
1343 set_except_vector(26, handle_dsp
);
1346 /* Special exception: R4[04]00 uses also the divec space. */
1347 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_r4000
, 0x100);
1348 else if (cpu_has_4kex
)
1349 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
1351 memcpy((void *)(CAC_BASE
+ 0x080), &except_vec3_generic
, 0x80);
1354 #ifdef CONFIG_MIPS32_COMPAT
1358 flush_icache_range(ebase
, ebase
+ 0x400);
1359 flush_tlb_handlers();