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MIPS: Optimize current_cpu_type() for better code.
[deliverable/linux.git] / arch / mips / kernel / traps.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/context_tracking.h>
17 #include <linux/kexec.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mm.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/spinlock.h>
25 #include <linux/kallsyms.h>
26 #include <linux/bootmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/ptrace.h>
29 #include <linux/kgdb.h>
30 #include <linux/kdebug.h>
31 #include <linux/kprobes.h>
32 #include <linux/notifier.h>
33 #include <linux/kdb.h>
34 #include <linux/irq.h>
35 #include <linux/perf_event.h>
36
37 #include <asm/bootinfo.h>
38 #include <asm/branch.h>
39 #include <asm/break.h>
40 #include <asm/cop2.h>
41 #include <asm/cpu.h>
42 #include <asm/cpu-type.h>
43 #include <asm/dsp.h>
44 #include <asm/fpu.h>
45 #include <asm/fpu_emulator.h>
46 #include <asm/idle.h>
47 #include <asm/mipsregs.h>
48 #include <asm/mipsmtregs.h>
49 #include <asm/module.h>
50 #include <asm/pgtable.h>
51 #include <asm/ptrace.h>
52 #include <asm/sections.h>
53 #include <asm/tlbdebug.h>
54 #include <asm/traps.h>
55 #include <asm/uaccess.h>
56 #include <asm/watch.h>
57 #include <asm/mmu_context.h>
58 #include <asm/types.h>
59 #include <asm/stacktrace.h>
60 #include <asm/uasm.h>
61
62 extern void check_wait(void);
63 extern asmlinkage void rollback_handle_int(void);
64 extern asmlinkage void handle_int(void);
65 extern u32 handle_tlbl[];
66 extern u32 handle_tlbs[];
67 extern u32 handle_tlbm[];
68 extern asmlinkage void handle_adel(void);
69 extern asmlinkage void handle_ades(void);
70 extern asmlinkage void handle_ibe(void);
71 extern asmlinkage void handle_dbe(void);
72 extern asmlinkage void handle_sys(void);
73 extern asmlinkage void handle_bp(void);
74 extern asmlinkage void handle_ri(void);
75 extern asmlinkage void handle_ri_rdhwr_vivt(void);
76 extern asmlinkage void handle_ri_rdhwr(void);
77 extern asmlinkage void handle_cpu(void);
78 extern asmlinkage void handle_ov(void);
79 extern asmlinkage void handle_tr(void);
80 extern asmlinkage void handle_fpe(void);
81 extern asmlinkage void handle_mdmx(void);
82 extern asmlinkage void handle_watch(void);
83 extern asmlinkage void handle_mt(void);
84 extern asmlinkage void handle_dsp(void);
85 extern asmlinkage void handle_mcheck(void);
86 extern asmlinkage void handle_reserved(void);
87
88 void (*board_be_init)(void);
89 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
90 void (*board_nmi_handler_setup)(void);
91 void (*board_ejtag_handler_setup)(void);
92 void (*board_bind_eic_interrupt)(int irq, int regset);
93 void (*board_ebase_setup)(void);
94 void(*board_cache_error_setup)(void);
95
96 static void show_raw_backtrace(unsigned long reg29)
97 {
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
99 unsigned long addr;
100
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
103 printk("\n");
104 #endif
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112 if (__kernel_text_address(addr))
113 print_ip_sym(addr);
114 }
115 printk("\n");
116 }
117
118 #ifdef CONFIG_KALLSYMS
119 int raw_show_trace;
120 static int __init set_raw_show_trace(char *str)
121 {
122 raw_show_trace = 1;
123 return 1;
124 }
125 __setup("raw_show_trace", set_raw_show_trace);
126 #endif
127
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
129 {
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
133
134 if (!task)
135 task = current;
136
137 if (raw_show_trace || !__kernel_text_address(pc)) {
138 show_raw_backtrace(sp);
139 return;
140 }
141 printk("Call Trace:\n");
142 do {
143 print_ip_sym(pc);
144 pc = unwind_stack(task, &sp, pc, &ra);
145 } while (pc);
146 printk("\n");
147 }
148
149 /*
150 * This routine abuses get_user()/put_user() to reference pointers
151 * with at least a bit of error checking ...
152 */
153 static void show_stacktrace(struct task_struct *task,
154 const struct pt_regs *regs)
155 {
156 const int field = 2 * sizeof(unsigned long);
157 long stackdata;
158 int i;
159 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
160
161 printk("Stack :");
162 i = 0;
163 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
164 if (i && ((i % (64 / field)) == 0))
165 printk("\n ");
166 if (i > 39) {
167 printk(" ...");
168 break;
169 }
170
171 if (__get_user(stackdata, sp++)) {
172 printk(" (Bad stack address)");
173 break;
174 }
175
176 printk(" %0*lx", field, stackdata);
177 i++;
178 }
179 printk("\n");
180 show_backtrace(task, regs);
181 }
182
183 void show_stack(struct task_struct *task, unsigned long *sp)
184 {
185 struct pt_regs regs;
186 if (sp) {
187 regs.regs[29] = (unsigned long)sp;
188 regs.regs[31] = 0;
189 regs.cp0_epc = 0;
190 } else {
191 if (task && task != current) {
192 regs.regs[29] = task->thread.reg29;
193 regs.regs[31] = 0;
194 regs.cp0_epc = task->thread.reg31;
195 #ifdef CONFIG_KGDB_KDB
196 } else if (atomic_read(&kgdb_active) != -1 &&
197 kdb_current_regs) {
198 memcpy(&regs, kdb_current_regs, sizeof(regs));
199 #endif /* CONFIG_KGDB_KDB */
200 } else {
201 prepare_frametrace(&regs);
202 }
203 }
204 show_stacktrace(task, &regs);
205 }
206
207 static void show_code(unsigned int __user *pc)
208 {
209 long i;
210 unsigned short __user *pc16 = NULL;
211
212 printk("\nCode:");
213
214 if ((unsigned long)pc & 1)
215 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
216 for(i = -3 ; i < 6 ; i++) {
217 unsigned int insn;
218 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
219 printk(" (Bad address in epc)\n");
220 break;
221 }
222 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
223 }
224 }
225
226 static void __show_regs(const struct pt_regs *regs)
227 {
228 const int field = 2 * sizeof(unsigned long);
229 unsigned int cause = regs->cp0_cause;
230 int i;
231
232 show_regs_print_info(KERN_DEFAULT);
233
234 /*
235 * Saved main processor registers
236 */
237 for (i = 0; i < 32; ) {
238 if ((i % 4) == 0)
239 printk("$%2d :", i);
240 if (i == 0)
241 printk(" %0*lx", field, 0UL);
242 else if (i == 26 || i == 27)
243 printk(" %*s", field, "");
244 else
245 printk(" %0*lx", field, regs->regs[i]);
246
247 i++;
248 if ((i % 4) == 0)
249 printk("\n");
250 }
251
252 #ifdef CONFIG_CPU_HAS_SMARTMIPS
253 printk("Acx : %0*lx\n", field, regs->acx);
254 #endif
255 printk("Hi : %0*lx\n", field, regs->hi);
256 printk("Lo : %0*lx\n", field, regs->lo);
257
258 /*
259 * Saved cp0 registers
260 */
261 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
262 (void *) regs->cp0_epc);
263 printk(" %s\n", print_tainted());
264 printk("ra : %0*lx %pS\n", field, regs->regs[31],
265 (void *) regs->regs[31]);
266
267 printk("Status: %08x ", (uint32_t) regs->cp0_status);
268
269 if (cpu_has_3kex) {
270 if (regs->cp0_status & ST0_KUO)
271 printk("KUo ");
272 if (regs->cp0_status & ST0_IEO)
273 printk("IEo ");
274 if (regs->cp0_status & ST0_KUP)
275 printk("KUp ");
276 if (regs->cp0_status & ST0_IEP)
277 printk("IEp ");
278 if (regs->cp0_status & ST0_KUC)
279 printk("KUc ");
280 if (regs->cp0_status & ST0_IEC)
281 printk("IEc ");
282 } else if (cpu_has_4kex) {
283 if (regs->cp0_status & ST0_KX)
284 printk("KX ");
285 if (regs->cp0_status & ST0_SX)
286 printk("SX ");
287 if (regs->cp0_status & ST0_UX)
288 printk("UX ");
289 switch (regs->cp0_status & ST0_KSU) {
290 case KSU_USER:
291 printk("USER ");
292 break;
293 case KSU_SUPERVISOR:
294 printk("SUPERVISOR ");
295 break;
296 case KSU_KERNEL:
297 printk("KERNEL ");
298 break;
299 default:
300 printk("BAD_MODE ");
301 break;
302 }
303 if (regs->cp0_status & ST0_ERL)
304 printk("ERL ");
305 if (regs->cp0_status & ST0_EXL)
306 printk("EXL ");
307 if (regs->cp0_status & ST0_IE)
308 printk("IE ");
309 }
310 printk("\n");
311
312 printk("Cause : %08x\n", cause);
313
314 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
315 if (1 <= cause && cause <= 5)
316 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
317
318 printk("PrId : %08x (%s)\n", read_c0_prid(),
319 cpu_name_string());
320 }
321
322 /*
323 * FIXME: really the generic show_regs should take a const pointer argument.
324 */
325 void show_regs(struct pt_regs *regs)
326 {
327 __show_regs((struct pt_regs *)regs);
328 }
329
330 void show_registers(struct pt_regs *regs)
331 {
332 const int field = 2 * sizeof(unsigned long);
333
334 __show_regs(regs);
335 print_modules();
336 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
337 current->comm, current->pid, current_thread_info(), current,
338 field, current_thread_info()->tp_value);
339 if (cpu_has_userlocal) {
340 unsigned long tls;
341
342 tls = read_c0_userlocal();
343 if (tls != current_thread_info()->tp_value)
344 printk("*HwTLS: %0*lx\n", field, tls);
345 }
346
347 show_stacktrace(current, regs);
348 show_code((unsigned int __user *) regs->cp0_epc);
349 printk("\n");
350 }
351
352 static int regs_to_trapnr(struct pt_regs *regs)
353 {
354 return (regs->cp0_cause >> 2) & 0x1f;
355 }
356
357 static DEFINE_RAW_SPINLOCK(die_lock);
358
359 void __noreturn die(const char *str, struct pt_regs *regs)
360 {
361 static int die_counter;
362 int sig = SIGSEGV;
363 #ifdef CONFIG_MIPS_MT_SMTC
364 unsigned long dvpret;
365 #endif /* CONFIG_MIPS_MT_SMTC */
366
367 oops_enter();
368
369 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
370 sig = 0;
371
372 console_verbose();
373 raw_spin_lock_irq(&die_lock);
374 #ifdef CONFIG_MIPS_MT_SMTC
375 dvpret = dvpe();
376 #endif /* CONFIG_MIPS_MT_SMTC */
377 bust_spinlocks(1);
378 #ifdef CONFIG_MIPS_MT_SMTC
379 mips_mt_regdump(dvpret);
380 #endif /* CONFIG_MIPS_MT_SMTC */
381
382 printk("%s[#%d]:\n", str, ++die_counter);
383 show_registers(regs);
384 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
385 raw_spin_unlock_irq(&die_lock);
386
387 oops_exit();
388
389 if (in_interrupt())
390 panic("Fatal exception in interrupt");
391
392 if (panic_on_oops) {
393 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
394 ssleep(5);
395 panic("Fatal exception");
396 }
397
398 if (regs && kexec_should_crash(current))
399 crash_kexec(regs);
400
401 do_exit(sig);
402 }
403
404 extern struct exception_table_entry __start___dbe_table[];
405 extern struct exception_table_entry __stop___dbe_table[];
406
407 __asm__(
408 " .section __dbe_table, \"a\"\n"
409 " .previous \n");
410
411 /* Given an address, look for it in the exception tables. */
412 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
413 {
414 const struct exception_table_entry *e;
415
416 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
417 if (!e)
418 e = search_module_dbetables(addr);
419 return e;
420 }
421
422 asmlinkage void do_be(struct pt_regs *regs)
423 {
424 const int field = 2 * sizeof(unsigned long);
425 const struct exception_table_entry *fixup = NULL;
426 int data = regs->cp0_cause & 4;
427 int action = MIPS_BE_FATAL;
428 enum ctx_state prev_state;
429
430 prev_state = exception_enter();
431 /* XXX For now. Fixme, this searches the wrong table ... */
432 if (data && !user_mode(regs))
433 fixup = search_dbe_tables(exception_epc(regs));
434
435 if (fixup)
436 action = MIPS_BE_FIXUP;
437
438 if (board_be_handler)
439 action = board_be_handler(regs, fixup != NULL);
440
441 switch (action) {
442 case MIPS_BE_DISCARD:
443 goto out;
444 case MIPS_BE_FIXUP:
445 if (fixup) {
446 regs->cp0_epc = fixup->nextinsn;
447 goto out;
448 }
449 break;
450 default:
451 break;
452 }
453
454 /*
455 * Assume it would be too dangerous to continue ...
456 */
457 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
458 data ? "Data" : "Instruction",
459 field, regs->cp0_epc, field, regs->regs[31]);
460 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
461 == NOTIFY_STOP)
462 goto out;
463
464 die_if_kernel("Oops", regs);
465 force_sig(SIGBUS, current);
466
467 out:
468 exception_exit(prev_state);
469 }
470
471 /*
472 * ll/sc, rdhwr, sync emulation
473 */
474
475 #define OPCODE 0xfc000000
476 #define BASE 0x03e00000
477 #define RT 0x001f0000
478 #define OFFSET 0x0000ffff
479 #define LL 0xc0000000
480 #define SC 0xe0000000
481 #define SPEC0 0x00000000
482 #define SPEC3 0x7c000000
483 #define RD 0x0000f800
484 #define FUNC 0x0000003f
485 #define SYNC 0x0000000f
486 #define RDHWR 0x0000003b
487
488 /* microMIPS definitions */
489 #define MM_POOL32A_FUNC 0xfc00ffff
490 #define MM_RDHWR 0x00006b3c
491 #define MM_RS 0x001f0000
492 #define MM_RT 0x03e00000
493
494 /*
495 * The ll_bit is cleared by r*_switch.S
496 */
497
498 unsigned int ll_bit;
499 struct task_struct *ll_task;
500
501 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
502 {
503 unsigned long value, __user *vaddr;
504 long offset;
505
506 /*
507 * analyse the ll instruction that just caused a ri exception
508 * and put the referenced address to addr.
509 */
510
511 /* sign extend offset */
512 offset = opcode & OFFSET;
513 offset <<= 16;
514 offset >>= 16;
515
516 vaddr = (unsigned long __user *)
517 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
518
519 if ((unsigned long)vaddr & 3)
520 return SIGBUS;
521 if (get_user(value, vaddr))
522 return SIGSEGV;
523
524 preempt_disable();
525
526 if (ll_task == NULL || ll_task == current) {
527 ll_bit = 1;
528 } else {
529 ll_bit = 0;
530 }
531 ll_task = current;
532
533 preempt_enable();
534
535 regs->regs[(opcode & RT) >> 16] = value;
536
537 return 0;
538 }
539
540 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
541 {
542 unsigned long __user *vaddr;
543 unsigned long reg;
544 long offset;
545
546 /*
547 * analyse the sc instruction that just caused a ri exception
548 * and put the referenced address to addr.
549 */
550
551 /* sign extend offset */
552 offset = opcode & OFFSET;
553 offset <<= 16;
554 offset >>= 16;
555
556 vaddr = (unsigned long __user *)
557 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
558 reg = (opcode & RT) >> 16;
559
560 if ((unsigned long)vaddr & 3)
561 return SIGBUS;
562
563 preempt_disable();
564
565 if (ll_bit == 0 || ll_task != current) {
566 regs->regs[reg] = 0;
567 preempt_enable();
568 return 0;
569 }
570
571 preempt_enable();
572
573 if (put_user(regs->regs[reg], vaddr))
574 return SIGSEGV;
575
576 regs->regs[reg] = 1;
577
578 return 0;
579 }
580
581 /*
582 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
583 * opcodes are supposed to result in coprocessor unusable exceptions if
584 * executed on ll/sc-less processors. That's the theory. In practice a
585 * few processors such as NEC's VR4100 throw reserved instruction exceptions
586 * instead, so we're doing the emulation thing in both exception handlers.
587 */
588 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
589 {
590 if ((opcode & OPCODE) == LL) {
591 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
592 1, regs, 0);
593 return simulate_ll(regs, opcode);
594 }
595 if ((opcode & OPCODE) == SC) {
596 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
597 1, regs, 0);
598 return simulate_sc(regs, opcode);
599 }
600
601 return -1; /* Must be something else ... */
602 }
603
604 /*
605 * Simulate trapping 'rdhwr' instructions to provide user accessible
606 * registers not implemented in hardware.
607 */
608 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
609 {
610 struct thread_info *ti = task_thread_info(current);
611
612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
613 1, regs, 0);
614 switch (rd) {
615 case 0: /* CPU number */
616 regs->regs[rt] = smp_processor_id();
617 return 0;
618 case 1: /* SYNCI length */
619 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
620 current_cpu_data.icache.linesz);
621 return 0;
622 case 2: /* Read count register */
623 regs->regs[rt] = read_c0_count();
624 return 0;
625 case 3: /* Count register resolution */
626 switch (current_cpu_type()) {
627 case CPU_20KC:
628 case CPU_25KF:
629 regs->regs[rt] = 1;
630 break;
631 default:
632 regs->regs[rt] = 2;
633 }
634 return 0;
635 case 29:
636 regs->regs[rt] = ti->tp_value;
637 return 0;
638 default:
639 return -1;
640 }
641 }
642
643 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
644 {
645 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
646 int rd = (opcode & RD) >> 11;
647 int rt = (opcode & RT) >> 16;
648
649 simulate_rdhwr(regs, rd, rt);
650 return 0;
651 }
652
653 /* Not ours. */
654 return -1;
655 }
656
657 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
658 {
659 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
660 int rd = (opcode & MM_RS) >> 16;
661 int rt = (opcode & MM_RT) >> 21;
662 simulate_rdhwr(regs, rd, rt);
663 return 0;
664 }
665
666 /* Not ours. */
667 return -1;
668 }
669
670 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
671 {
672 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
673 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
674 1, regs, 0);
675 return 0;
676 }
677
678 return -1; /* Must be something else ... */
679 }
680
681 asmlinkage void do_ov(struct pt_regs *regs)
682 {
683 enum ctx_state prev_state;
684 siginfo_t info;
685
686 prev_state = exception_enter();
687 die_if_kernel("Integer overflow", regs);
688
689 info.si_code = FPE_INTOVF;
690 info.si_signo = SIGFPE;
691 info.si_errno = 0;
692 info.si_addr = (void __user *) regs->cp0_epc;
693 force_sig_info(SIGFPE, &info, current);
694 exception_exit(prev_state);
695 }
696
697 int process_fpemu_return(int sig, void __user *fault_addr)
698 {
699 if (sig == SIGSEGV || sig == SIGBUS) {
700 struct siginfo si = {0};
701 si.si_addr = fault_addr;
702 si.si_signo = sig;
703 if (sig == SIGSEGV) {
704 if (find_vma(current->mm, (unsigned long)fault_addr))
705 si.si_code = SEGV_ACCERR;
706 else
707 si.si_code = SEGV_MAPERR;
708 } else {
709 si.si_code = BUS_ADRERR;
710 }
711 force_sig_info(sig, &si, current);
712 return 1;
713 } else if (sig) {
714 force_sig(sig, current);
715 return 1;
716 } else {
717 return 0;
718 }
719 }
720
721 /*
722 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
723 */
724 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
725 {
726 enum ctx_state prev_state;
727 siginfo_t info = {0};
728
729 prev_state = exception_enter();
730 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
731 == NOTIFY_STOP)
732 goto out;
733 die_if_kernel("FP exception in kernel code", regs);
734
735 if (fcr31 & FPU_CSR_UNI_X) {
736 int sig;
737 void __user *fault_addr = NULL;
738
739 /*
740 * Unimplemented operation exception. If we've got the full
741 * software emulator on-board, let's use it...
742 *
743 * Force FPU to dump state into task/thread context. We're
744 * moving a lot of data here for what is probably a single
745 * instruction, but the alternative is to pre-decode the FP
746 * register operands before invoking the emulator, which seems
747 * a bit extreme for what should be an infrequent event.
748 */
749 /* Ensure 'resume' not overwrite saved fp context again. */
750 lose_fpu(1);
751
752 /* Run the emulator */
753 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
754 &fault_addr);
755
756 /*
757 * We can't allow the emulated instruction to leave any of
758 * the cause bit set in $fcr31.
759 */
760 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
761
762 /* Restore the hardware register state */
763 own_fpu(1); /* Using the FPU again. */
764
765 /* If something went wrong, signal */
766 process_fpemu_return(sig, fault_addr);
767
768 goto out;
769 } else if (fcr31 & FPU_CSR_INV_X)
770 info.si_code = FPE_FLTINV;
771 else if (fcr31 & FPU_CSR_DIV_X)
772 info.si_code = FPE_FLTDIV;
773 else if (fcr31 & FPU_CSR_OVF_X)
774 info.si_code = FPE_FLTOVF;
775 else if (fcr31 & FPU_CSR_UDF_X)
776 info.si_code = FPE_FLTUND;
777 else if (fcr31 & FPU_CSR_INE_X)
778 info.si_code = FPE_FLTRES;
779 else
780 info.si_code = __SI_FAULT;
781 info.si_signo = SIGFPE;
782 info.si_errno = 0;
783 info.si_addr = (void __user *) regs->cp0_epc;
784 force_sig_info(SIGFPE, &info, current);
785
786 out:
787 exception_exit(prev_state);
788 }
789
790 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
791 const char *str)
792 {
793 siginfo_t info;
794 char b[40];
795
796 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
797 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
798 return;
799 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
800
801 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
802 return;
803
804 /*
805 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
806 * insns, even for trap and break codes that indicate arithmetic
807 * failures. Weird ...
808 * But should we continue the brokenness??? --macro
809 */
810 switch (code) {
811 case BRK_OVERFLOW:
812 case BRK_DIVZERO:
813 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
814 die_if_kernel(b, regs);
815 if (code == BRK_DIVZERO)
816 info.si_code = FPE_INTDIV;
817 else
818 info.si_code = FPE_INTOVF;
819 info.si_signo = SIGFPE;
820 info.si_errno = 0;
821 info.si_addr = (void __user *) regs->cp0_epc;
822 force_sig_info(SIGFPE, &info, current);
823 break;
824 case BRK_BUG:
825 die_if_kernel("Kernel bug detected", regs);
826 force_sig(SIGTRAP, current);
827 break;
828 case BRK_MEMU:
829 /*
830 * Address errors may be deliberately induced by the FPU
831 * emulator to retake control of the CPU after executing the
832 * instruction in the delay slot of an emulated branch.
833 *
834 * Terminate if exception was recognized as a delay slot return
835 * otherwise handle as normal.
836 */
837 if (do_dsemulret(regs))
838 return;
839
840 die_if_kernel("Math emu break/trap", regs);
841 force_sig(SIGTRAP, current);
842 break;
843 default:
844 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
845 die_if_kernel(b, regs);
846 force_sig(SIGTRAP, current);
847 }
848 }
849
850 asmlinkage void do_bp(struct pt_regs *regs)
851 {
852 unsigned int opcode, bcode;
853 enum ctx_state prev_state;
854 unsigned long epc;
855 u16 instr[2];
856
857 prev_state = exception_enter();
858 if (get_isa16_mode(regs->cp0_epc)) {
859 /* Calculate EPC. */
860 epc = exception_epc(regs);
861 if (cpu_has_mmips) {
862 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
863 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
864 goto out_sigsegv;
865 opcode = (instr[0] << 16) | instr[1];
866 } else {
867 /* MIPS16e mode */
868 if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
869 goto out_sigsegv;
870 bcode = (instr[0] >> 6) & 0x3f;
871 do_trap_or_bp(regs, bcode, "Break");
872 goto out;
873 }
874 } else {
875 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
876 goto out_sigsegv;
877 }
878
879 /*
880 * There is the ancient bug in the MIPS assemblers that the break
881 * code starts left to bit 16 instead to bit 6 in the opcode.
882 * Gas is bug-compatible, but not always, grrr...
883 * We handle both cases with a simple heuristics. --macro
884 */
885 bcode = ((opcode >> 6) & ((1 << 20) - 1));
886 if (bcode >= (1 << 10))
887 bcode >>= 10;
888
889 /*
890 * notify the kprobe handlers, if instruction is likely to
891 * pertain to them.
892 */
893 switch (bcode) {
894 case BRK_KPROBE_BP:
895 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
896 goto out;
897 else
898 break;
899 case BRK_KPROBE_SSTEPBP:
900 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
901 goto out;
902 else
903 break;
904 default:
905 break;
906 }
907
908 do_trap_or_bp(regs, bcode, "Break");
909
910 out:
911 exception_exit(prev_state);
912 return;
913
914 out_sigsegv:
915 force_sig(SIGSEGV, current);
916 goto out;
917 }
918
919 asmlinkage void do_tr(struct pt_regs *regs)
920 {
921 u32 opcode, tcode = 0;
922 enum ctx_state prev_state;
923 u16 instr[2];
924 unsigned long epc = msk_isa16_mode(exception_epc(regs));
925
926 prev_state = exception_enter();
927 if (get_isa16_mode(regs->cp0_epc)) {
928 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
929 __get_user(instr[1], (u16 __user *)(epc + 2)))
930 goto out_sigsegv;
931 opcode = (instr[0] << 16) | instr[1];
932 /* Immediate versions don't provide a code. */
933 if (!(opcode & OPCODE))
934 tcode = (opcode >> 12) & ((1 << 4) - 1);
935 } else {
936 if (__get_user(opcode, (u32 __user *)epc))
937 goto out_sigsegv;
938 /* Immediate versions don't provide a code. */
939 if (!(opcode & OPCODE))
940 tcode = (opcode >> 6) & ((1 << 10) - 1);
941 }
942
943 do_trap_or_bp(regs, tcode, "Trap");
944
945 out:
946 exception_exit(prev_state);
947 return;
948
949 out_sigsegv:
950 force_sig(SIGSEGV, current);
951 goto out;
952 }
953
954 asmlinkage void do_ri(struct pt_regs *regs)
955 {
956 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
957 unsigned long old_epc = regs->cp0_epc;
958 unsigned long old31 = regs->regs[31];
959 enum ctx_state prev_state;
960 unsigned int opcode = 0;
961 int status = -1;
962
963 prev_state = exception_enter();
964 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
965 == NOTIFY_STOP)
966 goto out;
967
968 die_if_kernel("Reserved instruction in kernel code", regs);
969
970 if (unlikely(compute_return_epc(regs) < 0))
971 goto out;
972
973 if (get_isa16_mode(regs->cp0_epc)) {
974 unsigned short mmop[2] = { 0 };
975
976 if (unlikely(get_user(mmop[0], epc) < 0))
977 status = SIGSEGV;
978 if (unlikely(get_user(mmop[1], epc) < 0))
979 status = SIGSEGV;
980 opcode = (mmop[0] << 16) | mmop[1];
981
982 if (status < 0)
983 status = simulate_rdhwr_mm(regs, opcode);
984 } else {
985 if (unlikely(get_user(opcode, epc) < 0))
986 status = SIGSEGV;
987
988 if (!cpu_has_llsc && status < 0)
989 status = simulate_llsc(regs, opcode);
990
991 if (status < 0)
992 status = simulate_rdhwr_normal(regs, opcode);
993
994 if (status < 0)
995 status = simulate_sync(regs, opcode);
996 }
997
998 if (status < 0)
999 status = SIGILL;
1000
1001 if (unlikely(status > 0)) {
1002 regs->cp0_epc = old_epc; /* Undo skip-over. */
1003 regs->regs[31] = old31;
1004 force_sig(status, current);
1005 }
1006
1007 out:
1008 exception_exit(prev_state);
1009 }
1010
1011 /*
1012 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1013 * emulated more than some threshold number of instructions, force migration to
1014 * a "CPU" that has FP support.
1015 */
1016 static void mt_ase_fp_affinity(void)
1017 {
1018 #ifdef CONFIG_MIPS_MT_FPAFF
1019 if (mt_fpemul_threshold > 0 &&
1020 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1021 /*
1022 * If there's no FPU present, or if the application has already
1023 * restricted the allowed set to exclude any CPUs with FPUs,
1024 * we'll skip the procedure.
1025 */
1026 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1027 cpumask_t tmask;
1028
1029 current->thread.user_cpus_allowed
1030 = current->cpus_allowed;
1031 cpus_and(tmask, current->cpus_allowed,
1032 mt_fpu_cpumask);
1033 set_cpus_allowed_ptr(current, &tmask);
1034 set_thread_flag(TIF_FPUBOUND);
1035 }
1036 }
1037 #endif /* CONFIG_MIPS_MT_FPAFF */
1038 }
1039
1040 /*
1041 * No lock; only written during early bootup by CPU 0.
1042 */
1043 static RAW_NOTIFIER_HEAD(cu2_chain);
1044
1045 int __ref register_cu2_notifier(struct notifier_block *nb)
1046 {
1047 return raw_notifier_chain_register(&cu2_chain, nb);
1048 }
1049
1050 int cu2_notifier_call_chain(unsigned long val, void *v)
1051 {
1052 return raw_notifier_call_chain(&cu2_chain, val, v);
1053 }
1054
1055 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1056 void *data)
1057 {
1058 struct pt_regs *regs = data;
1059
1060 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1061 "instruction", regs);
1062 force_sig(SIGILL, current);
1063
1064 return NOTIFY_OK;
1065 }
1066
1067 asmlinkage void do_cpu(struct pt_regs *regs)
1068 {
1069 enum ctx_state prev_state;
1070 unsigned int __user *epc;
1071 unsigned long old_epc, old31;
1072 unsigned int opcode;
1073 unsigned int cpid;
1074 int status;
1075 unsigned long __maybe_unused flags;
1076
1077 prev_state = exception_enter();
1078 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1079
1080 if (cpid != 2)
1081 die_if_kernel("do_cpu invoked from kernel context!", regs);
1082
1083 switch (cpid) {
1084 case 0:
1085 epc = (unsigned int __user *)exception_epc(regs);
1086 old_epc = regs->cp0_epc;
1087 old31 = regs->regs[31];
1088 opcode = 0;
1089 status = -1;
1090
1091 if (unlikely(compute_return_epc(regs) < 0))
1092 goto out;
1093
1094 if (get_isa16_mode(regs->cp0_epc)) {
1095 unsigned short mmop[2] = { 0 };
1096
1097 if (unlikely(get_user(mmop[0], epc) < 0))
1098 status = SIGSEGV;
1099 if (unlikely(get_user(mmop[1], epc) < 0))
1100 status = SIGSEGV;
1101 opcode = (mmop[0] << 16) | mmop[1];
1102
1103 if (status < 0)
1104 status = simulate_rdhwr_mm(regs, opcode);
1105 } else {
1106 if (unlikely(get_user(opcode, epc) < 0))
1107 status = SIGSEGV;
1108
1109 if (!cpu_has_llsc && status < 0)
1110 status = simulate_llsc(regs, opcode);
1111
1112 if (status < 0)
1113 status = simulate_rdhwr_normal(regs, opcode);
1114 }
1115
1116 if (status < 0)
1117 status = SIGILL;
1118
1119 if (unlikely(status > 0)) {
1120 regs->cp0_epc = old_epc; /* Undo skip-over. */
1121 regs->regs[31] = old31;
1122 force_sig(status, current);
1123 }
1124
1125 goto out;
1126
1127 case 3:
1128 /*
1129 * Old (MIPS I and MIPS II) processors will set this code
1130 * for COP1X opcode instructions that replaced the original
1131 * COP3 space. We don't limit COP1 space instructions in
1132 * the emulator according to the CPU ISA, so we want to
1133 * treat COP1X instructions consistently regardless of which
1134 * code the CPU chose. Therefore we redirect this trap to
1135 * the FP emulator too.
1136 *
1137 * Then some newer FPU-less processors use this code
1138 * erroneously too, so they are covered by this choice
1139 * as well.
1140 */
1141 if (raw_cpu_has_fpu)
1142 break;
1143 /* Fall through. */
1144
1145 case 1:
1146 if (used_math()) /* Using the FPU again. */
1147 own_fpu(1);
1148 else { /* First time FPU user. */
1149 init_fpu();
1150 set_used_math();
1151 }
1152
1153 if (!raw_cpu_has_fpu) {
1154 int sig;
1155 void __user *fault_addr = NULL;
1156 sig = fpu_emulator_cop1Handler(regs,
1157 &current->thread.fpu,
1158 0, &fault_addr);
1159 if (!process_fpemu_return(sig, fault_addr))
1160 mt_ase_fp_affinity();
1161 }
1162
1163 goto out;
1164
1165 case 2:
1166 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1167 goto out;
1168 }
1169
1170 force_sig(SIGILL, current);
1171
1172 out:
1173 exception_exit(prev_state);
1174 }
1175
1176 asmlinkage void do_mdmx(struct pt_regs *regs)
1177 {
1178 enum ctx_state prev_state;
1179
1180 prev_state = exception_enter();
1181 force_sig(SIGILL, current);
1182 exception_exit(prev_state);
1183 }
1184
1185 /*
1186 * Called with interrupts disabled.
1187 */
1188 asmlinkage void do_watch(struct pt_regs *regs)
1189 {
1190 enum ctx_state prev_state;
1191 u32 cause;
1192
1193 prev_state = exception_enter();
1194 /*
1195 * Clear WP (bit 22) bit of cause register so we don't loop
1196 * forever.
1197 */
1198 cause = read_c0_cause();
1199 cause &= ~(1 << 22);
1200 write_c0_cause(cause);
1201
1202 /*
1203 * If the current thread has the watch registers loaded, save
1204 * their values and send SIGTRAP. Otherwise another thread
1205 * left the registers set, clear them and continue.
1206 */
1207 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1208 mips_read_watch_registers();
1209 local_irq_enable();
1210 force_sig(SIGTRAP, current);
1211 } else {
1212 mips_clear_watch_registers();
1213 local_irq_enable();
1214 }
1215 exception_exit(prev_state);
1216 }
1217
1218 asmlinkage void do_mcheck(struct pt_regs *regs)
1219 {
1220 const int field = 2 * sizeof(unsigned long);
1221 int multi_match = regs->cp0_status & ST0_TS;
1222 enum ctx_state prev_state;
1223
1224 prev_state = exception_enter();
1225 show_regs(regs);
1226
1227 if (multi_match) {
1228 printk("Index : %0x\n", read_c0_index());
1229 printk("Pagemask: %0x\n", read_c0_pagemask());
1230 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1231 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1232 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1233 printk("\n");
1234 dump_tlb_all();
1235 }
1236
1237 show_code((unsigned int __user *) regs->cp0_epc);
1238
1239 /*
1240 * Some chips may have other causes of machine check (e.g. SB1
1241 * graduation timer)
1242 */
1243 panic("Caught Machine Check exception - %scaused by multiple "
1244 "matching entries in the TLB.",
1245 (multi_match) ? "" : "not ");
1246 }
1247
1248 asmlinkage void do_mt(struct pt_regs *regs)
1249 {
1250 int subcode;
1251
1252 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1253 >> VPECONTROL_EXCPT_SHIFT;
1254 switch (subcode) {
1255 case 0:
1256 printk(KERN_DEBUG "Thread Underflow\n");
1257 break;
1258 case 1:
1259 printk(KERN_DEBUG "Thread Overflow\n");
1260 break;
1261 case 2:
1262 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1263 break;
1264 case 3:
1265 printk(KERN_DEBUG "Gating Storage Exception\n");
1266 break;
1267 case 4:
1268 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1269 break;
1270 case 5:
1271 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1272 break;
1273 default:
1274 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1275 subcode);
1276 break;
1277 }
1278 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1279
1280 force_sig(SIGILL, current);
1281 }
1282
1283
1284 asmlinkage void do_dsp(struct pt_regs *regs)
1285 {
1286 if (cpu_has_dsp)
1287 panic("Unexpected DSP exception");
1288
1289 force_sig(SIGILL, current);
1290 }
1291
1292 asmlinkage void do_reserved(struct pt_regs *regs)
1293 {
1294 /*
1295 * Game over - no way to handle this if it ever occurs. Most probably
1296 * caused by a new unknown cpu type or after another deadly
1297 * hard/software error.
1298 */
1299 show_regs(regs);
1300 panic("Caught reserved exception %ld - should not happen.",
1301 (regs->cp0_cause & 0x7f) >> 2);
1302 }
1303
1304 static int __initdata l1parity = 1;
1305 static int __init nol1parity(char *s)
1306 {
1307 l1parity = 0;
1308 return 1;
1309 }
1310 __setup("nol1par", nol1parity);
1311 static int __initdata l2parity = 1;
1312 static int __init nol2parity(char *s)
1313 {
1314 l2parity = 0;
1315 return 1;
1316 }
1317 __setup("nol2par", nol2parity);
1318
1319 /*
1320 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1321 * it different ways.
1322 */
1323 static inline void parity_protection_init(void)
1324 {
1325 switch (current_cpu_type()) {
1326 case CPU_24K:
1327 case CPU_34K:
1328 case CPU_74K:
1329 case CPU_1004K:
1330 {
1331 #define ERRCTL_PE 0x80000000
1332 #define ERRCTL_L2P 0x00800000
1333 unsigned long errctl;
1334 unsigned int l1parity_present, l2parity_present;
1335
1336 errctl = read_c0_ecc();
1337 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1338
1339 /* probe L1 parity support */
1340 write_c0_ecc(errctl | ERRCTL_PE);
1341 back_to_back_c0_hazard();
1342 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1343
1344 /* probe L2 parity support */
1345 write_c0_ecc(errctl|ERRCTL_L2P);
1346 back_to_back_c0_hazard();
1347 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1348
1349 if (l1parity_present && l2parity_present) {
1350 if (l1parity)
1351 errctl |= ERRCTL_PE;
1352 if (l1parity ^ l2parity)
1353 errctl |= ERRCTL_L2P;
1354 } else if (l1parity_present) {
1355 if (l1parity)
1356 errctl |= ERRCTL_PE;
1357 } else if (l2parity_present) {
1358 if (l2parity)
1359 errctl |= ERRCTL_L2P;
1360 } else {
1361 /* No parity available */
1362 }
1363
1364 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1365
1366 write_c0_ecc(errctl);
1367 back_to_back_c0_hazard();
1368 errctl = read_c0_ecc();
1369 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1370
1371 if (l1parity_present)
1372 printk(KERN_INFO "Cache parity protection %sabled\n",
1373 (errctl & ERRCTL_PE) ? "en" : "dis");
1374
1375 if (l2parity_present) {
1376 if (l1parity_present && l1parity)
1377 errctl ^= ERRCTL_L2P;
1378 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1379 (errctl & ERRCTL_L2P) ? "en" : "dis");
1380 }
1381 }
1382 break;
1383
1384 case CPU_5KC:
1385 case CPU_5KE:
1386 case CPU_LOONGSON1:
1387 write_c0_ecc(0x80000000);
1388 back_to_back_c0_hazard();
1389 /* Set the PE bit (bit 31) in the c0_errctl register. */
1390 printk(KERN_INFO "Cache parity protection %sabled\n",
1391 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1392 break;
1393 case CPU_20KC:
1394 case CPU_25KF:
1395 /* Clear the DE bit (bit 16) in the c0_status register. */
1396 printk(KERN_INFO "Enable cache parity protection for "
1397 "MIPS 20KC/25KF CPUs.\n");
1398 clear_c0_status(ST0_DE);
1399 break;
1400 default:
1401 break;
1402 }
1403 }
1404
1405 asmlinkage void cache_parity_error(void)
1406 {
1407 const int field = 2 * sizeof(unsigned long);
1408 unsigned int reg_val;
1409
1410 /* For the moment, report the problem and hang. */
1411 printk("Cache error exception:\n");
1412 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1413 reg_val = read_c0_cacheerr();
1414 printk("c0_cacheerr == %08x\n", reg_val);
1415
1416 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1417 reg_val & (1<<30) ? "secondary" : "primary",
1418 reg_val & (1<<31) ? "data" : "insn");
1419 printk("Error bits: %s%s%s%s%s%s%s\n",
1420 reg_val & (1<<29) ? "ED " : "",
1421 reg_val & (1<<28) ? "ET " : "",
1422 reg_val & (1<<26) ? "EE " : "",
1423 reg_val & (1<<25) ? "EB " : "",
1424 reg_val & (1<<24) ? "EI " : "",
1425 reg_val & (1<<23) ? "E1 " : "",
1426 reg_val & (1<<22) ? "E0 " : "");
1427 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1428
1429 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1430 if (reg_val & (1<<22))
1431 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1432
1433 if (reg_val & (1<<23))
1434 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1435 #endif
1436
1437 panic("Can't handle the cache error!");
1438 }
1439
1440 /*
1441 * SDBBP EJTAG debug exception handler.
1442 * We skip the instruction and return to the next instruction.
1443 */
1444 void ejtag_exception_handler(struct pt_regs *regs)
1445 {
1446 const int field = 2 * sizeof(unsigned long);
1447 unsigned long depc, old_epc, old_ra;
1448 unsigned int debug;
1449
1450 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1451 depc = read_c0_depc();
1452 debug = read_c0_debug();
1453 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1454 if (debug & 0x80000000) {
1455 /*
1456 * In branch delay slot.
1457 * We cheat a little bit here and use EPC to calculate the
1458 * debug return address (DEPC). EPC is restored after the
1459 * calculation.
1460 */
1461 old_epc = regs->cp0_epc;
1462 old_ra = regs->regs[31];
1463 regs->cp0_epc = depc;
1464 compute_return_epc(regs);
1465 depc = regs->cp0_epc;
1466 regs->cp0_epc = old_epc;
1467 regs->regs[31] = old_ra;
1468 } else
1469 depc += 4;
1470 write_c0_depc(depc);
1471
1472 #if 0
1473 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1474 write_c0_debug(debug | 0x100);
1475 #endif
1476 }
1477
1478 /*
1479 * NMI exception handler.
1480 * No lock; only written during early bootup by CPU 0.
1481 */
1482 static RAW_NOTIFIER_HEAD(nmi_chain);
1483
1484 int register_nmi_notifier(struct notifier_block *nb)
1485 {
1486 return raw_notifier_chain_register(&nmi_chain, nb);
1487 }
1488
1489 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1490 {
1491 raw_notifier_call_chain(&nmi_chain, 0, regs);
1492 bust_spinlocks(1);
1493 printk("NMI taken!!!!\n");
1494 die("NMI", regs);
1495 }
1496
1497 #define VECTORSPACING 0x100 /* for EI/VI mode */
1498
1499 unsigned long ebase;
1500 unsigned long exception_handlers[32];
1501 unsigned long vi_handlers[64];
1502
1503 void __init *set_except_vector(int n, void *addr)
1504 {
1505 unsigned long handler = (unsigned long) addr;
1506 unsigned long old_handler;
1507
1508 #ifdef CONFIG_CPU_MICROMIPS
1509 /*
1510 * Only the TLB handlers are cache aligned with an even
1511 * address. All other handlers are on an odd address and
1512 * require no modification. Otherwise, MIPS32 mode will
1513 * be entered when handling any TLB exceptions. That
1514 * would be bad...since we must stay in microMIPS mode.
1515 */
1516 if (!(handler & 0x1))
1517 handler |= 1;
1518 #endif
1519 old_handler = xchg(&exception_handlers[n], handler);
1520
1521 if (n == 0 && cpu_has_divec) {
1522 #ifdef CONFIG_CPU_MICROMIPS
1523 unsigned long jump_mask = ~((1 << 27) - 1);
1524 #else
1525 unsigned long jump_mask = ~((1 << 28) - 1);
1526 #endif
1527 u32 *buf = (u32 *)(ebase + 0x200);
1528 unsigned int k0 = 26;
1529 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1530 uasm_i_j(&buf, handler & ~jump_mask);
1531 uasm_i_nop(&buf);
1532 } else {
1533 UASM_i_LA(&buf, k0, handler);
1534 uasm_i_jr(&buf, k0);
1535 uasm_i_nop(&buf);
1536 }
1537 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1538 }
1539 return (void *)old_handler;
1540 }
1541
1542 static void do_default_vi(void)
1543 {
1544 show_regs(get_irq_regs());
1545 panic("Caught unexpected vectored interrupt.");
1546 }
1547
1548 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1549 {
1550 unsigned long handler;
1551 unsigned long old_handler = vi_handlers[n];
1552 int srssets = current_cpu_data.srsets;
1553 u16 *h;
1554 unsigned char *b;
1555
1556 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1557 BUG_ON((n < 0) && (n > 9));
1558
1559 if (addr == NULL) {
1560 handler = (unsigned long) do_default_vi;
1561 srs = 0;
1562 } else
1563 handler = (unsigned long) addr;
1564 vi_handlers[n] = handler;
1565
1566 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1567
1568 if (srs >= srssets)
1569 panic("Shadow register set %d not supported", srs);
1570
1571 if (cpu_has_veic) {
1572 if (board_bind_eic_interrupt)
1573 board_bind_eic_interrupt(n, srs);
1574 } else if (cpu_has_vint) {
1575 /* SRSMap is only defined if shadow sets are implemented */
1576 if (srssets > 1)
1577 change_c0_srsmap(0xf << n*4, srs << n*4);
1578 }
1579
1580 if (srs == 0) {
1581 /*
1582 * If no shadow set is selected then use the default handler
1583 * that does normal register saving and standard interrupt exit
1584 */
1585 extern char except_vec_vi, except_vec_vi_lui;
1586 extern char except_vec_vi_ori, except_vec_vi_end;
1587 extern char rollback_except_vec_vi;
1588 char *vec_start = using_rollback_handler() ?
1589 &rollback_except_vec_vi : &except_vec_vi;
1590 #ifdef CONFIG_MIPS_MT_SMTC
1591 /*
1592 * We need to provide the SMTC vectored interrupt handler
1593 * not only with the address of the handler, but with the
1594 * Status.IM bit to be masked before going there.
1595 */
1596 extern char except_vec_vi_mori;
1597 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1598 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1599 #else
1600 const int mori_offset = &except_vec_vi_mori - vec_start;
1601 #endif
1602 #endif /* CONFIG_MIPS_MT_SMTC */
1603 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1604 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1605 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1606 #else
1607 const int lui_offset = &except_vec_vi_lui - vec_start;
1608 const int ori_offset = &except_vec_vi_ori - vec_start;
1609 #endif
1610 const int handler_len = &except_vec_vi_end - vec_start;
1611
1612 if (handler_len > VECTORSPACING) {
1613 /*
1614 * Sigh... panicing won't help as the console
1615 * is probably not configured :(
1616 */
1617 panic("VECTORSPACING too small");
1618 }
1619
1620 set_handler(((unsigned long)b - ebase), vec_start,
1621 #ifdef CONFIG_CPU_MICROMIPS
1622 (handler_len - 1));
1623 #else
1624 handler_len);
1625 #endif
1626 #ifdef CONFIG_MIPS_MT_SMTC
1627 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1628
1629 h = (u16 *)(b + mori_offset);
1630 *h = (0x100 << n);
1631 #endif /* CONFIG_MIPS_MT_SMTC */
1632 h = (u16 *)(b + lui_offset);
1633 *h = (handler >> 16) & 0xffff;
1634 h = (u16 *)(b + ori_offset);
1635 *h = (handler & 0xffff);
1636 local_flush_icache_range((unsigned long)b,
1637 (unsigned long)(b+handler_len));
1638 }
1639 else {
1640 /*
1641 * In other cases jump directly to the interrupt handler. It
1642 * is the handler's responsibility to save registers if required
1643 * (eg hi/lo) and return from the exception using "eret".
1644 */
1645 u32 insn;
1646
1647 h = (u16 *)b;
1648 /* j handler */
1649 #ifdef CONFIG_CPU_MICROMIPS
1650 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1651 #else
1652 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1653 #endif
1654 h[0] = (insn >> 16) & 0xffff;
1655 h[1] = insn & 0xffff;
1656 h[2] = 0;
1657 h[3] = 0;
1658 local_flush_icache_range((unsigned long)b,
1659 (unsigned long)(b+8));
1660 }
1661
1662 return (void *)old_handler;
1663 }
1664
1665 void *set_vi_handler(int n, vi_handler_t addr)
1666 {
1667 return set_vi_srs_handler(n, addr, 0);
1668 }
1669
1670 extern void tlb_init(void);
1671
1672 /*
1673 * Timer interrupt
1674 */
1675 int cp0_compare_irq;
1676 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1677 int cp0_compare_irq_shift;
1678
1679 /*
1680 * Performance counter IRQ or -1 if shared with timer
1681 */
1682 int cp0_perfcount_irq;
1683 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1684
1685 static int noulri;
1686
1687 static int __init ulri_disable(char *s)
1688 {
1689 pr_info("Disabling ulri\n");
1690 noulri = 1;
1691
1692 return 1;
1693 }
1694 __setup("noulri", ulri_disable);
1695
1696 void per_cpu_trap_init(bool is_boot_cpu)
1697 {
1698 unsigned int cpu = smp_processor_id();
1699 unsigned int status_set = ST0_CU0;
1700 unsigned int hwrena = cpu_hwrena_impl_bits;
1701 #ifdef CONFIG_MIPS_MT_SMTC
1702 int secondaryTC = 0;
1703 int bootTC = (cpu == 0);
1704
1705 /*
1706 * Only do per_cpu_trap_init() for first TC of Each VPE.
1707 * Note that this hack assumes that the SMTC init code
1708 * assigns TCs consecutively and in ascending order.
1709 */
1710
1711 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1712 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1713 secondaryTC = 1;
1714 #endif /* CONFIG_MIPS_MT_SMTC */
1715
1716 /*
1717 * Disable coprocessors and select 32-bit or 64-bit addressing
1718 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1719 * flag that some firmware may have left set and the TS bit (for
1720 * IP27). Set XX for ISA IV code to work.
1721 */
1722 #ifdef CONFIG_64BIT
1723 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1724 #endif
1725 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1726 status_set |= ST0_XX;
1727 if (cpu_has_dsp)
1728 status_set |= ST0_MX;
1729
1730 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1731 status_set);
1732
1733 if (cpu_has_mips_r2)
1734 hwrena |= 0x0000000f;
1735
1736 if (!noulri && cpu_has_userlocal)
1737 hwrena |= (1 << 29);
1738
1739 if (hwrena)
1740 write_c0_hwrena(hwrena);
1741
1742 #ifdef CONFIG_MIPS_MT_SMTC
1743 if (!secondaryTC) {
1744 #endif /* CONFIG_MIPS_MT_SMTC */
1745
1746 if (cpu_has_veic || cpu_has_vint) {
1747 unsigned long sr = set_c0_status(ST0_BEV);
1748 write_c0_ebase(ebase);
1749 write_c0_status(sr);
1750 /* Setting vector spacing enables EI/VI mode */
1751 change_c0_intctl(0x3e0, VECTORSPACING);
1752 }
1753 if (cpu_has_divec) {
1754 if (cpu_has_mipsmt) {
1755 unsigned int vpflags = dvpe();
1756 set_c0_cause(CAUSEF_IV);
1757 evpe(vpflags);
1758 } else
1759 set_c0_cause(CAUSEF_IV);
1760 }
1761
1762 /*
1763 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1764 *
1765 * o read IntCtl.IPTI to determine the timer interrupt
1766 * o read IntCtl.IPPCI to determine the performance counter interrupt
1767 */
1768 if (cpu_has_mips_r2) {
1769 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1770 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1771 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1772 if (cp0_perfcount_irq == cp0_compare_irq)
1773 cp0_perfcount_irq = -1;
1774 } else {
1775 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1776 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1777 cp0_perfcount_irq = -1;
1778 }
1779
1780 #ifdef CONFIG_MIPS_MT_SMTC
1781 }
1782 #endif /* CONFIG_MIPS_MT_SMTC */
1783
1784 if (!cpu_data[cpu].asid_cache)
1785 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1786
1787 atomic_inc(&init_mm.mm_count);
1788 current->active_mm = &init_mm;
1789 BUG_ON(current->mm);
1790 enter_lazy_tlb(&init_mm, current);
1791
1792 #ifdef CONFIG_MIPS_MT_SMTC
1793 if (bootTC) {
1794 #endif /* CONFIG_MIPS_MT_SMTC */
1795 /* Boot CPU's cache setup in setup_arch(). */
1796 if (!is_boot_cpu)
1797 cpu_cache_init();
1798 tlb_init();
1799 #ifdef CONFIG_MIPS_MT_SMTC
1800 } else if (!secondaryTC) {
1801 /*
1802 * First TC in non-boot VPE must do subset of tlb_init()
1803 * for MMU countrol registers.
1804 */
1805 write_c0_pagemask(PM_DEFAULT_MASK);
1806 write_c0_wired(0);
1807 }
1808 #endif /* CONFIG_MIPS_MT_SMTC */
1809 TLBMISS_HANDLER_SETUP();
1810 }
1811
1812 /* Install CPU exception handler */
1813 void set_handler(unsigned long offset, void *addr, unsigned long size)
1814 {
1815 #ifdef CONFIG_CPU_MICROMIPS
1816 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1817 #else
1818 memcpy((void *)(ebase + offset), addr, size);
1819 #endif
1820 local_flush_icache_range(ebase + offset, ebase + offset + size);
1821 }
1822
1823 static char panic_null_cerr[] =
1824 "Trying to set NULL cache error exception handler";
1825
1826 /*
1827 * Install uncached CPU exception handler.
1828 * This is suitable only for the cache error exception which is the only
1829 * exception handler that is being run uncached.
1830 */
1831 void set_uncached_handler(unsigned long offset, void *addr,
1832 unsigned long size)
1833 {
1834 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1835
1836 if (!addr)
1837 panic(panic_null_cerr);
1838
1839 memcpy((void *)(uncached_ebase + offset), addr, size);
1840 }
1841
1842 static int __initdata rdhwr_noopt;
1843 static int __init set_rdhwr_noopt(char *str)
1844 {
1845 rdhwr_noopt = 1;
1846 return 1;
1847 }
1848
1849 __setup("rdhwr_noopt", set_rdhwr_noopt);
1850
1851 void __init trap_init(void)
1852 {
1853 extern char except_vec3_generic;
1854 extern char except_vec4;
1855 extern char except_vec3_r4000;
1856 unsigned long i;
1857
1858 check_wait();
1859
1860 #if defined(CONFIG_KGDB)
1861 if (kgdb_early_setup)
1862 return; /* Already done */
1863 #endif
1864
1865 if (cpu_has_veic || cpu_has_vint) {
1866 unsigned long size = 0x200 + VECTORSPACING*64;
1867 ebase = (unsigned long)
1868 __alloc_bootmem(size, 1 << fls(size), 0);
1869 } else {
1870 #ifdef CONFIG_KVM_GUEST
1871 #define KVM_GUEST_KSEG0 0x40000000
1872 ebase = KVM_GUEST_KSEG0;
1873 #else
1874 ebase = CKSEG0;
1875 #endif
1876 if (cpu_has_mips_r2)
1877 ebase += (read_c0_ebase() & 0x3ffff000);
1878 }
1879
1880 if (cpu_has_mmips) {
1881 unsigned int config3 = read_c0_config3();
1882
1883 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
1884 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
1885 else
1886 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
1887 }
1888
1889 if (board_ebase_setup)
1890 board_ebase_setup();
1891 per_cpu_trap_init(true);
1892
1893 /*
1894 * Copy the generic exception handlers to their final destination.
1895 * This will be overriden later as suitable for a particular
1896 * configuration.
1897 */
1898 set_handler(0x180, &except_vec3_generic, 0x80);
1899
1900 /*
1901 * Setup default vectors
1902 */
1903 for (i = 0; i <= 31; i++)
1904 set_except_vector(i, handle_reserved);
1905
1906 /*
1907 * Copy the EJTAG debug exception vector handler code to it's final
1908 * destination.
1909 */
1910 if (cpu_has_ejtag && board_ejtag_handler_setup)
1911 board_ejtag_handler_setup();
1912
1913 /*
1914 * Only some CPUs have the watch exceptions.
1915 */
1916 if (cpu_has_watch)
1917 set_except_vector(23, handle_watch);
1918
1919 /*
1920 * Initialise interrupt handlers
1921 */
1922 if (cpu_has_veic || cpu_has_vint) {
1923 int nvec = cpu_has_veic ? 64 : 8;
1924 for (i = 0; i < nvec; i++)
1925 set_vi_handler(i, NULL);
1926 }
1927 else if (cpu_has_divec)
1928 set_handler(0x200, &except_vec4, 0x8);
1929
1930 /*
1931 * Some CPUs can enable/disable for cache parity detection, but does
1932 * it different ways.
1933 */
1934 parity_protection_init();
1935
1936 /*
1937 * The Data Bus Errors / Instruction Bus Errors are signaled
1938 * by external hardware. Therefore these two exceptions
1939 * may have board specific handlers.
1940 */
1941 if (board_be_init)
1942 board_be_init();
1943
1944 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
1945 : handle_int);
1946 set_except_vector(1, handle_tlbm);
1947 set_except_vector(2, handle_tlbl);
1948 set_except_vector(3, handle_tlbs);
1949
1950 set_except_vector(4, handle_adel);
1951 set_except_vector(5, handle_ades);
1952
1953 set_except_vector(6, handle_ibe);
1954 set_except_vector(7, handle_dbe);
1955
1956 set_except_vector(8, handle_sys);
1957 set_except_vector(9, handle_bp);
1958 set_except_vector(10, rdhwr_noopt ? handle_ri :
1959 (cpu_has_vtag_icache ?
1960 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1961 set_except_vector(11, handle_cpu);
1962 set_except_vector(12, handle_ov);
1963 set_except_vector(13, handle_tr);
1964
1965 if (current_cpu_type() == CPU_R6000 ||
1966 current_cpu_type() == CPU_R6000A) {
1967 /*
1968 * The R6000 is the only R-series CPU that features a machine
1969 * check exception (similar to the R4000 cache error) and
1970 * unaligned ldc1/sdc1 exception. The handlers have not been
1971 * written yet. Well, anyway there is no R6000 machine on the
1972 * current list of targets for Linux/MIPS.
1973 * (Duh, crap, there is someone with a triple R6k machine)
1974 */
1975 //set_except_vector(14, handle_mc);
1976 //set_except_vector(15, handle_ndc);
1977 }
1978
1979
1980 if (board_nmi_handler_setup)
1981 board_nmi_handler_setup();
1982
1983 if (cpu_has_fpu && !cpu_has_nofpuex)
1984 set_except_vector(15, handle_fpe);
1985
1986 set_except_vector(22, handle_mdmx);
1987
1988 if (cpu_has_mcheck)
1989 set_except_vector(24, handle_mcheck);
1990
1991 if (cpu_has_mipsmt)
1992 set_except_vector(25, handle_mt);
1993
1994 set_except_vector(26, handle_dsp);
1995
1996 if (board_cache_error_setup)
1997 board_cache_error_setup();
1998
1999 if (cpu_has_vce)
2000 /* Special exception: R4[04]00 uses also the divec space. */
2001 set_handler(0x180, &except_vec3_r4000, 0x100);
2002 else if (cpu_has_4kex)
2003 set_handler(0x180, &except_vec3_generic, 0x80);
2004 else
2005 set_handler(0x080, &except_vec3_generic, 0x80);
2006
2007 local_flush_icache_range(ebase, ebase + 0x400);
2008
2009 sort_extable(__start___dbe_table, __stop___dbe_table);
2010
2011 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2012 }
Linux kernel - Deliverables
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