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[MIPS] Rearrange show_stack, show_trace
[deliverable/linux.git] / arch / mips / kernel / traps.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
13 */
14 #include <linux/init.h>
15 #include <linux/mm.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
24
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
28 #include <asm/cpu.h>
29 #include <asm/dsp.h>
30 #include <asm/fpu.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
44
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_cpu(void);
57 extern asmlinkage void handle_ov(void);
58 extern asmlinkage void handle_tr(void);
59 extern asmlinkage void handle_fpe(void);
60 extern asmlinkage void handle_mdmx(void);
61 extern asmlinkage void handle_watch(void);
62 extern asmlinkage void handle_mt(void);
63 extern asmlinkage void handle_dsp(void);
64 extern asmlinkage void handle_mcheck(void);
65 extern asmlinkage void handle_reserved(void);
66
67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
68 struct mips_fpu_struct *ctx);
69
70 void (*board_be_init)(void);
71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
72 void (*board_nmi_handler_setup)(void);
73 void (*board_ejtag_handler_setup)(void);
74 void (*board_bind_eic_interrupt)(int irq, int regset);
75
76 /*
77 * These constant is for searching for possible module text segments.
78 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
79 */
80 #define MODULE_RANGE (8*1024*1024)
81
82 static void show_trace(unsigned long *stack)
83 {
84 const int field = 2 * sizeof(unsigned long);
85 unsigned long addr;
86
87 printk("Call Trace:");
88 #ifdef CONFIG_KALLSYMS
89 printk("\n");
90 #endif
91 while (!kstack_end(stack)) {
92 addr = *stack++;
93 if (__kernel_text_address(addr)) {
94 printk(" [<%0*lx>] ", field, addr);
95 print_symbol("%s\n", addr);
96 }
97 }
98 printk("\n");
99 }
100
101 /*
102 * This routine abuses get_user()/put_user() to reference pointers
103 * with at least a bit of error checking ...
104 */
105 void show_stack(struct task_struct *task, unsigned long *sp)
106 {
107 const int field = 2 * sizeof(unsigned long);
108 long stackdata;
109 int i;
110 unsigned long *stack;
111
112 if (!sp) {
113 if (task && task != current)
114 sp = (unsigned long *) task->thread.reg29;
115 else
116 sp = (unsigned long *) &sp;
117 }
118 stack = sp;
119
120 printk("Stack :");
121 i = 0;
122 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
123 if (i && ((i % (64 / field)) == 0))
124 printk("\n ");
125 if (i > 39) {
126 printk(" ...");
127 break;
128 }
129
130 if (__get_user(stackdata, sp++)) {
131 printk(" (Bad stack address)");
132 break;
133 }
134
135 printk(" %0*lx", field, stackdata);
136 i++;
137 }
138 printk("\n");
139 show_trace(stack);
140 }
141
142 /*
143 * The architecture-independent dump_stack generator
144 */
145 void dump_stack(void)
146 {
147 unsigned long stack;
148
149 show_trace(&stack);
150 }
151
152 EXPORT_SYMBOL(dump_stack);
153
154 void show_code(unsigned int *pc)
155 {
156 long i;
157
158 printk("\nCode:");
159
160 for(i = -3 ; i < 6 ; i++) {
161 unsigned int insn;
162 if (__get_user(insn, pc + i)) {
163 printk(" (Bad address in epc)\n");
164 break;
165 }
166 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
167 }
168 }
169
170 void show_regs(struct pt_regs *regs)
171 {
172 const int field = 2 * sizeof(unsigned long);
173 unsigned int cause = regs->cp0_cause;
174 int i;
175
176 printk("Cpu %d\n", smp_processor_id());
177
178 /*
179 * Saved main processor registers
180 */
181 for (i = 0; i < 32; ) {
182 if ((i % 4) == 0)
183 printk("$%2d :", i);
184 if (i == 0)
185 printk(" %0*lx", field, 0UL);
186 else if (i == 26 || i == 27)
187 printk(" %*s", field, "");
188 else
189 printk(" %0*lx", field, regs->regs[i]);
190
191 i++;
192 if ((i % 4) == 0)
193 printk("\n");
194 }
195
196 printk("Hi : %0*lx\n", field, regs->hi);
197 printk("Lo : %0*lx\n", field, regs->lo);
198
199 /*
200 * Saved cp0 registers
201 */
202 printk("epc : %0*lx ", field, regs->cp0_epc);
203 print_symbol("%s ", regs->cp0_epc);
204 printk(" %s\n", print_tainted());
205 printk("ra : %0*lx ", field, regs->regs[31]);
206 print_symbol("%s\n", regs->regs[31]);
207
208 printk("Status: %08x ", (uint32_t) regs->cp0_status);
209
210 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
211 if (regs->cp0_status & ST0_KUO)
212 printk("KUo ");
213 if (regs->cp0_status & ST0_IEO)
214 printk("IEo ");
215 if (regs->cp0_status & ST0_KUP)
216 printk("KUp ");
217 if (regs->cp0_status & ST0_IEP)
218 printk("IEp ");
219 if (regs->cp0_status & ST0_KUC)
220 printk("KUc ");
221 if (regs->cp0_status & ST0_IEC)
222 printk("IEc ");
223 } else {
224 if (regs->cp0_status & ST0_KX)
225 printk("KX ");
226 if (regs->cp0_status & ST0_SX)
227 printk("SX ");
228 if (regs->cp0_status & ST0_UX)
229 printk("UX ");
230 switch (regs->cp0_status & ST0_KSU) {
231 case KSU_USER:
232 printk("USER ");
233 break;
234 case KSU_SUPERVISOR:
235 printk("SUPERVISOR ");
236 break;
237 case KSU_KERNEL:
238 printk("KERNEL ");
239 break;
240 default:
241 printk("BAD_MODE ");
242 break;
243 }
244 if (regs->cp0_status & ST0_ERL)
245 printk("ERL ");
246 if (regs->cp0_status & ST0_EXL)
247 printk("EXL ");
248 if (regs->cp0_status & ST0_IE)
249 printk("IE ");
250 }
251 printk("\n");
252
253 printk("Cause : %08x\n", cause);
254
255 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
256 if (1 <= cause && cause <= 5)
257 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
258
259 printk("PrId : %08x\n", read_c0_prid());
260 }
261
262 void show_registers(struct pt_regs *regs)
263 {
264 show_regs(regs);
265 print_modules();
266 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
267 current->comm, current->pid, current_thread_info(), current);
268 show_stack(current, (long *) regs->regs[29]);
269 show_code((unsigned int *) regs->cp0_epc);
270 printk("\n");
271 }
272
273 static DEFINE_SPINLOCK(die_lock);
274
275 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
276 {
277 static int die_counter;
278 #ifdef CONFIG_MIPS_MT_SMTC
279 unsigned long dvpret = dvpe();
280 #endif /* CONFIG_MIPS_MT_SMTC */
281
282 console_verbose();
283 spin_lock_irq(&die_lock);
284 bust_spinlocks(1);
285 #ifdef CONFIG_MIPS_MT_SMTC
286 mips_mt_regdump(dvpret);
287 #endif /* CONFIG_MIPS_MT_SMTC */
288 printk("%s[#%d]:\n", str, ++die_counter);
289 show_registers(regs);
290 spin_unlock_irq(&die_lock);
291
292 if (in_interrupt())
293 panic("Fatal exception in interrupt");
294
295 if (panic_on_oops) {
296 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
297 ssleep(5);
298 panic("Fatal exception");
299 }
300
301 do_exit(SIGSEGV);
302 }
303
304 extern const struct exception_table_entry __start___dbe_table[];
305 extern const struct exception_table_entry __stop___dbe_table[];
306
307 void __declare_dbe_table(void)
308 {
309 __asm__ __volatile__(
310 ".section\t__dbe_table,\"a\"\n\t"
311 ".previous"
312 );
313 }
314
315 /* Given an address, look for it in the exception tables. */
316 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
317 {
318 const struct exception_table_entry *e;
319
320 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
321 if (!e)
322 e = search_module_dbetables(addr);
323 return e;
324 }
325
326 asmlinkage void do_be(struct pt_regs *regs)
327 {
328 const int field = 2 * sizeof(unsigned long);
329 const struct exception_table_entry *fixup = NULL;
330 int data = regs->cp0_cause & 4;
331 int action = MIPS_BE_FATAL;
332
333 /* XXX For now. Fixme, this searches the wrong table ... */
334 if (data && !user_mode(regs))
335 fixup = search_dbe_tables(exception_epc(regs));
336
337 if (fixup)
338 action = MIPS_BE_FIXUP;
339
340 if (board_be_handler)
341 action = board_be_handler(regs, fixup != 0);
342
343 switch (action) {
344 case MIPS_BE_DISCARD:
345 return;
346 case MIPS_BE_FIXUP:
347 if (fixup) {
348 regs->cp0_epc = fixup->nextinsn;
349 return;
350 }
351 break;
352 default:
353 break;
354 }
355
356 /*
357 * Assume it would be too dangerous to continue ...
358 */
359 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
360 data ? "Data" : "Instruction",
361 field, regs->cp0_epc, field, regs->regs[31]);
362 die_if_kernel("Oops", regs);
363 force_sig(SIGBUS, current);
364 }
365
366 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
367 {
368 unsigned int __user *epc;
369
370 epc = (unsigned int __user *) regs->cp0_epc +
371 ((regs->cp0_cause & CAUSEF_BD) != 0);
372 if (!get_user(*opcode, epc))
373 return 0;
374
375 force_sig(SIGSEGV, current);
376 return 1;
377 }
378
379 /*
380 * ll/sc emulation
381 */
382
383 #define OPCODE 0xfc000000
384 #define BASE 0x03e00000
385 #define RT 0x001f0000
386 #define OFFSET 0x0000ffff
387 #define LL 0xc0000000
388 #define SC 0xe0000000
389 #define SPEC3 0x7c000000
390 #define RD 0x0000f800
391 #define FUNC 0x0000003f
392 #define RDHWR 0x0000003b
393
394 /*
395 * The ll_bit is cleared by r*_switch.S
396 */
397
398 unsigned long ll_bit;
399
400 static struct task_struct *ll_task = NULL;
401
402 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
403 {
404 unsigned long value, __user *vaddr;
405 long offset;
406 int signal = 0;
407
408 /*
409 * analyse the ll instruction that just caused a ri exception
410 * and put the referenced address to addr.
411 */
412
413 /* sign extend offset */
414 offset = opcode & OFFSET;
415 offset <<= 16;
416 offset >>= 16;
417
418 vaddr = (unsigned long __user *)
419 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
420
421 if ((unsigned long)vaddr & 3) {
422 signal = SIGBUS;
423 goto sig;
424 }
425 if (get_user(value, vaddr)) {
426 signal = SIGSEGV;
427 goto sig;
428 }
429
430 preempt_disable();
431
432 if (ll_task == NULL || ll_task == current) {
433 ll_bit = 1;
434 } else {
435 ll_bit = 0;
436 }
437 ll_task = current;
438
439 preempt_enable();
440
441 compute_return_epc(regs);
442
443 regs->regs[(opcode & RT) >> 16] = value;
444
445 return;
446
447 sig:
448 force_sig(signal, current);
449 }
450
451 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
452 {
453 unsigned long __user *vaddr;
454 unsigned long reg;
455 long offset;
456 int signal = 0;
457
458 /*
459 * analyse the sc instruction that just caused a ri exception
460 * and put the referenced address to addr.
461 */
462
463 /* sign extend offset */
464 offset = opcode & OFFSET;
465 offset <<= 16;
466 offset >>= 16;
467
468 vaddr = (unsigned long __user *)
469 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
470 reg = (opcode & RT) >> 16;
471
472 if ((unsigned long)vaddr & 3) {
473 signal = SIGBUS;
474 goto sig;
475 }
476
477 preempt_disable();
478
479 if (ll_bit == 0 || ll_task != current) {
480 compute_return_epc(regs);
481 regs->regs[reg] = 0;
482 preempt_enable();
483 return;
484 }
485
486 preempt_enable();
487
488 if (put_user(regs->regs[reg], vaddr)) {
489 signal = SIGSEGV;
490 goto sig;
491 }
492
493 compute_return_epc(regs);
494 regs->regs[reg] = 1;
495
496 return;
497
498 sig:
499 force_sig(signal, current);
500 }
501
502 /*
503 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
504 * opcodes are supposed to result in coprocessor unusable exceptions if
505 * executed on ll/sc-less processors. That's the theory. In practice a
506 * few processors such as NEC's VR4100 throw reserved instruction exceptions
507 * instead, so we're doing the emulation thing in both exception handlers.
508 */
509 static inline int simulate_llsc(struct pt_regs *regs)
510 {
511 unsigned int opcode;
512
513 if (unlikely(get_insn_opcode(regs, &opcode)))
514 return -EFAULT;
515
516 if ((opcode & OPCODE) == LL) {
517 simulate_ll(regs, opcode);
518 return 0;
519 }
520 if ((opcode & OPCODE) == SC) {
521 simulate_sc(regs, opcode);
522 return 0;
523 }
524
525 return -EFAULT; /* Strange things going on ... */
526 }
527
528 /*
529 * Simulate trapping 'rdhwr' instructions to provide user accessible
530 * registers not implemented in hardware. The only current use of this
531 * is the thread area pointer.
532 */
533 static inline int simulate_rdhwr(struct pt_regs *regs)
534 {
535 struct thread_info *ti = task_thread_info(current);
536 unsigned int opcode;
537
538 if (unlikely(get_insn_opcode(regs, &opcode)))
539 return -EFAULT;
540
541 if (unlikely(compute_return_epc(regs)))
542 return -EFAULT;
543
544 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
545 int rd = (opcode & RD) >> 11;
546 int rt = (opcode & RT) >> 16;
547 switch (rd) {
548 case 29:
549 regs->regs[rt] = ti->tp_value;
550 return 0;
551 default:
552 return -EFAULT;
553 }
554 }
555
556 /* Not ours. */
557 return -EFAULT;
558 }
559
560 asmlinkage void do_ov(struct pt_regs *regs)
561 {
562 siginfo_t info;
563
564 die_if_kernel("Integer overflow", regs);
565
566 info.si_code = FPE_INTOVF;
567 info.si_signo = SIGFPE;
568 info.si_errno = 0;
569 info.si_addr = (void __user *) regs->cp0_epc;
570 force_sig_info(SIGFPE, &info, current);
571 }
572
573 /*
574 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
575 */
576 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
577 {
578 die_if_kernel("FP exception in kernel code", regs);
579
580 if (fcr31 & FPU_CSR_UNI_X) {
581 int sig;
582
583 preempt_disable();
584
585 #ifdef CONFIG_PREEMPT
586 if (!is_fpu_owner()) {
587 /* We might lose fpu before disabling preempt... */
588 own_fpu();
589 BUG_ON(!used_math());
590 restore_fp(current);
591 }
592 #endif
593 /*
594 * Unimplemented operation exception. If we've got the full
595 * software emulator on-board, let's use it...
596 *
597 * Force FPU to dump state into task/thread context. We're
598 * moving a lot of data here for what is probably a single
599 * instruction, but the alternative is to pre-decode the FP
600 * register operands before invoking the emulator, which seems
601 * a bit extreme for what should be an infrequent event.
602 */
603 save_fp(current);
604 /* Ensure 'resume' not overwrite saved fp context again. */
605 lose_fpu();
606
607 preempt_enable();
608
609 /* Run the emulator */
610 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
611
612 preempt_disable();
613
614 own_fpu(); /* Using the FPU again. */
615 /*
616 * We can't allow the emulated instruction to leave any of
617 * the cause bit set in $fcr31.
618 */
619 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
620
621 /* Restore the hardware register state */
622 restore_fp(current);
623
624 preempt_enable();
625
626 /* If something went wrong, signal */
627 if (sig)
628 force_sig(sig, current);
629
630 return;
631 }
632
633 force_sig(SIGFPE, current);
634 }
635
636 asmlinkage void do_bp(struct pt_regs *regs)
637 {
638 unsigned int opcode, bcode;
639 siginfo_t info;
640
641 die_if_kernel("Break instruction in kernel code", regs);
642
643 if (get_insn_opcode(regs, &opcode))
644 return;
645
646 /*
647 * There is the ancient bug in the MIPS assemblers that the break
648 * code starts left to bit 16 instead to bit 6 in the opcode.
649 * Gas is bug-compatible, but not always, grrr...
650 * We handle both cases with a simple heuristics. --macro
651 */
652 bcode = ((opcode >> 6) & ((1 << 20) - 1));
653 if (bcode < (1 << 10))
654 bcode <<= 10;
655
656 /*
657 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
658 * insns, even for break codes that indicate arithmetic failures.
659 * Weird ...)
660 * But should we continue the brokenness??? --macro
661 */
662 switch (bcode) {
663 case BRK_OVERFLOW << 10:
664 case BRK_DIVZERO << 10:
665 if (bcode == (BRK_DIVZERO << 10))
666 info.si_code = FPE_INTDIV;
667 else
668 info.si_code = FPE_INTOVF;
669 info.si_signo = SIGFPE;
670 info.si_errno = 0;
671 info.si_addr = (void __user *) regs->cp0_epc;
672 force_sig_info(SIGFPE, &info, current);
673 break;
674 default:
675 force_sig(SIGTRAP, current);
676 }
677 }
678
679 asmlinkage void do_tr(struct pt_regs *regs)
680 {
681 unsigned int opcode, tcode = 0;
682 siginfo_t info;
683
684 die_if_kernel("Trap instruction in kernel code", regs);
685
686 if (get_insn_opcode(regs, &opcode))
687 return;
688
689 /* Immediate versions don't provide a code. */
690 if (!(opcode & OPCODE))
691 tcode = ((opcode >> 6) & ((1 << 10) - 1));
692
693 /*
694 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
695 * insns, even for trap codes that indicate arithmetic failures.
696 * Weird ...)
697 * But should we continue the brokenness??? --macro
698 */
699 switch (tcode) {
700 case BRK_OVERFLOW:
701 case BRK_DIVZERO:
702 if (tcode == BRK_DIVZERO)
703 info.si_code = FPE_INTDIV;
704 else
705 info.si_code = FPE_INTOVF;
706 info.si_signo = SIGFPE;
707 info.si_errno = 0;
708 info.si_addr = (void __user *) regs->cp0_epc;
709 force_sig_info(SIGFPE, &info, current);
710 break;
711 default:
712 force_sig(SIGTRAP, current);
713 }
714 }
715
716 asmlinkage void do_ri(struct pt_regs *regs)
717 {
718 die_if_kernel("Reserved instruction in kernel code", regs);
719
720 if (!cpu_has_llsc)
721 if (!simulate_llsc(regs))
722 return;
723
724 if (!simulate_rdhwr(regs))
725 return;
726
727 force_sig(SIGILL, current);
728 }
729
730 asmlinkage void do_cpu(struct pt_regs *regs)
731 {
732 unsigned int cpid;
733
734 die_if_kernel("do_cpu invoked from kernel context!", regs);
735
736 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
737
738 switch (cpid) {
739 case 0:
740 if (!cpu_has_llsc)
741 if (!simulate_llsc(regs))
742 return;
743
744 if (!simulate_rdhwr(regs))
745 return;
746
747 break;
748
749 case 1:
750 preempt_disable();
751
752 own_fpu();
753 if (used_math()) { /* Using the FPU again. */
754 restore_fp(current);
755 } else { /* First time FPU user. */
756 init_fpu();
757 set_used_math();
758 }
759
760 preempt_enable();
761
762 if (!cpu_has_fpu) {
763 int sig = fpu_emulator_cop1Handler(regs,
764 &current->thread.fpu);
765 if (sig)
766 force_sig(sig, current);
767 #ifdef CONFIG_MIPS_MT_FPAFF
768 else {
769 /*
770 * MIPS MT processors may have fewer FPU contexts
771 * than CPU threads. If we've emulated more than
772 * some threshold number of instructions, force
773 * migration to a "CPU" that has FP support.
774 */
775 if(mt_fpemul_threshold > 0
776 && ((current->thread.emulated_fp++
777 > mt_fpemul_threshold))) {
778 /*
779 * If there's no FPU present, or if the
780 * application has already restricted
781 * the allowed set to exclude any CPUs
782 * with FPUs, we'll skip the procedure.
783 */
784 if (cpus_intersects(current->cpus_allowed,
785 mt_fpu_cpumask)) {
786 cpumask_t tmask;
787
788 cpus_and(tmask,
789 current->thread.user_cpus_allowed,
790 mt_fpu_cpumask);
791 set_cpus_allowed(current, tmask);
792 current->thread.mflags |= MF_FPUBOUND;
793 }
794 }
795 }
796 #endif /* CONFIG_MIPS_MT_FPAFF */
797 }
798
799 return;
800
801 case 2:
802 case 3:
803 die_if_kernel("do_cpu invoked from kernel context!", regs);
804 break;
805 }
806
807 force_sig(SIGILL, current);
808 }
809
810 asmlinkage void do_mdmx(struct pt_regs *regs)
811 {
812 force_sig(SIGILL, current);
813 }
814
815 asmlinkage void do_watch(struct pt_regs *regs)
816 {
817 /*
818 * We use the watch exception where available to detect stack
819 * overflows.
820 */
821 dump_tlb_all();
822 show_regs(regs);
823 panic("Caught WATCH exception - probably caused by stack overflow.");
824 }
825
826 asmlinkage void do_mcheck(struct pt_regs *regs)
827 {
828 const int field = 2 * sizeof(unsigned long);
829 int multi_match = regs->cp0_status & ST0_TS;
830
831 show_regs(regs);
832
833 if (multi_match) {
834 printk("Index : %0x\n", read_c0_index());
835 printk("Pagemask: %0x\n", read_c0_pagemask());
836 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
837 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
838 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
839 printk("\n");
840 dump_tlb_all();
841 }
842
843 show_code((unsigned int *) regs->cp0_epc);
844
845 /*
846 * Some chips may have other causes of machine check (e.g. SB1
847 * graduation timer)
848 */
849 panic("Caught Machine Check exception - %scaused by multiple "
850 "matching entries in the TLB.",
851 (multi_match) ? "" : "not ");
852 }
853
854 asmlinkage void do_mt(struct pt_regs *regs)
855 {
856 int subcode;
857
858 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
859 >> VPECONTROL_EXCPT_SHIFT;
860 switch (subcode) {
861 case 0:
862 printk(KERN_DEBUG "Thread Underflow\n");
863 break;
864 case 1:
865 printk(KERN_DEBUG "Thread Overflow\n");
866 break;
867 case 2:
868 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
869 break;
870 case 3:
871 printk(KERN_DEBUG "Gating Storage Exception\n");
872 break;
873 case 4:
874 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
875 break;
876 case 5:
877 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
878 break;
879 default:
880 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
881 subcode);
882 break;
883 }
884 die_if_kernel("MIPS MT Thread exception in kernel", regs);
885
886 force_sig(SIGILL, current);
887 }
888
889
890 asmlinkage void do_dsp(struct pt_regs *regs)
891 {
892 if (cpu_has_dsp)
893 panic("Unexpected DSP exception\n");
894
895 force_sig(SIGILL, current);
896 }
897
898 asmlinkage void do_reserved(struct pt_regs *regs)
899 {
900 /*
901 * Game over - no way to handle this if it ever occurs. Most probably
902 * caused by a new unknown cpu type or after another deadly
903 * hard/software error.
904 */
905 show_regs(regs);
906 panic("Caught reserved exception %ld - should not happen.",
907 (regs->cp0_cause & 0x7f) >> 2);
908 }
909
910 asmlinkage void do_default_vi(struct pt_regs *regs)
911 {
912 show_regs(regs);
913 panic("Caught unexpected vectored interrupt.");
914 }
915
916 /*
917 * Some MIPS CPUs can enable/disable for cache parity detection, but do
918 * it different ways.
919 */
920 static inline void parity_protection_init(void)
921 {
922 switch (current_cpu_data.cputype) {
923 case CPU_24K:
924 case CPU_34K:
925 case CPU_5KC:
926 write_c0_ecc(0x80000000);
927 back_to_back_c0_hazard();
928 /* Set the PE bit (bit 31) in the c0_errctl register. */
929 printk(KERN_INFO "Cache parity protection %sabled\n",
930 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
931 break;
932 case CPU_20KC:
933 case CPU_25KF:
934 /* Clear the DE bit (bit 16) in the c0_status register. */
935 printk(KERN_INFO "Enable cache parity protection for "
936 "MIPS 20KC/25KF CPUs.\n");
937 clear_c0_status(ST0_DE);
938 break;
939 default:
940 break;
941 }
942 }
943
944 asmlinkage void cache_parity_error(void)
945 {
946 const int field = 2 * sizeof(unsigned long);
947 unsigned int reg_val;
948
949 /* For the moment, report the problem and hang. */
950 printk("Cache error exception:\n");
951 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
952 reg_val = read_c0_cacheerr();
953 printk("c0_cacheerr == %08x\n", reg_val);
954
955 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
956 reg_val & (1<<30) ? "secondary" : "primary",
957 reg_val & (1<<31) ? "data" : "insn");
958 printk("Error bits: %s%s%s%s%s%s%s\n",
959 reg_val & (1<<29) ? "ED " : "",
960 reg_val & (1<<28) ? "ET " : "",
961 reg_val & (1<<26) ? "EE " : "",
962 reg_val & (1<<25) ? "EB " : "",
963 reg_val & (1<<24) ? "EI " : "",
964 reg_val & (1<<23) ? "E1 " : "",
965 reg_val & (1<<22) ? "E0 " : "");
966 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
967
968 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
969 if (reg_val & (1<<22))
970 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
971
972 if (reg_val & (1<<23))
973 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
974 #endif
975
976 panic("Can't handle the cache error!");
977 }
978
979 /*
980 * SDBBP EJTAG debug exception handler.
981 * We skip the instruction and return to the next instruction.
982 */
983 void ejtag_exception_handler(struct pt_regs *regs)
984 {
985 const int field = 2 * sizeof(unsigned long);
986 unsigned long depc, old_epc;
987 unsigned int debug;
988
989 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
990 depc = read_c0_depc();
991 debug = read_c0_debug();
992 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
993 if (debug & 0x80000000) {
994 /*
995 * In branch delay slot.
996 * We cheat a little bit here and use EPC to calculate the
997 * debug return address (DEPC). EPC is restored after the
998 * calculation.
999 */
1000 old_epc = regs->cp0_epc;
1001 regs->cp0_epc = depc;
1002 __compute_return_epc(regs);
1003 depc = regs->cp0_epc;
1004 regs->cp0_epc = old_epc;
1005 } else
1006 depc += 4;
1007 write_c0_depc(depc);
1008
1009 #if 0
1010 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1011 write_c0_debug(debug | 0x100);
1012 #endif
1013 }
1014
1015 /*
1016 * NMI exception handler.
1017 */
1018 void nmi_exception_handler(struct pt_regs *regs)
1019 {
1020 #ifdef CONFIG_MIPS_MT_SMTC
1021 unsigned long dvpret = dvpe();
1022 bust_spinlocks(1);
1023 printk("NMI taken!!!!\n");
1024 mips_mt_regdump(dvpret);
1025 #else
1026 bust_spinlocks(1);
1027 printk("NMI taken!!!!\n");
1028 #endif /* CONFIG_MIPS_MT_SMTC */
1029 die("NMI", regs);
1030 while(1) ;
1031 }
1032
1033 #define VECTORSPACING 0x100 /* for EI/VI mode */
1034
1035 unsigned long ebase;
1036 unsigned long exception_handlers[32];
1037 unsigned long vi_handlers[64];
1038
1039 /*
1040 * As a side effect of the way this is implemented we're limited
1041 * to interrupt handlers in the address range from
1042 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1043 */
1044 void *set_except_vector(int n, void *addr)
1045 {
1046 unsigned long handler = (unsigned long) addr;
1047 unsigned long old_handler = exception_handlers[n];
1048
1049 exception_handlers[n] = handler;
1050 if (n == 0 && cpu_has_divec) {
1051 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1052 (0x03ffffff & (handler >> 2));
1053 flush_icache_range(ebase + 0x200, ebase + 0x204);
1054 }
1055 return (void *)old_handler;
1056 }
1057
1058 #ifdef CONFIG_CPU_MIPSR2_SRS
1059 /*
1060 * MIPSR2 shadow register set allocation
1061 * FIXME: SMP...
1062 */
1063
1064 static struct shadow_registers {
1065 /*
1066 * Number of shadow register sets supported
1067 */
1068 unsigned long sr_supported;
1069 /*
1070 * Bitmap of allocated shadow registers
1071 */
1072 unsigned long sr_allocated;
1073 } shadow_registers;
1074
1075 static void mips_srs_init(void)
1076 {
1077 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1078 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1079 shadow_registers.sr_supported);
1080 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1081 }
1082
1083 int mips_srs_max(void)
1084 {
1085 return shadow_registers.sr_supported;
1086 }
1087
1088 int mips_srs_alloc(void)
1089 {
1090 struct shadow_registers *sr = &shadow_registers;
1091 int set;
1092
1093 again:
1094 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1095 if (set >= sr->sr_supported)
1096 return -1;
1097
1098 if (test_and_set_bit(set, &sr->sr_allocated))
1099 goto again;
1100
1101 return set;
1102 }
1103
1104 void mips_srs_free(int set)
1105 {
1106 struct shadow_registers *sr = &shadow_registers;
1107
1108 clear_bit(set, &sr->sr_allocated);
1109 }
1110
1111 static void *set_vi_srs_handler(int n, void *addr, int srs)
1112 {
1113 unsigned long handler;
1114 unsigned long old_handler = vi_handlers[n];
1115 u32 *w;
1116 unsigned char *b;
1117
1118 if (!cpu_has_veic && !cpu_has_vint)
1119 BUG();
1120
1121 if (addr == NULL) {
1122 handler = (unsigned long) do_default_vi;
1123 srs = 0;
1124 } else
1125 handler = (unsigned long) addr;
1126 vi_handlers[n] = (unsigned long) addr;
1127
1128 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1129
1130 if (srs >= mips_srs_max())
1131 panic("Shadow register set %d not supported", srs);
1132
1133 if (cpu_has_veic) {
1134 if (board_bind_eic_interrupt)
1135 board_bind_eic_interrupt (n, srs);
1136 } else if (cpu_has_vint) {
1137 /* SRSMap is only defined if shadow sets are implemented */
1138 if (mips_srs_max() > 1)
1139 change_c0_srsmap (0xf << n*4, srs << n*4);
1140 }
1141
1142 if (srs == 0) {
1143 /*
1144 * If no shadow set is selected then use the default handler
1145 * that does normal register saving and a standard interrupt exit
1146 */
1147
1148 extern char except_vec_vi, except_vec_vi_lui;
1149 extern char except_vec_vi_ori, except_vec_vi_end;
1150 #ifdef CONFIG_MIPS_MT_SMTC
1151 /*
1152 * We need to provide the SMTC vectored interrupt handler
1153 * not only with the address of the handler, but with the
1154 * Status.IM bit to be masked before going there.
1155 */
1156 extern char except_vec_vi_mori;
1157 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1158 #endif /* CONFIG_MIPS_MT_SMTC */
1159 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1160 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1161 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1162
1163 if (handler_len > VECTORSPACING) {
1164 /*
1165 * Sigh... panicing won't help as the console
1166 * is probably not configured :(
1167 */
1168 panic ("VECTORSPACING too small");
1169 }
1170
1171 memcpy (b, &except_vec_vi, handler_len);
1172 #ifdef CONFIG_MIPS_MT_SMTC
1173 if (n > 7)
1174 printk("Vector index %d exceeds SMTC maximum\n", n);
1175 w = (u32 *)(b + mori_offset);
1176 *w = (*w & 0xffff0000) | (0x100 << n);
1177 #endif /* CONFIG_MIPS_MT_SMTC */
1178 w = (u32 *)(b + lui_offset);
1179 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1180 w = (u32 *)(b + ori_offset);
1181 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1182 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1183 }
1184 else {
1185 /*
1186 * In other cases jump directly to the interrupt handler
1187 *
1188 * It is the handlers responsibility to save registers if required
1189 * (eg hi/lo) and return from the exception using "eret"
1190 */
1191 w = (u32 *)b;
1192 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1193 *w = 0;
1194 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1195 }
1196
1197 return (void *)old_handler;
1198 }
1199
1200 void *set_vi_handler(int n, void *addr)
1201 {
1202 return set_vi_srs_handler(n, addr, 0);
1203 }
1204
1205 #else
1206
1207 static inline void mips_srs_init(void)
1208 {
1209 }
1210
1211 #endif /* CONFIG_CPU_MIPSR2_SRS */
1212
1213 /*
1214 * This is used by native signal handling
1215 */
1216 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1217 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1218
1219 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1220 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1221
1222 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1223 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1224
1225 #ifdef CONFIG_SMP
1226 static int smp_save_fp_context(struct sigcontext *sc)
1227 {
1228 return cpu_has_fpu
1229 ? _save_fp_context(sc)
1230 : fpu_emulator_save_context(sc);
1231 }
1232
1233 static int smp_restore_fp_context(struct sigcontext *sc)
1234 {
1235 return cpu_has_fpu
1236 ? _restore_fp_context(sc)
1237 : fpu_emulator_restore_context(sc);
1238 }
1239 #endif
1240
1241 static inline void signal_init(void)
1242 {
1243 #ifdef CONFIG_SMP
1244 /* For now just do the cpu_has_fpu check when the functions are invoked */
1245 save_fp_context = smp_save_fp_context;
1246 restore_fp_context = smp_restore_fp_context;
1247 #else
1248 if (cpu_has_fpu) {
1249 save_fp_context = _save_fp_context;
1250 restore_fp_context = _restore_fp_context;
1251 } else {
1252 save_fp_context = fpu_emulator_save_context;
1253 restore_fp_context = fpu_emulator_restore_context;
1254 }
1255 #endif
1256 }
1257
1258 #ifdef CONFIG_MIPS32_COMPAT
1259
1260 /*
1261 * This is used by 32-bit signal stuff on the 64-bit kernel
1262 */
1263 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1264 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1265
1266 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1267 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1268
1269 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1270 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1271
1272 static inline void signal32_init(void)
1273 {
1274 if (cpu_has_fpu) {
1275 save_fp_context32 = _save_fp_context32;
1276 restore_fp_context32 = _restore_fp_context32;
1277 } else {
1278 save_fp_context32 = fpu_emulator_save_context32;
1279 restore_fp_context32 = fpu_emulator_restore_context32;
1280 }
1281 }
1282 #endif
1283
1284 extern void cpu_cache_init(void);
1285 extern void tlb_init(void);
1286 extern void flush_tlb_handlers(void);
1287
1288 void __init per_cpu_trap_init(void)
1289 {
1290 unsigned int cpu = smp_processor_id();
1291 unsigned int status_set = ST0_CU0;
1292 #ifdef CONFIG_MIPS_MT_SMTC
1293 int secondaryTC = 0;
1294 int bootTC = (cpu == 0);
1295
1296 /*
1297 * Only do per_cpu_trap_init() for first TC of Each VPE.
1298 * Note that this hack assumes that the SMTC init code
1299 * assigns TCs consecutively and in ascending order.
1300 */
1301
1302 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1303 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1304 secondaryTC = 1;
1305 #endif /* CONFIG_MIPS_MT_SMTC */
1306
1307 /*
1308 * Disable coprocessors and select 32-bit or 64-bit addressing
1309 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1310 * flag that some firmware may have left set and the TS bit (for
1311 * IP27). Set XX for ISA IV code to work.
1312 */
1313 #ifdef CONFIG_64BIT
1314 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1315 #endif
1316 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1317 status_set |= ST0_XX;
1318 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1319 status_set);
1320
1321 if (cpu_has_dsp)
1322 set_c0_status(ST0_MX);
1323
1324 #ifdef CONFIG_CPU_MIPSR2
1325 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1326 #endif
1327
1328 #ifdef CONFIG_MIPS_MT_SMTC
1329 if (!secondaryTC) {
1330 #endif /* CONFIG_MIPS_MT_SMTC */
1331
1332 /*
1333 * Interrupt handling.
1334 */
1335 if (cpu_has_veic || cpu_has_vint) {
1336 write_c0_ebase (ebase);
1337 /* Setting vector spacing enables EI/VI mode */
1338 change_c0_intctl (0x3e0, VECTORSPACING);
1339 }
1340 if (cpu_has_divec) {
1341 if (cpu_has_mipsmt) {
1342 unsigned int vpflags = dvpe();
1343 set_c0_cause(CAUSEF_IV);
1344 evpe(vpflags);
1345 } else
1346 set_c0_cause(CAUSEF_IV);
1347 }
1348 #ifdef CONFIG_MIPS_MT_SMTC
1349 }
1350 #endif /* CONFIG_MIPS_MT_SMTC */
1351
1352 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1353 TLBMISS_HANDLER_SETUP();
1354
1355 atomic_inc(&init_mm.mm_count);
1356 current->active_mm = &init_mm;
1357 BUG_ON(current->mm);
1358 enter_lazy_tlb(&init_mm, current);
1359
1360 #ifdef CONFIG_MIPS_MT_SMTC
1361 if (bootTC) {
1362 #endif /* CONFIG_MIPS_MT_SMTC */
1363 cpu_cache_init();
1364 tlb_init();
1365 #ifdef CONFIG_MIPS_MT_SMTC
1366 }
1367 #endif /* CONFIG_MIPS_MT_SMTC */
1368 }
1369
1370 /* Install CPU exception handler */
1371 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1372 {
1373 memcpy((void *)(ebase + offset), addr, size);
1374 flush_icache_range(ebase + offset, ebase + offset + size);
1375 }
1376
1377 /* Install uncached CPU exception handler */
1378 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1379 {
1380 #ifdef CONFIG_32BIT
1381 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1382 #endif
1383 #ifdef CONFIG_64BIT
1384 unsigned long uncached_ebase = TO_UNCAC(ebase);
1385 #endif
1386
1387 memcpy((void *)(uncached_ebase + offset), addr, size);
1388 }
1389
1390 void __init trap_init(void)
1391 {
1392 extern char except_vec3_generic, except_vec3_r4000;
1393 extern char except_vec4;
1394 unsigned long i;
1395
1396 if (cpu_has_veic || cpu_has_vint)
1397 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1398 else
1399 ebase = CAC_BASE;
1400
1401 mips_srs_init();
1402
1403 per_cpu_trap_init();
1404
1405 /*
1406 * Copy the generic exception handlers to their final destination.
1407 * This will be overriden later as suitable for a particular
1408 * configuration.
1409 */
1410 set_handler(0x180, &except_vec3_generic, 0x80);
1411
1412 /*
1413 * Setup default vectors
1414 */
1415 for (i = 0; i <= 31; i++)
1416 set_except_vector(i, handle_reserved);
1417
1418 /*
1419 * Copy the EJTAG debug exception vector handler code to it's final
1420 * destination.
1421 */
1422 if (cpu_has_ejtag && board_ejtag_handler_setup)
1423 board_ejtag_handler_setup ();
1424
1425 /*
1426 * Only some CPUs have the watch exceptions.
1427 */
1428 if (cpu_has_watch)
1429 set_except_vector(23, handle_watch);
1430
1431 /*
1432 * Initialise interrupt handlers
1433 */
1434 if (cpu_has_veic || cpu_has_vint) {
1435 int nvec = cpu_has_veic ? 64 : 8;
1436 for (i = 0; i < nvec; i++)
1437 set_vi_handler(i, NULL);
1438 }
1439 else if (cpu_has_divec)
1440 set_handler(0x200, &except_vec4, 0x8);
1441
1442 /*
1443 * Some CPUs can enable/disable for cache parity detection, but does
1444 * it different ways.
1445 */
1446 parity_protection_init();
1447
1448 /*
1449 * The Data Bus Errors / Instruction Bus Errors are signaled
1450 * by external hardware. Therefore these two exceptions
1451 * may have board specific handlers.
1452 */
1453 if (board_be_init)
1454 board_be_init();
1455
1456 set_except_vector(0, handle_int);
1457 set_except_vector(1, handle_tlbm);
1458 set_except_vector(2, handle_tlbl);
1459 set_except_vector(3, handle_tlbs);
1460
1461 set_except_vector(4, handle_adel);
1462 set_except_vector(5, handle_ades);
1463
1464 set_except_vector(6, handle_ibe);
1465 set_except_vector(7, handle_dbe);
1466
1467 set_except_vector(8, handle_sys);
1468 set_except_vector(9, handle_bp);
1469 set_except_vector(10, handle_ri);
1470 set_except_vector(11, handle_cpu);
1471 set_except_vector(12, handle_ov);
1472 set_except_vector(13, handle_tr);
1473
1474 if (current_cpu_data.cputype == CPU_R6000 ||
1475 current_cpu_data.cputype == CPU_R6000A) {
1476 /*
1477 * The R6000 is the only R-series CPU that features a machine
1478 * check exception (similar to the R4000 cache error) and
1479 * unaligned ldc1/sdc1 exception. The handlers have not been
1480 * written yet. Well, anyway there is no R6000 machine on the
1481 * current list of targets for Linux/MIPS.
1482 * (Duh, crap, there is someone with a triple R6k machine)
1483 */
1484 //set_except_vector(14, handle_mc);
1485 //set_except_vector(15, handle_ndc);
1486 }
1487
1488
1489 if (board_nmi_handler_setup)
1490 board_nmi_handler_setup();
1491
1492 if (cpu_has_fpu && !cpu_has_nofpuex)
1493 set_except_vector(15, handle_fpe);
1494
1495 set_except_vector(22, handle_mdmx);
1496
1497 if (cpu_has_mcheck)
1498 set_except_vector(24, handle_mcheck);
1499
1500 if (cpu_has_mipsmt)
1501 set_except_vector(25, handle_mt);
1502
1503 if (cpu_has_dsp)
1504 set_except_vector(26, handle_dsp);
1505
1506 if (cpu_has_vce)
1507 /* Special exception: R4[04]00 uses also the divec space. */
1508 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1509 else if (cpu_has_4kex)
1510 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1511 else
1512 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1513
1514 signal_init();
1515 #ifdef CONFIG_MIPS32_COMPAT
1516 signal32_init();
1517 #endif
1518
1519 flush_icache_range(ebase, ebase + 0x400);
1520 flush_tlb_handlers();
1521 }
Linux kernel - Deliverables
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