2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bug.h>
16 #include <linux/compiler.h>
17 #include <linux/context_tracking.h>
18 #include <linux/cpu_pm.h>
19 #include <linux/kexec.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/spinlock.h>
27 #include <linux/kallsyms.h>
28 #include <linux/bootmem.h>
29 #include <linux/interrupt.h>
30 #include <linux/ptrace.h>
31 #include <linux/kgdb.h>
32 #include <linux/kdebug.h>
33 #include <linux/kprobes.h>
34 #include <linux/notifier.h>
35 #include <linux/kdb.h>
36 #include <linux/irq.h>
37 #include <linux/perf_event.h>
39 #include <asm/bootinfo.h>
40 #include <asm/branch.h>
41 #include <asm/break.h>
44 #include <asm/cpu-type.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/mips-r2-to-r6-emul.h>
50 #include <asm/mipsregs.h>
51 #include <asm/mipsmtregs.h>
52 #include <asm/module.h>
54 #include <asm/pgtable.h>
55 #include <asm/ptrace.h>
56 #include <asm/sections.h>
57 #include <asm/tlbdebug.h>
58 #include <asm/traps.h>
59 #include <asm/uaccess.h>
60 #include <asm/watch.h>
61 #include <asm/mmu_context.h>
62 #include <asm/types.h>
63 #include <asm/stacktrace.h>
66 extern void check_wait(void);
67 extern asmlinkage
void rollback_handle_int(void);
68 extern asmlinkage
void handle_int(void);
69 extern u32 handle_tlbl
[];
70 extern u32 handle_tlbs
[];
71 extern u32 handle_tlbm
[];
72 extern asmlinkage
void handle_adel(void);
73 extern asmlinkage
void handle_ades(void);
74 extern asmlinkage
void handle_ibe(void);
75 extern asmlinkage
void handle_dbe(void);
76 extern asmlinkage
void handle_sys(void);
77 extern asmlinkage
void handle_bp(void);
78 extern asmlinkage
void handle_ri(void);
79 extern asmlinkage
void handle_ri_rdhwr_vivt(void);
80 extern asmlinkage
void handle_ri_rdhwr(void);
81 extern asmlinkage
void handle_cpu(void);
82 extern asmlinkage
void handle_ov(void);
83 extern asmlinkage
void handle_tr(void);
84 extern asmlinkage
void handle_msa_fpe(void);
85 extern asmlinkage
void handle_fpe(void);
86 extern asmlinkage
void handle_ftlb(void);
87 extern asmlinkage
void handle_msa(void);
88 extern asmlinkage
void handle_mdmx(void);
89 extern asmlinkage
void handle_watch(void);
90 extern asmlinkage
void handle_mt(void);
91 extern asmlinkage
void handle_dsp(void);
92 extern asmlinkage
void handle_mcheck(void);
93 extern asmlinkage
void handle_reserved(void);
94 extern void tlb_do_page_fault_0(void);
96 void (*board_be_init
)(void);
97 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
98 void (*board_nmi_handler_setup
)(void);
99 void (*board_ejtag_handler_setup
)(void);
100 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
101 void (*board_ebase_setup
)(void);
102 void(*board_cache_error_setup
)(void);
104 static void show_raw_backtrace(unsigned long reg29
)
106 unsigned long *sp
= (unsigned long *)(reg29
& ~3);
109 printk("Call Trace:");
110 #ifdef CONFIG_KALLSYMS
113 while (!kstack_end(sp
)) {
114 unsigned long __user
*p
=
115 (unsigned long __user
*)(unsigned long)sp
++;
116 if (__get_user(addr
, p
)) {
117 printk(" (Bad stack address)");
120 if (__kernel_text_address(addr
))
126 #ifdef CONFIG_KALLSYMS
128 static int __init
set_raw_show_trace(char *str
)
133 __setup("raw_show_trace", set_raw_show_trace
);
136 static void show_backtrace(struct task_struct
*task
, const struct pt_regs
*regs
)
138 unsigned long sp
= regs
->regs
[29];
139 unsigned long ra
= regs
->regs
[31];
140 unsigned long pc
= regs
->cp0_epc
;
145 if (raw_show_trace
|| !__kernel_text_address(pc
)) {
146 show_raw_backtrace(sp
);
149 printk("Call Trace:\n");
152 pc
= unwind_stack(task
, &sp
, pc
, &ra
);
158 * This routine abuses get_user()/put_user() to reference pointers
159 * with at least a bit of error checking ...
161 static void show_stacktrace(struct task_struct
*task
,
162 const struct pt_regs
*regs
)
164 const int field
= 2 * sizeof(unsigned long);
167 unsigned long __user
*sp
= (unsigned long __user
*)regs
->regs
[29];
171 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
172 if (i
&& ((i
% (64 / field
)) == 0))
179 if (__get_user(stackdata
, sp
++)) {
180 printk(" (Bad stack address)");
184 printk(" %0*lx", field
, stackdata
);
188 show_backtrace(task
, regs
);
191 void show_stack(struct task_struct
*task
, unsigned long *sp
)
195 regs
.regs
[29] = (unsigned long)sp
;
199 if (task
&& task
!= current
) {
200 regs
.regs
[29] = task
->thread
.reg29
;
202 regs
.cp0_epc
= task
->thread
.reg31
;
203 #ifdef CONFIG_KGDB_KDB
204 } else if (atomic_read(&kgdb_active
) != -1 &&
206 memcpy(®s
, kdb_current_regs
, sizeof(regs
));
207 #endif /* CONFIG_KGDB_KDB */
209 prepare_frametrace(®s
);
212 show_stacktrace(task
, ®s
);
215 static void show_code(unsigned int __user
*pc
)
218 unsigned short __user
*pc16
= NULL
;
222 if ((unsigned long)pc
& 1)
223 pc16
= (unsigned short __user
*)((unsigned long)pc
& ~1);
224 for(i
= -3 ; i
< 6 ; i
++) {
226 if (pc16
? __get_user(insn
, pc16
+ i
) : __get_user(insn
, pc
+ i
)) {
227 printk(" (Bad address in epc)\n");
230 printk("%c%0*x%c", (i
?' ':'<'), pc16
? 4 : 8, insn
, (i
?' ':'>'));
234 static void __show_regs(const struct pt_regs
*regs
)
236 const int field
= 2 * sizeof(unsigned long);
237 unsigned int cause
= regs
->cp0_cause
;
240 show_regs_print_info(KERN_DEFAULT
);
243 * Saved main processor registers
245 for (i
= 0; i
< 32; ) {
249 printk(" %0*lx", field
, 0UL);
250 else if (i
== 26 || i
== 27)
251 printk(" %*s", field
, "");
253 printk(" %0*lx", field
, regs
->regs
[i
]);
260 #ifdef CONFIG_CPU_HAS_SMARTMIPS
261 printk("Acx : %0*lx\n", field
, regs
->acx
);
263 printk("Hi : %0*lx\n", field
, regs
->hi
);
264 printk("Lo : %0*lx\n", field
, regs
->lo
);
267 * Saved cp0 registers
269 printk("epc : %0*lx %pS\n", field
, regs
->cp0_epc
,
270 (void *) regs
->cp0_epc
);
271 printk(" %s\n", print_tainted());
272 printk("ra : %0*lx %pS\n", field
, regs
->regs
[31],
273 (void *) regs
->regs
[31]);
275 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
278 if (regs
->cp0_status
& ST0_KUO
)
280 if (regs
->cp0_status
& ST0_IEO
)
282 if (regs
->cp0_status
& ST0_KUP
)
284 if (regs
->cp0_status
& ST0_IEP
)
286 if (regs
->cp0_status
& ST0_KUC
)
288 if (regs
->cp0_status
& ST0_IEC
)
290 } else if (cpu_has_4kex
) {
291 if (regs
->cp0_status
& ST0_KX
)
293 if (regs
->cp0_status
& ST0_SX
)
295 if (regs
->cp0_status
& ST0_UX
)
297 switch (regs
->cp0_status
& ST0_KSU
) {
302 printk("SUPERVISOR ");
311 if (regs
->cp0_status
& ST0_ERL
)
313 if (regs
->cp0_status
& ST0_EXL
)
315 if (regs
->cp0_status
& ST0_IE
)
320 printk("Cause : %08x\n", cause
);
322 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
323 if (1 <= cause
&& cause
<= 5)
324 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
326 printk("PrId : %08x (%s)\n", read_c0_prid(),
331 * FIXME: really the generic show_regs should take a const pointer argument.
333 void show_regs(struct pt_regs
*regs
)
335 __show_regs((struct pt_regs
*)regs
);
338 void show_registers(struct pt_regs
*regs
)
340 const int field
= 2 * sizeof(unsigned long);
341 mm_segment_t old_fs
= get_fs();
345 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
346 current
->comm
, current
->pid
, current_thread_info(), current
,
347 field
, current_thread_info()->tp_value
);
348 if (cpu_has_userlocal
) {
351 tls
= read_c0_userlocal();
352 if (tls
!= current_thread_info()->tp_value
)
353 printk("*HwTLS: %0*lx\n", field
, tls
);
356 if (!user_mode(regs
))
357 /* Necessary for getting the correct stack content */
359 show_stacktrace(current
, regs
);
360 show_code((unsigned int __user
*) regs
->cp0_epc
);
365 static int regs_to_trapnr(struct pt_regs
*regs
)
367 return (regs
->cp0_cause
>> 2) & 0x1f;
370 static DEFINE_RAW_SPINLOCK(die_lock
);
372 void __noreturn
die(const char *str
, struct pt_regs
*regs
)
374 static int die_counter
;
379 if (notify_die(DIE_OOPS
, str
, regs
, 0, regs_to_trapnr(regs
),
380 SIGSEGV
) == NOTIFY_STOP
)
384 raw_spin_lock_irq(&die_lock
);
387 printk("%s[#%d]:\n", str
, ++die_counter
);
388 show_registers(regs
);
389 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
390 raw_spin_unlock_irq(&die_lock
);
395 panic("Fatal exception in interrupt");
398 printk(KERN_EMERG
"Fatal exception: panic in 5 seconds");
400 panic("Fatal exception");
403 if (regs
&& kexec_should_crash(current
))
409 extern struct exception_table_entry __start___dbe_table
[];
410 extern struct exception_table_entry __stop___dbe_table
[];
413 " .section __dbe_table, \"a\"\n"
416 /* Given an address, look for it in the exception tables. */
417 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
419 const struct exception_table_entry
*e
;
421 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
423 e
= search_module_dbetables(addr
);
427 asmlinkage
void do_be(struct pt_regs
*regs
)
429 const int field
= 2 * sizeof(unsigned long);
430 const struct exception_table_entry
*fixup
= NULL
;
431 int data
= regs
->cp0_cause
& 4;
432 int action
= MIPS_BE_FATAL
;
433 enum ctx_state prev_state
;
435 prev_state
= exception_enter();
436 /* XXX For now. Fixme, this searches the wrong table ... */
437 if (data
&& !user_mode(regs
))
438 fixup
= search_dbe_tables(exception_epc(regs
));
441 action
= MIPS_BE_FIXUP
;
443 if (board_be_handler
)
444 action
= board_be_handler(regs
, fixup
!= NULL
);
447 case MIPS_BE_DISCARD
:
451 regs
->cp0_epc
= fixup
->nextinsn
;
460 * Assume it would be too dangerous to continue ...
462 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
463 data
? "Data" : "Instruction",
464 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
465 if (notify_die(DIE_OOPS
, "bus error", regs
, 0, regs_to_trapnr(regs
),
466 SIGBUS
) == NOTIFY_STOP
)
469 die_if_kernel("Oops", regs
);
470 force_sig(SIGBUS
, current
);
473 exception_exit(prev_state
);
477 * ll/sc, rdhwr, sync emulation
480 #define OPCODE 0xfc000000
481 #define BASE 0x03e00000
482 #define RT 0x001f0000
483 #define OFFSET 0x0000ffff
484 #define LL 0xc0000000
485 #define SC 0xe0000000
486 #define SPEC0 0x00000000
487 #define SPEC3 0x7c000000
488 #define RD 0x0000f800
489 #define FUNC 0x0000003f
490 #define SYNC 0x0000000f
491 #define RDHWR 0x0000003b
493 /* microMIPS definitions */
494 #define MM_POOL32A_FUNC 0xfc00ffff
495 #define MM_RDHWR 0x00006b3c
496 #define MM_RS 0x001f0000
497 #define MM_RT 0x03e00000
500 * The ll_bit is cleared by r*_switch.S
504 struct task_struct
*ll_task
;
506 static inline int simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
508 unsigned long value
, __user
*vaddr
;
512 * analyse the ll instruction that just caused a ri exception
513 * and put the referenced address to addr.
516 /* sign extend offset */
517 offset
= opcode
& OFFSET
;
521 vaddr
= (unsigned long __user
*)
522 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
524 if ((unsigned long)vaddr
& 3)
526 if (get_user(value
, vaddr
))
531 if (ll_task
== NULL
|| ll_task
== current
) {
540 regs
->regs
[(opcode
& RT
) >> 16] = value
;
545 static inline int simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
547 unsigned long __user
*vaddr
;
552 * analyse the sc instruction that just caused a ri exception
553 * and put the referenced address to addr.
556 /* sign extend offset */
557 offset
= opcode
& OFFSET
;
561 vaddr
= (unsigned long __user
*)
562 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
563 reg
= (opcode
& RT
) >> 16;
565 if ((unsigned long)vaddr
& 3)
570 if (ll_bit
== 0 || ll_task
!= current
) {
578 if (put_user(regs
->regs
[reg
], vaddr
))
587 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
588 * opcodes are supposed to result in coprocessor unusable exceptions if
589 * executed on ll/sc-less processors. That's the theory. In practice a
590 * few processors such as NEC's VR4100 throw reserved instruction exceptions
591 * instead, so we're doing the emulation thing in both exception handlers.
593 static int simulate_llsc(struct pt_regs
*regs
, unsigned int opcode
)
595 if ((opcode
& OPCODE
) == LL
) {
596 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
598 return simulate_ll(regs
, opcode
);
600 if ((opcode
& OPCODE
) == SC
) {
601 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
603 return simulate_sc(regs
, opcode
);
606 return -1; /* Must be something else ... */
610 * Simulate trapping 'rdhwr' instructions to provide user accessible
611 * registers not implemented in hardware.
613 static int simulate_rdhwr(struct pt_regs
*regs
, int rd
, int rt
)
615 struct thread_info
*ti
= task_thread_info(current
);
617 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
620 case 0: /* CPU number */
621 regs
->regs
[rt
] = smp_processor_id();
623 case 1: /* SYNCI length */
624 regs
->regs
[rt
] = min(current_cpu_data
.dcache
.linesz
,
625 current_cpu_data
.icache
.linesz
);
627 case 2: /* Read count register */
628 regs
->regs
[rt
] = read_c0_count();
630 case 3: /* Count register resolution */
631 switch (current_cpu_type()) {
641 regs
->regs
[rt
] = ti
->tp_value
;
648 static int simulate_rdhwr_normal(struct pt_regs
*regs
, unsigned int opcode
)
650 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
651 int rd
= (opcode
& RD
) >> 11;
652 int rt
= (opcode
& RT
) >> 16;
654 simulate_rdhwr(regs
, rd
, rt
);
662 static int simulate_rdhwr_mm(struct pt_regs
*regs
, unsigned short opcode
)
664 if ((opcode
& MM_POOL32A_FUNC
) == MM_RDHWR
) {
665 int rd
= (opcode
& MM_RS
) >> 16;
666 int rt
= (opcode
& MM_RT
) >> 21;
667 simulate_rdhwr(regs
, rd
, rt
);
675 static int simulate_sync(struct pt_regs
*regs
, unsigned int opcode
)
677 if ((opcode
& OPCODE
) == SPEC0
&& (opcode
& FUNC
) == SYNC
) {
678 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
683 return -1; /* Must be something else ... */
686 asmlinkage
void do_ov(struct pt_regs
*regs
)
688 enum ctx_state prev_state
;
691 prev_state
= exception_enter();
692 die_if_kernel("Integer overflow", regs
);
694 info
.si_code
= FPE_INTOVF
;
695 info
.si_signo
= SIGFPE
;
697 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
698 force_sig_info(SIGFPE
, &info
, current
);
699 exception_exit(prev_state
);
702 int process_fpemu_return(int sig
, void __user
*fault_addr
)
704 if (sig
== SIGSEGV
|| sig
== SIGBUS
) {
705 struct siginfo si
= {0};
706 si
.si_addr
= fault_addr
;
708 if (sig
== SIGSEGV
) {
709 down_read(¤t
->mm
->mmap_sem
);
710 if (find_vma(current
->mm
, (unsigned long)fault_addr
))
711 si
.si_code
= SEGV_ACCERR
;
713 si
.si_code
= SEGV_MAPERR
;
714 up_read(¤t
->mm
->mmap_sem
);
716 si
.si_code
= BUS_ADRERR
;
718 force_sig_info(sig
, &si
, current
);
721 force_sig(sig
, current
);
728 static int simulate_fp(struct pt_regs
*regs
, unsigned int opcode
,
729 unsigned long old_epc
, unsigned long old_ra
)
731 union mips_instruction inst
= { .word
= opcode
};
732 void __user
*fault_addr
= NULL
;
735 /* If it's obviously not an FP instruction, skip it */
736 switch (inst
.i_format
.opcode
) {
750 * do_ri skipped over the instruction via compute_return_epc, undo
751 * that for the FPU emulator.
753 regs
->cp0_epc
= old_epc
;
754 regs
->regs
[31] = old_ra
;
756 /* Save the FP context to struct thread_struct */
759 /* Run the emulator */
760 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1,
763 /* If something went wrong, signal */
764 process_fpemu_return(sig
, fault_addr
);
766 /* Restore the hardware register state */
773 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
775 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
777 enum ctx_state prev_state
;
778 siginfo_t info
= {0};
780 prev_state
= exception_enter();
781 if (notify_die(DIE_FP
, "FP exception", regs
, 0, regs_to_trapnr(regs
),
782 SIGFPE
) == NOTIFY_STOP
)
784 die_if_kernel("FP exception in kernel code", regs
);
786 if (fcr31
& FPU_CSR_UNI_X
) {
788 void __user
*fault_addr
= NULL
;
791 * Unimplemented operation exception. If we've got the full
792 * software emulator on-board, let's use it...
794 * Force FPU to dump state into task/thread context. We're
795 * moving a lot of data here for what is probably a single
796 * instruction, but the alternative is to pre-decode the FP
797 * register operands before invoking the emulator, which seems
798 * a bit extreme for what should be an infrequent event.
800 /* Ensure 'resume' not overwrite saved fp context again. */
803 /* Run the emulator */
804 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1,
808 * We can't allow the emulated instruction to leave any of
809 * the cause bit set in $fcr31.
811 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
813 /* Restore the hardware register state */
814 own_fpu(1); /* Using the FPU again. */
816 /* If something went wrong, signal */
817 process_fpemu_return(sig
, fault_addr
);
820 } else if (fcr31
& FPU_CSR_INV_X
)
821 info
.si_code
= FPE_FLTINV
;
822 else if (fcr31
& FPU_CSR_DIV_X
)
823 info
.si_code
= FPE_FLTDIV
;
824 else if (fcr31
& FPU_CSR_OVF_X
)
825 info
.si_code
= FPE_FLTOVF
;
826 else if (fcr31
& FPU_CSR_UDF_X
)
827 info
.si_code
= FPE_FLTUND
;
828 else if (fcr31
& FPU_CSR_INE_X
)
829 info
.si_code
= FPE_FLTRES
;
831 info
.si_code
= __SI_FAULT
;
832 info
.si_signo
= SIGFPE
;
834 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
835 force_sig_info(SIGFPE
, &info
, current
);
838 exception_exit(prev_state
);
841 void do_trap_or_bp(struct pt_regs
*regs
, unsigned int code
,
847 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
848 if (kgdb_ll_trap(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
850 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
852 if (notify_die(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
),
853 SIGTRAP
) == NOTIFY_STOP
)
857 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
858 * insns, even for trap and break codes that indicate arithmetic
859 * failures. Weird ...
860 * But should we continue the brokenness??? --macro
865 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
866 die_if_kernel(b
, regs
);
867 if (code
== BRK_DIVZERO
)
868 info
.si_code
= FPE_INTDIV
;
870 info
.si_code
= FPE_INTOVF
;
871 info
.si_signo
= SIGFPE
;
873 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
874 force_sig_info(SIGFPE
, &info
, current
);
877 die_if_kernel("Kernel bug detected", regs
);
878 force_sig(SIGTRAP
, current
);
882 * This breakpoint code is used by the FPU emulator to retake
883 * control of the CPU after executing the instruction from the
884 * delay slot of an emulated branch.
886 * Terminate if exception was recognized as a delay slot return
887 * otherwise handle as normal.
889 if (do_dsemulret(regs
))
892 die_if_kernel("Math emu break/trap", regs
);
893 force_sig(SIGTRAP
, current
);
896 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
897 die_if_kernel(b
, regs
);
898 force_sig(SIGTRAP
, current
);
902 asmlinkage
void do_bp(struct pt_regs
*regs
)
904 unsigned long epc
= msk_isa16_mode(exception_epc(regs
));
905 unsigned int opcode
, bcode
;
906 enum ctx_state prev_state
;
910 if (!user_mode(regs
))
913 prev_state
= exception_enter();
914 if (get_isa16_mode(regs
->cp0_epc
)) {
917 if (__get_user(instr
[0], (u16 __user
*)epc
))
920 if (!cpu_has_mmips
) {
922 bcode
= (instr
[0] >> 5) & 0x3f;
923 } else if (mm_insn_16bit(instr
[0])) {
924 /* 16-bit microMIPS BREAK */
925 bcode
= instr
[0] & 0xf;
927 /* 32-bit microMIPS BREAK */
928 if (__get_user(instr
[1], (u16 __user
*)(epc
+ 2)))
930 opcode
= (instr
[0] << 16) | instr
[1];
931 bcode
= (opcode
>> 6) & ((1 << 20) - 1);
934 if (__get_user(opcode
, (unsigned int __user
*)epc
))
936 bcode
= (opcode
>> 6) & ((1 << 20) - 1);
940 * There is the ancient bug in the MIPS assemblers that the break
941 * code starts left to bit 16 instead to bit 6 in the opcode.
942 * Gas is bug-compatible, but not always, grrr...
943 * We handle both cases with a simple heuristics. --macro
945 if (bcode
>= (1 << 10))
946 bcode
= ((bcode
& ((1 << 10) - 1)) << 10) | (bcode
>> 10);
949 * notify the kprobe handlers, if instruction is likely to
954 if (notify_die(DIE_BREAK
, "debug", regs
, bcode
,
955 regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
959 case BRK_KPROBE_SSTEPBP
:
960 if (notify_die(DIE_SSTEPBP
, "single_step", regs
, bcode
,
961 regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
969 do_trap_or_bp(regs
, bcode
, "Break");
973 exception_exit(prev_state
);
977 force_sig(SIGSEGV
, current
);
981 asmlinkage
void do_tr(struct pt_regs
*regs
)
983 u32 opcode
, tcode
= 0;
984 enum ctx_state prev_state
;
987 unsigned long epc
= msk_isa16_mode(exception_epc(regs
));
990 if (!user_mode(regs
))
993 prev_state
= exception_enter();
994 if (get_isa16_mode(regs
->cp0_epc
)) {
995 if (__get_user(instr
[0], (u16 __user
*)(epc
+ 0)) ||
996 __get_user(instr
[1], (u16 __user
*)(epc
+ 2)))
998 opcode
= (instr
[0] << 16) | instr
[1];
999 /* Immediate versions don't provide a code. */
1000 if (!(opcode
& OPCODE
))
1001 tcode
= (opcode
>> 12) & ((1 << 4) - 1);
1003 if (__get_user(opcode
, (u32 __user
*)epc
))
1005 /* Immediate versions don't provide a code. */
1006 if (!(opcode
& OPCODE
))
1007 tcode
= (opcode
>> 6) & ((1 << 10) - 1);
1010 do_trap_or_bp(regs
, tcode
, "Trap");
1014 exception_exit(prev_state
);
1018 force_sig(SIGSEGV
, current
);
1022 asmlinkage
void do_ri(struct pt_regs
*regs
)
1024 unsigned int __user
*epc
= (unsigned int __user
*)exception_epc(regs
);
1025 unsigned long old_epc
= regs
->cp0_epc
;
1026 unsigned long old31
= regs
->regs
[31];
1027 enum ctx_state prev_state
;
1028 unsigned int opcode
= 0;
1032 * Avoid any kernel code. Just emulate the R2 instruction
1033 * as quickly as possible.
1035 if (mipsr2_emulation
&& cpu_has_mips_r6
&&
1036 likely(user_mode(regs
)) &&
1037 likely(get_user(opcode
, epc
) >= 0)) {
1038 status
= mipsr2_decoder(regs
, opcode
);
1042 task_thread_info(current
)->r2_emul_return
= 1;
1047 process_fpemu_return(status
,
1048 ¤t
->thread
.cp0_baduaddr
);
1049 task_thread_info(current
)->r2_emul_return
= 1;
1056 prev_state
= exception_enter();
1058 if (notify_die(DIE_RI
, "RI Fault", regs
, 0, regs_to_trapnr(regs
),
1059 SIGILL
) == NOTIFY_STOP
)
1062 die_if_kernel("Reserved instruction in kernel code", regs
);
1064 if (unlikely(compute_return_epc(regs
) < 0))
1067 if (get_isa16_mode(regs
->cp0_epc
)) {
1068 unsigned short mmop
[2] = { 0 };
1070 if (unlikely(get_user(mmop
[0], epc
) < 0))
1072 if (unlikely(get_user(mmop
[1], epc
) < 0))
1074 opcode
= (mmop
[0] << 16) | mmop
[1];
1077 status
= simulate_rdhwr_mm(regs
, opcode
);
1079 if (unlikely(get_user(opcode
, epc
) < 0))
1082 if (!cpu_has_llsc
&& status
< 0)
1083 status
= simulate_llsc(regs
, opcode
);
1086 status
= simulate_rdhwr_normal(regs
, opcode
);
1089 status
= simulate_sync(regs
, opcode
);
1092 status
= simulate_fp(regs
, opcode
, old_epc
, old31
);
1098 if (unlikely(status
> 0)) {
1099 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1100 regs
->regs
[31] = old31
;
1101 force_sig(status
, current
);
1105 exception_exit(prev_state
);
1109 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1110 * emulated more than some threshold number of instructions, force migration to
1111 * a "CPU" that has FP support.
1113 static void mt_ase_fp_affinity(void)
1115 #ifdef CONFIG_MIPS_MT_FPAFF
1116 if (mt_fpemul_threshold
> 0 &&
1117 ((current
->thread
.emulated_fp
++ > mt_fpemul_threshold
))) {
1119 * If there's no FPU present, or if the application has already
1120 * restricted the allowed set to exclude any CPUs with FPUs,
1121 * we'll skip the procedure.
1123 if (cpus_intersects(current
->cpus_allowed
, mt_fpu_cpumask
)) {
1126 current
->thread
.user_cpus_allowed
1127 = current
->cpus_allowed
;
1128 cpus_and(tmask
, current
->cpus_allowed
,
1130 set_cpus_allowed_ptr(current
, &tmask
);
1131 set_thread_flag(TIF_FPUBOUND
);
1134 #endif /* CONFIG_MIPS_MT_FPAFF */
1138 * No lock; only written during early bootup by CPU 0.
1140 static RAW_NOTIFIER_HEAD(cu2_chain
);
1142 int __ref
register_cu2_notifier(struct notifier_block
*nb
)
1144 return raw_notifier_chain_register(&cu2_chain
, nb
);
1147 int cu2_notifier_call_chain(unsigned long val
, void *v
)
1149 return raw_notifier_call_chain(&cu2_chain
, val
, v
);
1152 static int default_cu2_call(struct notifier_block
*nfb
, unsigned long action
,
1155 struct pt_regs
*regs
= data
;
1157 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1158 "instruction", regs
);
1159 force_sig(SIGILL
, current
);
1164 static int wait_on_fp_mode_switch(atomic_t
*p
)
1167 * The FP mode for this task is currently being switched. That may
1168 * involve modifications to the format of this tasks FP context which
1169 * make it unsafe to proceed with execution for the moment. Instead,
1170 * schedule some other task.
1176 static int enable_restore_fp_context(int msa
)
1178 int err
, was_fpu_owner
, prior_msa
;
1181 * If an FP mode switch is currently underway, wait for it to
1182 * complete before proceeding.
1184 wait_on_atomic_t(¤t
->mm
->context
.fp_mode_switching
,
1185 wait_on_fp_mode_switch
, TASK_KILLABLE
);
1188 /* First time FP context user. */
1194 set_thread_flag(TIF_USEDMSA
);
1195 set_thread_flag(TIF_MSA_CTX_LIVE
);
1204 * This task has formerly used the FP context.
1206 * If this thread has no live MSA vector context then we can simply
1207 * restore the scalar FP context. If it has live MSA vector context
1208 * (that is, it has or may have used MSA since last performing a
1209 * function call) then we'll need to restore the vector context. This
1210 * applies even if we're currently only executing a scalar FP
1211 * instruction. This is because if we were to later execute an MSA
1212 * instruction then we'd either have to:
1214 * - Restore the vector context & clobber any registers modified by
1215 * scalar FP instructions between now & then.
1219 * - Not restore the vector context & lose the most significant bits
1220 * of all vector registers.
1222 * Neither of those options is acceptable. We cannot restore the least
1223 * significant bits of the registers now & only restore the most
1224 * significant bits later because the most significant bits of any
1225 * vector registers whose aliased FP register is modified now will have
1226 * been zeroed. We'd have no way to know that when restoring the vector
1227 * context & thus may load an outdated value for the most significant
1228 * bits of a vector register.
1230 if (!msa
&& !thread_msa_context_live())
1234 * This task is using or has previously used MSA. Thus we require
1235 * that Status.FR == 1.
1238 was_fpu_owner
= is_fpu_owner();
1239 err
= own_fpu_inatomic(0);
1244 write_msa_csr(current
->thread
.fpu
.msacsr
);
1245 set_thread_flag(TIF_USEDMSA
);
1248 * If this is the first time that the task is using MSA and it has
1249 * previously used scalar FP in this time slice then we already nave
1250 * FP context which we shouldn't clobber. We do however need to clear
1251 * the upper 64b of each vector register so that this task has no
1252 * opportunity to see data left behind by another.
1254 prior_msa
= test_and_set_thread_flag(TIF_MSA_CTX_LIVE
);
1255 if (!prior_msa
&& was_fpu_owner
) {
1263 * Restore the least significant 64b of each vector register
1264 * from the existing scalar FP context.
1266 _restore_fp(current
);
1269 * The task has not formerly used MSA, so clear the upper 64b
1270 * of each vector register such that it cannot see data left
1271 * behind by another task.
1275 /* We need to restore the vector context. */
1276 restore_msa(current
);
1278 /* Restore the scalar FP control & status register */
1280 write_32bit_cp1_register(CP1_STATUS
,
1281 current
->thread
.fpu
.fcr31
);
1290 asmlinkage
void do_cpu(struct pt_regs
*regs
)
1292 enum ctx_state prev_state
;
1293 unsigned int __user
*epc
;
1294 unsigned long old_epc
, old31
;
1295 unsigned int opcode
;
1298 unsigned long __maybe_unused flags
;
1300 prev_state
= exception_enter();
1301 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
1304 die_if_kernel("do_cpu invoked from kernel context!", regs
);
1308 epc
= (unsigned int __user
*)exception_epc(regs
);
1309 old_epc
= regs
->cp0_epc
;
1310 old31
= regs
->regs
[31];
1314 if (unlikely(compute_return_epc(regs
) < 0))
1317 if (get_isa16_mode(regs
->cp0_epc
)) {
1318 unsigned short mmop
[2] = { 0 };
1320 if (unlikely(get_user(mmop
[0], epc
) < 0))
1322 if (unlikely(get_user(mmop
[1], epc
) < 0))
1324 opcode
= (mmop
[0] << 16) | mmop
[1];
1327 status
= simulate_rdhwr_mm(regs
, opcode
);
1329 if (unlikely(get_user(opcode
, epc
) < 0))
1332 if (!cpu_has_llsc
&& status
< 0)
1333 status
= simulate_llsc(regs
, opcode
);
1336 status
= simulate_rdhwr_normal(regs
, opcode
);
1342 if (unlikely(status
> 0)) {
1343 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1344 regs
->regs
[31] = old31
;
1345 force_sig(status
, current
);
1352 * Old (MIPS I and MIPS II) processors will set this code
1353 * for COP1X opcode instructions that replaced the original
1354 * COP3 space. We don't limit COP1 space instructions in
1355 * the emulator according to the CPU ISA, so we want to
1356 * treat COP1X instructions consistently regardless of which
1357 * code the CPU chose. Therefore we redirect this trap to
1358 * the FP emulator too.
1360 * Then some newer FPU-less processors use this code
1361 * erroneously too, so they are covered by this choice
1364 if (raw_cpu_has_fpu
) {
1365 force_sig(SIGILL
, current
);
1371 err
= enable_restore_fp_context(0);
1373 if (!raw_cpu_has_fpu
|| err
) {
1375 void __user
*fault_addr
= NULL
;
1376 sig
= fpu_emulator_cop1Handler(regs
,
1377 ¤t
->thread
.fpu
,
1379 if (!process_fpemu_return(sig
, fault_addr
) && !err
)
1380 mt_ase_fp_affinity();
1386 raw_notifier_call_chain(&cu2_chain
, CU2_EXCEPTION
, regs
);
1390 exception_exit(prev_state
);
1393 asmlinkage
void do_msa_fpe(struct pt_regs
*regs
)
1395 enum ctx_state prev_state
;
1397 prev_state
= exception_enter();
1398 die_if_kernel("do_msa_fpe invoked from kernel context!", regs
);
1399 force_sig(SIGFPE
, current
);
1400 exception_exit(prev_state
);
1403 asmlinkage
void do_msa(struct pt_regs
*regs
)
1405 enum ctx_state prev_state
;
1408 prev_state
= exception_enter();
1410 if (!cpu_has_msa
|| test_thread_flag(TIF_32BIT_FPREGS
)) {
1411 force_sig(SIGILL
, current
);
1415 die_if_kernel("do_msa invoked from kernel context!", regs
);
1417 err
= enable_restore_fp_context(1);
1419 force_sig(SIGILL
, current
);
1421 exception_exit(prev_state
);
1424 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
1426 enum ctx_state prev_state
;
1428 prev_state
= exception_enter();
1429 force_sig(SIGILL
, current
);
1430 exception_exit(prev_state
);
1434 * Called with interrupts disabled.
1436 asmlinkage
void do_watch(struct pt_regs
*regs
)
1438 enum ctx_state prev_state
;
1441 prev_state
= exception_enter();
1443 * Clear WP (bit 22) bit of cause register so we don't loop
1446 cause
= read_c0_cause();
1447 cause
&= ~(1 << 22);
1448 write_c0_cause(cause
);
1451 * If the current thread has the watch registers loaded, save
1452 * their values and send SIGTRAP. Otherwise another thread
1453 * left the registers set, clear them and continue.
1455 if (test_tsk_thread_flag(current
, TIF_LOAD_WATCH
)) {
1456 mips_read_watch_registers();
1458 force_sig(SIGTRAP
, current
);
1460 mips_clear_watch_registers();
1463 exception_exit(prev_state
);
1466 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
1468 const int field
= 2 * sizeof(unsigned long);
1469 int multi_match
= regs
->cp0_status
& ST0_TS
;
1470 enum ctx_state prev_state
;
1472 prev_state
= exception_enter();
1476 pr_err("Index : %0x\n", read_c0_index());
1477 pr_err("Pagemask: %0x\n", read_c0_pagemask());
1478 pr_err("EntryHi : %0*lx\n", field
, read_c0_entryhi());
1479 pr_err("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
1480 pr_err("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
1481 pr_err("Wired : %0x\n", read_c0_wired());
1482 pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
1484 pr_err("PWField : %0*lx\n", field
, read_c0_pwfield());
1485 pr_err("PWSize : %0*lx\n", field
, read_c0_pwsize());
1486 pr_err("PWCtl : %0x\n", read_c0_pwctl());
1492 show_code((unsigned int __user
*) regs
->cp0_epc
);
1495 * Some chips may have other causes of machine check (e.g. SB1
1498 panic("Caught Machine Check exception - %scaused by multiple "
1499 "matching entries in the TLB.",
1500 (multi_match
) ? "" : "not ");
1503 asmlinkage
void do_mt(struct pt_regs
*regs
)
1507 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
1508 >> VPECONTROL_EXCPT_SHIFT
;
1511 printk(KERN_DEBUG
"Thread Underflow\n");
1514 printk(KERN_DEBUG
"Thread Overflow\n");
1517 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
1520 printk(KERN_DEBUG
"Gating Storage Exception\n");
1523 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
1526 printk(KERN_DEBUG
"Gating Storage Scheduler Exception\n");
1529 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
1533 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
1535 force_sig(SIGILL
, current
);
1539 asmlinkage
void do_dsp(struct pt_regs
*regs
)
1542 panic("Unexpected DSP exception");
1544 force_sig(SIGILL
, current
);
1547 asmlinkage
void do_reserved(struct pt_regs
*regs
)
1550 * Game over - no way to handle this if it ever occurs. Most probably
1551 * caused by a new unknown cpu type or after another deadly
1552 * hard/software error.
1555 panic("Caught reserved exception %ld - should not happen.",
1556 (regs
->cp0_cause
& 0x7f) >> 2);
1559 static int __initdata l1parity
= 1;
1560 static int __init
nol1parity(char *s
)
1565 __setup("nol1par", nol1parity
);
1566 static int __initdata l2parity
= 1;
1567 static int __init
nol2parity(char *s
)
1572 __setup("nol2par", nol2parity
);
1575 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1576 * it different ways.
1578 static inline void parity_protection_init(void)
1580 switch (current_cpu_type()) {
1586 case CPU_INTERAPTIV
:
1589 case CPU_QEMU_GENERIC
:
1591 #define ERRCTL_PE 0x80000000
1592 #define ERRCTL_L2P 0x00800000
1593 unsigned long errctl
;
1594 unsigned int l1parity_present
, l2parity_present
;
1596 errctl
= read_c0_ecc();
1597 errctl
&= ~(ERRCTL_PE
|ERRCTL_L2P
);
1599 /* probe L1 parity support */
1600 write_c0_ecc(errctl
| ERRCTL_PE
);
1601 back_to_back_c0_hazard();
1602 l1parity_present
= (read_c0_ecc() & ERRCTL_PE
);
1604 /* probe L2 parity support */
1605 write_c0_ecc(errctl
|ERRCTL_L2P
);
1606 back_to_back_c0_hazard();
1607 l2parity_present
= (read_c0_ecc() & ERRCTL_L2P
);
1609 if (l1parity_present
&& l2parity_present
) {
1611 errctl
|= ERRCTL_PE
;
1612 if (l1parity
^ l2parity
)
1613 errctl
|= ERRCTL_L2P
;
1614 } else if (l1parity_present
) {
1616 errctl
|= ERRCTL_PE
;
1617 } else if (l2parity_present
) {
1619 errctl
|= ERRCTL_L2P
;
1621 /* No parity available */
1624 printk(KERN_INFO
"Writing ErrCtl register=%08lx\n", errctl
);
1626 write_c0_ecc(errctl
);
1627 back_to_back_c0_hazard();
1628 errctl
= read_c0_ecc();
1629 printk(KERN_INFO
"Readback ErrCtl register=%08lx\n", errctl
);
1631 if (l1parity_present
)
1632 printk(KERN_INFO
"Cache parity protection %sabled\n",
1633 (errctl
& ERRCTL_PE
) ? "en" : "dis");
1635 if (l2parity_present
) {
1636 if (l1parity_present
&& l1parity
)
1637 errctl
^= ERRCTL_L2P
;
1638 printk(KERN_INFO
"L2 cache parity protection %sabled\n",
1639 (errctl
& ERRCTL_L2P
) ? "en" : "dis");
1647 write_c0_ecc(0x80000000);
1648 back_to_back_c0_hazard();
1649 /* Set the PE bit (bit 31) in the c0_errctl register. */
1650 printk(KERN_INFO
"Cache parity protection %sabled\n",
1651 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1655 /* Clear the DE bit (bit 16) in the c0_status register. */
1656 printk(KERN_INFO
"Enable cache parity protection for "
1657 "MIPS 20KC/25KF CPUs.\n");
1658 clear_c0_status(ST0_DE
);
1665 asmlinkage
void cache_parity_error(void)
1667 const int field
= 2 * sizeof(unsigned long);
1668 unsigned int reg_val
;
1670 /* For the moment, report the problem and hang. */
1671 printk("Cache error exception:\n");
1672 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1673 reg_val
= read_c0_cacheerr();
1674 printk("c0_cacheerr == %08x\n", reg_val
);
1676 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1677 reg_val
& (1<<30) ? "secondary" : "primary",
1678 reg_val
& (1<<31) ? "data" : "insn");
1679 if ((cpu_has_mips_r2_r6
) &&
1680 ((current_cpu_data
.processor_id
& 0xff0000) == PRID_COMP_MIPS
)) {
1681 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1682 reg_val
& (1<<29) ? "ED " : "",
1683 reg_val
& (1<<28) ? "ET " : "",
1684 reg_val
& (1<<27) ? "ES " : "",
1685 reg_val
& (1<<26) ? "EE " : "",
1686 reg_val
& (1<<25) ? "EB " : "",
1687 reg_val
& (1<<24) ? "EI " : "",
1688 reg_val
& (1<<23) ? "E1 " : "",
1689 reg_val
& (1<<22) ? "E0 " : "");
1691 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1692 reg_val
& (1<<29) ? "ED " : "",
1693 reg_val
& (1<<28) ? "ET " : "",
1694 reg_val
& (1<<26) ? "EE " : "",
1695 reg_val
& (1<<25) ? "EB " : "",
1696 reg_val
& (1<<24) ? "EI " : "",
1697 reg_val
& (1<<23) ? "E1 " : "",
1698 reg_val
& (1<<22) ? "E0 " : "");
1700 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
1702 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1703 if (reg_val
& (1<<22))
1704 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
1706 if (reg_val
& (1<<23))
1707 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
1710 panic("Can't handle the cache error!");
1713 asmlinkage
void do_ftlb(void)
1715 const int field
= 2 * sizeof(unsigned long);
1716 unsigned int reg_val
;
1718 /* For the moment, report the problem and hang. */
1719 if ((cpu_has_mips_r2_r6
) &&
1720 ((current_cpu_data
.processor_id
& 0xff0000) == PRID_COMP_MIPS
)) {
1721 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1723 pr_err("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1724 reg_val
= read_c0_cacheerr();
1725 pr_err("c0_cacheerr == %08x\n", reg_val
);
1727 if ((reg_val
& 0xc0000000) == 0xc0000000) {
1728 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1730 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1731 reg_val
& (1<<30) ? "secondary" : "primary",
1732 reg_val
& (1<<31) ? "data" : "insn");
1735 pr_err("FTLB error exception\n");
1737 /* Just print the cacheerr bits for now */
1738 cache_parity_error();
1742 * SDBBP EJTAG debug exception handler.
1743 * We skip the instruction and return to the next instruction.
1745 void ejtag_exception_handler(struct pt_regs
*regs
)
1747 const int field
= 2 * sizeof(unsigned long);
1748 unsigned long depc
, old_epc
, old_ra
;
1751 printk(KERN_DEBUG
"SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1752 depc
= read_c0_depc();
1753 debug
= read_c0_debug();
1754 printk(KERN_DEBUG
"c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
1755 if (debug
& 0x80000000) {
1757 * In branch delay slot.
1758 * We cheat a little bit here and use EPC to calculate the
1759 * debug return address (DEPC). EPC is restored after the
1762 old_epc
= regs
->cp0_epc
;
1763 old_ra
= regs
->regs
[31];
1764 regs
->cp0_epc
= depc
;
1765 compute_return_epc(regs
);
1766 depc
= regs
->cp0_epc
;
1767 regs
->cp0_epc
= old_epc
;
1768 regs
->regs
[31] = old_ra
;
1771 write_c0_depc(depc
);
1774 printk(KERN_DEBUG
"\n\n----- Enable EJTAG single stepping ----\n\n");
1775 write_c0_debug(debug
| 0x100);
1780 * NMI exception handler.
1781 * No lock; only written during early bootup by CPU 0.
1783 static RAW_NOTIFIER_HEAD(nmi_chain
);
1785 int register_nmi_notifier(struct notifier_block
*nb
)
1787 return raw_notifier_chain_register(&nmi_chain
, nb
);
1790 void __noreturn
nmi_exception_handler(struct pt_regs
*regs
)
1794 raw_notifier_call_chain(&nmi_chain
, 0, regs
);
1796 snprintf(str
, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1797 smp_processor_id(), regs
->cp0_epc
);
1798 regs
->cp0_epc
= read_c0_errorepc();
1802 #define VECTORSPACING 0x100 /* for EI/VI mode */
1804 unsigned long ebase
;
1805 unsigned long exception_handlers
[32];
1806 unsigned long vi_handlers
[64];
1808 void __init
*set_except_vector(int n
, void *addr
)
1810 unsigned long handler
= (unsigned long) addr
;
1811 unsigned long old_handler
;
1813 #ifdef CONFIG_CPU_MICROMIPS
1815 * Only the TLB handlers are cache aligned with an even
1816 * address. All other handlers are on an odd address and
1817 * require no modification. Otherwise, MIPS32 mode will
1818 * be entered when handling any TLB exceptions. That
1819 * would be bad...since we must stay in microMIPS mode.
1821 if (!(handler
& 0x1))
1824 old_handler
= xchg(&exception_handlers
[n
], handler
);
1826 if (n
== 0 && cpu_has_divec
) {
1827 #ifdef CONFIG_CPU_MICROMIPS
1828 unsigned long jump_mask
= ~((1 << 27) - 1);
1830 unsigned long jump_mask
= ~((1 << 28) - 1);
1832 u32
*buf
= (u32
*)(ebase
+ 0x200);
1833 unsigned int k0
= 26;
1834 if ((handler
& jump_mask
) == ((ebase
+ 0x200) & jump_mask
)) {
1835 uasm_i_j(&buf
, handler
& ~jump_mask
);
1838 UASM_i_LA(&buf
, k0
, handler
);
1839 uasm_i_jr(&buf
, k0
);
1842 local_flush_icache_range(ebase
+ 0x200, (unsigned long)buf
);
1844 return (void *)old_handler
;
1847 static void do_default_vi(void)
1849 show_regs(get_irq_regs());
1850 panic("Caught unexpected vectored interrupt.");
1853 static void *set_vi_srs_handler(int n
, vi_handler_t addr
, int srs
)
1855 unsigned long handler
;
1856 unsigned long old_handler
= vi_handlers
[n
];
1857 int srssets
= current_cpu_data
.srsets
;
1861 BUG_ON(!cpu_has_veic
&& !cpu_has_vint
);
1864 handler
= (unsigned long) do_default_vi
;
1867 handler
= (unsigned long) addr
;
1868 vi_handlers
[n
] = handler
;
1870 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1873 panic("Shadow register set %d not supported", srs
);
1876 if (board_bind_eic_interrupt
)
1877 board_bind_eic_interrupt(n
, srs
);
1878 } else if (cpu_has_vint
) {
1879 /* SRSMap is only defined if shadow sets are implemented */
1881 change_c0_srsmap(0xf << n
*4, srs
<< n
*4);
1886 * If no shadow set is selected then use the default handler
1887 * that does normal register saving and standard interrupt exit
1889 extern char except_vec_vi
, except_vec_vi_lui
;
1890 extern char except_vec_vi_ori
, except_vec_vi_end
;
1891 extern char rollback_except_vec_vi
;
1892 char *vec_start
= using_rollback_handler() ?
1893 &rollback_except_vec_vi
: &except_vec_vi
;
1894 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1895 const int lui_offset
= &except_vec_vi_lui
- vec_start
+ 2;
1896 const int ori_offset
= &except_vec_vi_ori
- vec_start
+ 2;
1898 const int lui_offset
= &except_vec_vi_lui
- vec_start
;
1899 const int ori_offset
= &except_vec_vi_ori
- vec_start
;
1901 const int handler_len
= &except_vec_vi_end
- vec_start
;
1903 if (handler_len
> VECTORSPACING
) {
1905 * Sigh... panicing won't help as the console
1906 * is probably not configured :(
1908 panic("VECTORSPACING too small");
1911 set_handler(((unsigned long)b
- ebase
), vec_start
,
1912 #ifdef CONFIG_CPU_MICROMIPS
1917 h
= (u16
*)(b
+ lui_offset
);
1918 *h
= (handler
>> 16) & 0xffff;
1919 h
= (u16
*)(b
+ ori_offset
);
1920 *h
= (handler
& 0xffff);
1921 local_flush_icache_range((unsigned long)b
,
1922 (unsigned long)(b
+handler_len
));
1926 * In other cases jump directly to the interrupt handler. It
1927 * is the handler's responsibility to save registers if required
1928 * (eg hi/lo) and return from the exception using "eret".
1934 #ifdef CONFIG_CPU_MICROMIPS
1935 insn
= 0xd4000000 | (((u32
)handler
& 0x07ffffff) >> 1);
1937 insn
= 0x08000000 | (((u32
)handler
& 0x0fffffff) >> 2);
1939 h
[0] = (insn
>> 16) & 0xffff;
1940 h
[1] = insn
& 0xffff;
1943 local_flush_icache_range((unsigned long)b
,
1944 (unsigned long)(b
+8));
1947 return (void *)old_handler
;
1950 void *set_vi_handler(int n
, vi_handler_t addr
)
1952 return set_vi_srs_handler(n
, addr
, 0);
1955 extern void tlb_init(void);
1960 int cp0_compare_irq
;
1961 EXPORT_SYMBOL_GPL(cp0_compare_irq
);
1962 int cp0_compare_irq_shift
;
1965 * Performance counter IRQ or -1 if shared with timer
1967 int cp0_perfcount_irq
;
1968 EXPORT_SYMBOL_GPL(cp0_perfcount_irq
);
1971 * Fast debug channel IRQ or -1 if not present
1974 EXPORT_SYMBOL_GPL(cp0_fdc_irq
);
1978 static int __init
ulri_disable(char *s
)
1980 pr_info("Disabling ulri\n");
1985 __setup("noulri", ulri_disable
);
1987 /* configure STATUS register */
1988 static void configure_status(void)
1991 * Disable coprocessors and select 32-bit or 64-bit addressing
1992 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1993 * flag that some firmware may have left set and the TS bit (for
1994 * IP27). Set XX for ISA IV code to work.
1996 unsigned int status_set
= ST0_CU0
;
1998 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
2000 if (current_cpu_data
.isa_level
& MIPS_CPU_ISA_IV
)
2001 status_set
|= ST0_XX
;
2003 status_set
|= ST0_MX
;
2005 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
2009 /* configure HWRENA register */
2010 static void configure_hwrena(void)
2012 unsigned int hwrena
= cpu_hwrena_impl_bits
;
2014 if (cpu_has_mips_r2_r6
)
2015 hwrena
|= 0x0000000f;
2017 if (!noulri
&& cpu_has_userlocal
)
2018 hwrena
|= (1 << 29);
2021 write_c0_hwrena(hwrena
);
2024 static void configure_exception_vector(void)
2026 if (cpu_has_veic
|| cpu_has_vint
) {
2027 unsigned long sr
= set_c0_status(ST0_BEV
);
2028 write_c0_ebase(ebase
);
2029 write_c0_status(sr
);
2030 /* Setting vector spacing enables EI/VI mode */
2031 change_c0_intctl(0x3e0, VECTORSPACING
);
2033 if (cpu_has_divec
) {
2034 if (cpu_has_mipsmt
) {
2035 unsigned int vpflags
= dvpe();
2036 set_c0_cause(CAUSEF_IV
);
2039 set_c0_cause(CAUSEF_IV
);
2043 void per_cpu_trap_init(bool is_boot_cpu
)
2045 unsigned int cpu
= smp_processor_id();
2050 configure_exception_vector();
2053 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2055 * o read IntCtl.IPTI to determine the timer interrupt
2056 * o read IntCtl.IPPCI to determine the performance counter interrupt
2057 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2059 if (cpu_has_mips_r2_r6
) {
2060 cp0_compare_irq_shift
= CAUSEB_TI
- CAUSEB_IP
;
2061 cp0_compare_irq
= (read_c0_intctl() >> INTCTLB_IPTI
) & 7;
2062 cp0_perfcount_irq
= (read_c0_intctl() >> INTCTLB_IPPCI
) & 7;
2063 cp0_fdc_irq
= (read_c0_intctl() >> INTCTLB_IPFDC
) & 7;
2068 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
2069 cp0_compare_irq_shift
= CP0_LEGACY_PERFCNT_IRQ
;
2070 cp0_perfcount_irq
= -1;
2074 if (!cpu_data
[cpu
].asid_cache
)
2075 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
2077 atomic_inc(&init_mm
.mm_count
);
2078 current
->active_mm
= &init_mm
;
2079 BUG_ON(current
->mm
);
2080 enter_lazy_tlb(&init_mm
, current
);
2082 /* Boot CPU's cache setup in setup_arch(). */
2086 TLBMISS_HANDLER_SETUP();
2089 /* Install CPU exception handler */
2090 void set_handler(unsigned long offset
, void *addr
, unsigned long size
)
2092 #ifdef CONFIG_CPU_MICROMIPS
2093 memcpy((void *)(ebase
+ offset
), ((unsigned char *)addr
- 1), size
);
2095 memcpy((void *)(ebase
+ offset
), addr
, size
);
2097 local_flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
2100 static char panic_null_cerr
[] =
2101 "Trying to set NULL cache error exception handler";
2104 * Install uncached CPU exception handler.
2105 * This is suitable only for the cache error exception which is the only
2106 * exception handler that is being run uncached.
2108 void set_uncached_handler(unsigned long offset
, void *addr
,
2111 unsigned long uncached_ebase
= CKSEG1ADDR(ebase
);
2114 panic(panic_null_cerr
);
2116 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
2119 static int __initdata rdhwr_noopt
;
2120 static int __init
set_rdhwr_noopt(char *str
)
2126 __setup("rdhwr_noopt", set_rdhwr_noopt
);
2128 void __init
trap_init(void)
2130 extern char except_vec3_generic
;
2131 extern char except_vec4
;
2132 extern char except_vec3_r4000
;
2137 #if defined(CONFIG_KGDB)
2138 if (kgdb_early_setup
)
2139 return; /* Already done */
2142 if (cpu_has_veic
|| cpu_has_vint
) {
2143 unsigned long size
= 0x200 + VECTORSPACING
*64;
2144 ebase
= (unsigned long)
2145 __alloc_bootmem(size
, 1 << fls(size
), 0);
2147 #ifdef CONFIG_KVM_GUEST
2148 #define KVM_GUEST_KSEG0 0x40000000
2149 ebase
= KVM_GUEST_KSEG0
;
2153 if (cpu_has_mips_r2_r6
)
2154 ebase
+= (read_c0_ebase() & 0x3ffff000);
2157 if (cpu_has_mmips
) {
2158 unsigned int config3
= read_c0_config3();
2160 if (IS_ENABLED(CONFIG_CPU_MICROMIPS
))
2161 write_c0_config3(config3
| MIPS_CONF3_ISA_OE
);
2163 write_c0_config3(config3
& ~MIPS_CONF3_ISA_OE
);
2166 if (board_ebase_setup
)
2167 board_ebase_setup();
2168 per_cpu_trap_init(true);
2171 * Copy the generic exception handlers to their final destination.
2172 * This will be overriden later as suitable for a particular
2175 set_handler(0x180, &except_vec3_generic
, 0x80);
2178 * Setup default vectors
2180 for (i
= 0; i
<= 31; i
++)
2181 set_except_vector(i
, handle_reserved
);
2184 * Copy the EJTAG debug exception vector handler code to it's final
2187 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
2188 board_ejtag_handler_setup();
2191 * Only some CPUs have the watch exceptions.
2194 set_except_vector(23, handle_watch
);
2197 * Initialise interrupt handlers
2199 if (cpu_has_veic
|| cpu_has_vint
) {
2200 int nvec
= cpu_has_veic
? 64 : 8;
2201 for (i
= 0; i
< nvec
; i
++)
2202 set_vi_handler(i
, NULL
);
2204 else if (cpu_has_divec
)
2205 set_handler(0x200, &except_vec4
, 0x8);
2208 * Some CPUs can enable/disable for cache parity detection, but does
2209 * it different ways.
2211 parity_protection_init();
2214 * The Data Bus Errors / Instruction Bus Errors are signaled
2215 * by external hardware. Therefore these two exceptions
2216 * may have board specific handlers.
2221 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2223 set_except_vector(1, handle_tlbm
);
2224 set_except_vector(2, handle_tlbl
);
2225 set_except_vector(3, handle_tlbs
);
2227 set_except_vector(4, handle_adel
);
2228 set_except_vector(5, handle_ades
);
2230 set_except_vector(6, handle_ibe
);
2231 set_except_vector(7, handle_dbe
);
2233 set_except_vector(8, handle_sys
);
2234 set_except_vector(9, handle_bp
);
2235 set_except_vector(10, rdhwr_noopt
? handle_ri
:
2236 (cpu_has_vtag_icache
?
2237 handle_ri_rdhwr_vivt
: handle_ri_rdhwr
));
2238 set_except_vector(11, handle_cpu
);
2239 set_except_vector(12, handle_ov
);
2240 set_except_vector(13, handle_tr
);
2241 set_except_vector(14, handle_msa_fpe
);
2243 if (current_cpu_type() == CPU_R6000
||
2244 current_cpu_type() == CPU_R6000A
) {
2246 * The R6000 is the only R-series CPU that features a machine
2247 * check exception (similar to the R4000 cache error) and
2248 * unaligned ldc1/sdc1 exception. The handlers have not been
2249 * written yet. Well, anyway there is no R6000 machine on the
2250 * current list of targets for Linux/MIPS.
2251 * (Duh, crap, there is someone with a triple R6k machine)
2253 //set_except_vector(14, handle_mc);
2254 //set_except_vector(15, handle_ndc);
2258 if (board_nmi_handler_setup
)
2259 board_nmi_handler_setup();
2261 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
2262 set_except_vector(15, handle_fpe
);
2264 set_except_vector(16, handle_ftlb
);
2266 if (cpu_has_rixiex
) {
2267 set_except_vector(19, tlb_do_page_fault_0
);
2268 set_except_vector(20, tlb_do_page_fault_0
);
2271 set_except_vector(21, handle_msa
);
2272 set_except_vector(22, handle_mdmx
);
2275 set_except_vector(24, handle_mcheck
);
2278 set_except_vector(25, handle_mt
);
2280 set_except_vector(26, handle_dsp
);
2282 if (board_cache_error_setup
)
2283 board_cache_error_setup();
2286 /* Special exception: R4[04]00 uses also the divec space. */
2287 set_handler(0x180, &except_vec3_r4000
, 0x100);
2288 else if (cpu_has_4kex
)
2289 set_handler(0x180, &except_vec3_generic
, 0x80);
2291 set_handler(0x080, &except_vec3_generic
, 0x80);
2293 local_flush_icache_range(ebase
, ebase
+ 0x400);
2295 sort_extable(__start___dbe_table
, __stop___dbe_table
);
2297 cu2_notifier(default_cu2_call
, 0x80000000); /* Run last */
2300 static int trap_pm_notifier(struct notifier_block
*self
, unsigned long cmd
,
2304 case CPU_PM_ENTER_FAILED
:
2308 configure_exception_vector();
2310 /* Restore register with CPU number for TLB handlers */
2311 TLBMISS_HANDLER_RESTORE();
2319 static struct notifier_block trap_pm_notifier_block
= {
2320 .notifier_call
= trap_pm_notifier
,
2323 static int __init
trap_pm_init(void)
2325 return cpu_pm_register_notifier(&trap_pm_notifier_block
);
2327 arch_initcall(trap_pm_init
);