arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004  Maciej W. Rozycki
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/smp_lock.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/kallsyms.h>
  23
  24 #include <asm/bootinfo.h>
  25 #include <asm/branch.h>
  26 #include <asm/break.h>
  27 #include <asm/cpu.h>
  28 #include <asm/fpu.h>
  29 #include <asm/module.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/ptrace.h>
  32 #include <asm/sections.h>
  33 #include <asm/system.h>
  34 #include <asm/tlbdebug.h>
  35 #include <asm/traps.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/watch.h>
  39 #include <asm/types.h>
  40
  41 extern asmlinkage void handle_tlbm(void);
  42 extern asmlinkage void handle_tlbl(void);
  43 extern asmlinkage void handle_tlbs(void);
  44 extern asmlinkage void handle_adel(void);
  45 extern asmlinkage void handle_ades(void);
  46 extern asmlinkage void handle_ibe(void);
  47 extern asmlinkage void handle_dbe(void);
  48 extern asmlinkage void handle_sys(void);
  49 extern asmlinkage void handle_bp(void);
  50 extern asmlinkage void handle_ri(void);
  51 extern asmlinkage void handle_cpu(void);
  52 extern asmlinkage void handle_ov(void);
  53 extern asmlinkage void handle_tr(void);
  54 extern asmlinkage void handle_fpe(void);
  55 extern asmlinkage void handle_mdmx(void);
  56 extern asmlinkage void handle_watch(void);
  57 extern asmlinkage void handle_mcheck(void);
  58 extern asmlinkage void handle_reserved(void);
  59
  60 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
  61         struct mips_fpu_soft_struct *ctx);
  62
  63 void (*board_be_init)(void);
  64 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  65
  66 /*
  67  * These constant is for searching for possible module text segments.
  68  * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
  69  */
  70 #define MODULE_RANGE (8*1024*1024)
  71
  72 /*
  73  * This routine abuses get_user()/put_user() to reference pointers
  74  * with at least a bit of error checking ...
  75  */
  76 void show_stack(struct task_struct *task, unsigned long *sp)
  77 {
  78         const int field = 2 * sizeof(unsigned long);
  79         long stackdata;
  80         int i;
  81
  82         if (!sp) {
  83                 if (task && task != current)
  84                         sp = (unsigned long *) task->thread.reg29;
  85                 else
  86                         sp = (unsigned long *) &sp;
  87         }
  88
  89         printk("Stack :");
  90         i = 0;
  91         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
  92                 if (i && ((i % (64 / field)) == 0))
  93                         printk("\n       ");
  94                 if (i > 39) {
  95                         printk(" ...");
  96                         break;
  97                 }
  98
  99                 if (__get_user(stackdata, sp++)) {
 100                         printk(" (Bad stack address)");
 101                         break;
 102                 }
 103
 104                 printk(" %0*lx", field, stackdata);
 105                 i++;
 106         }
 107         printk("\n");
 108 }
 109
 110 void show_trace(struct task_struct *task, unsigned long *stack)
 111 {
 112         const int field = 2 * sizeof(unsigned long);
 113         unsigned long addr;
 114
 115         if (!stack) {
 116                 if (task && task != current)
 117                         stack = (unsigned long *) task->thread.reg29;
 118                 else
 119                         stack = (unsigned long *) &stack;
 120         }
 121
 122         printk("Call Trace:");
 123 #ifdef CONFIG_KALLSYMS
 124         printk("\n");
 125 #endif
 126         while (!kstack_end(stack)) {
 127                 addr = *stack++;
 128                 if (__kernel_text_address(addr)) {
 129                         printk(" [<%0*lx>] ", field, addr);
 130                         print_symbol("%s\n", addr);
 131                 }
 132         }
 133         printk("\n");
 134 }
 135
 136 /*
 137  * The architecture-independent dump_stack generator
 138  */
 139 void dump_stack(void)
 140 {
 141         unsigned long stack;
 142
 143         show_trace(current, &stack);
 144 }
 145
 146 EXPORT_SYMBOL(dump_stack);
 147
 148 void show_code(unsigned int *pc)
 149 {
 150         long i;
 151
 152         printk("\nCode:");
 153
 154         for(i = -3 ; i < 6 ; i++) {
 155                 unsigned int insn;
 156                 if (__get_user(insn, pc + i)) {
 157                         printk(" (Bad address in epc)\n");
 158                         break;
 159                 }
 160                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 161         }
 162 }
 163
 164 void show_regs(struct pt_regs *regs)
 165 {
 166         const int field = 2 * sizeof(unsigned long);
 167         unsigned int cause = regs->cp0_cause;
 168         int i;
 169
 170         printk("Cpu %d\n", smp_processor_id());
 171
 172         /*
 173          * Saved main processor registers
 174          */
 175         for (i = 0; i < 32; ) {
 176                 if ((i % 4) == 0)
 177                         printk("$%2d   :", i);
 178                 if (i == 0)
 179                         printk(" %0*lx", field, 0UL);
 180                 else if (i == 26 || i == 27)
 181                         printk(" %*s", field, "");
 182                 else
 183                         printk(" %0*lx", field, regs->regs[i]);
 184
 185                 i++;
 186                 if ((i % 4) == 0)
 187                         printk("\n");
 188         }
 189
 190         printk("Hi    : %0*lx\n", field, regs->hi);
 191         printk("Lo    : %0*lx\n", field, regs->lo);
 192
 193         /*
 194          * Saved cp0 registers
 195          */
 196         printk("epc   : %0*lx ", field, regs->cp0_epc);
 197         print_symbol("%s ", regs->cp0_epc);
 198         printk("    %s\n", print_tainted());
 199         printk("ra    : %0*lx ", field, regs->regs[31]);
 200         print_symbol("%s\n", regs->regs[31]);
 201
 202         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 203
 204         if (regs->cp0_status & ST0_KX)
 205                 printk("KX ");
 206         if (regs->cp0_status & ST0_SX)
 207                 printk("SX ");
 208         if (regs->cp0_status & ST0_UX)
 209                 printk("UX ");
 210         switch (regs->cp0_status & ST0_KSU) {
 211         case KSU_USER:
 212                 printk("USER ");
 213                 break;
 214         case KSU_SUPERVISOR:
 215                 printk("SUPERVISOR ");
 216                 break;
 217         case KSU_KERNEL:
 218                 printk("KERNEL ");
 219                 break;
 220         default:
 221                 printk("BAD_MODE ");
 222                 break;
 223         }
 224         if (regs->cp0_status & ST0_ERL)
 225                 printk("ERL ");
 226         if (regs->cp0_status & ST0_EXL)
 227                 printk("EXL ");
 228         if (regs->cp0_status & ST0_IE)
 229                 printk("IE ");
 230         printk("\n");
 231
 232         printk("Cause : %08x\n", cause);
 233
 234         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 235         if (1 <= cause && cause <= 5)
 236                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 237
 238         printk("PrId  : %08x\n", read_c0_prid());
 239 }
 240
 241 void show_registers(struct pt_regs *regs)
 242 {
 243         show_regs(regs);
 244         print_modules();
 245         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 246                 current->comm, current->pid, current_thread_info(), current);
 247         show_stack(current, (long *) regs->regs[29]);
 248         show_trace(current, (long *) regs->regs[29]);
 249         show_code((unsigned int *) regs->cp0_epc);
 250         printk("\n");
 251 }
 252
 253 static DEFINE_SPINLOCK(die_lock);
 254
 255 NORET_TYPE void __die(const char * str, struct pt_regs * regs,
 256         const char * file, const char * func, unsigned long line)
 257 {
 258         static int die_counter;
 259
 260         console_verbose();
 261         spin_lock_irq(&die_lock);
 262         printk("%s", str);
 263         if (file && func)
 264                 printk(" in %s:%s, line %ld", file, func, line);
 265         printk("[#%d]:\n", ++die_counter);
 266         show_registers(regs);
 267         spin_unlock_irq(&die_lock);
 268         do_exit(SIGSEGV);
 269 }
 270
 271 void __die_if_kernel(const char * str, struct pt_regs * regs,
 272                      const char * file, const char * func, unsigned long line)
 273 {
 274         if (!user_mode(regs))
 275                 __die(str, regs, file, func, line);
 276 }
 277
 278 extern const struct exception_table_entry __start___dbe_table[];
 279 extern const struct exception_table_entry __stop___dbe_table[];
 280
 281 void __declare_dbe_table(void)
 282 {
 283         __asm__ __volatile__(
 284         ".section\t__dbe_table,\"a\"\n\t"
 285         ".previous"
 286         );
 287 }
 288
 289 /* Given an address, look for it in the exception tables. */
 290 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 291 {
 292         const struct exception_table_entry *e;
 293
 294         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 295         if (!e)
 296                 e = search_module_dbetables(addr);
 297         return e;
 298 }
 299
 300 asmlinkage void do_be(struct pt_regs *regs)
 301 {
 302         const int field = 2 * sizeof(unsigned long);
 303         const struct exception_table_entry *fixup = NULL;
 304         int data = regs->cp0_cause & 4;
 305         int action = MIPS_BE_FATAL;
 306
 307         /* XXX For now.  Fixme, this searches the wrong table ...  */
 308         if (data && !user_mode(regs))
 309                 fixup = search_dbe_tables(exception_epc(regs));
 310
 311         if (fixup)
 312                 action = MIPS_BE_FIXUP;
 313
 314         if (board_be_handler)
 315                 action = board_be_handler(regs, fixup != 0);
 316
 317         switch (action) {
 318         case MIPS_BE_DISCARD:
 319                 return;
 320         case MIPS_BE_FIXUP:
 321                 if (fixup) {
 322                         regs->cp0_epc = fixup->nextinsn;
 323                         return;
 324                 }
 325                 break;
 326         default:
 327                 break;
 328         }
 329
 330         /*
 331          * Assume it would be too dangerous to continue ...
 332          */
 333         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 334                data ? "Data" : "Instruction",
 335                field, regs->cp0_epc, field, regs->regs[31]);
 336         die_if_kernel("Oops", regs);
 337         force_sig(SIGBUS, current);
 338 }
 339
 340 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
 341 {
 342         unsigned int __user *epc;
 343
 344         epc = (unsigned int __user *) regs->cp0_epc +
 345               ((regs->cp0_cause & CAUSEF_BD) != 0);
 346         if (!get_user(*opcode, epc))
 347                 return 0;
 348
 349         force_sig(SIGSEGV, current);
 350         return 1;
 351 }
 352
 353 /*
 354  * ll/sc emulation
 355  */
 356
 357 #define OPCODE 0xfc000000
 358 #define BASE   0x03e00000
 359 #define RT     0x001f0000
 360 #define OFFSET 0x0000ffff
 361 #define LL     0xc0000000
 362 #define SC     0xe0000000
 363 #define SPEC3  0x7c000000
 364 #define RD     0x0000f800
 365 #define FUNC   0x0000003f
 366 #define RDHWR  0x0000003b
 367
 368 /*
 369  * The ll_bit is cleared by r*_switch.S
 370  */
 371
 372 unsigned long ll_bit;
 373
 374 static struct task_struct *ll_task = NULL;
 375
 376 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 377 {
 378         unsigned long value, __user *vaddr;
 379         long offset;
 380         int signal = 0;
 381
 382         /*
 383          * analyse the ll instruction that just caused a ri exception
 384          * and put the referenced address to addr.
 385          */
 386
 387         /* sign extend offset */
 388         offset = opcode & OFFSET;
 389         offset <<= 16;
 390         offset >>= 16;
 391
 392         vaddr = (unsigned long __user *)
 393                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 394
 395         if ((unsigned long)vaddr & 3) {
 396                 signal = SIGBUS;
 397                 goto sig;
 398         }
 399         if (get_user(value, vaddr)) {
 400                 signal = SIGSEGV;
 401                 goto sig;
 402         }
 403
 404         preempt_disable();
 405
 406         if (ll_task == NULL || ll_task == current) {
 407                 ll_bit = 1;
 408         } else {
 409                 ll_bit = 0;
 410         }
 411         ll_task = current;
 412
 413         preempt_enable();
 414
 415         compute_return_epc(regs);
 416
 417         regs->regs[(opcode & RT) >> 16] = value;
 418
 419         return;
 420
 421 sig:
 422         force_sig(signal, current);
 423 }
 424
 425 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 426 {
 427         unsigned long __user *vaddr;
 428         unsigned long reg;
 429         long offset;
 430         int signal = 0;
 431
 432         /*
 433          * analyse the sc instruction that just caused a ri exception
 434          * and put the referenced address to addr.
 435          */
 436
 437         /* sign extend offset */
 438         offset = opcode & OFFSET;
 439         offset <<= 16;
 440         offset >>= 16;
 441
 442         vaddr = (unsigned long __user *)
 443                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 444         reg = (opcode & RT) >> 16;
 445
 446         if ((unsigned long)vaddr & 3) {
 447                 signal = SIGBUS;
 448                 goto sig;
 449         }
 450
 451         preempt_disable();
 452
 453         if (ll_bit == 0 || ll_task != current) {
 454                 compute_return_epc(regs);
 455                 regs->regs[reg] = 0;
 456                 preempt_enable();
 457                 return;
 458         }
 459
 460         preempt_enable();
 461
 462         if (put_user(regs->regs[reg], vaddr)) {
 463                 signal = SIGSEGV;
 464                 goto sig;
 465         }
 466
 467         compute_return_epc(regs);
 468         regs->regs[reg] = 1;
 469
 470         return;
 471
 472 sig:
 473         force_sig(signal, current);
 474 }
 475
 476 /*
 477  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 478  * opcodes are supposed to result in coprocessor unusable exceptions if
 479  * executed on ll/sc-less processors.  That's the theory.  In practice a
 480  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 481  * instead, so we're doing the emulation thing in both exception handlers.
 482  */
 483 static inline int simulate_llsc(struct pt_regs *regs)
 484 {
 485         unsigned int opcode;
 486
 487         if (unlikely(get_insn_opcode(regs, &opcode)))
 488                 return -EFAULT;
 489
 490         if ((opcode & OPCODE) == LL) {
 491                 simulate_ll(regs, opcode);
 492                 return 0;
 493         }
 494         if ((opcode & OPCODE) == SC) {
 495                 simulate_sc(regs, opcode);
 496                 return 0;
 497         }
 498
 499         return -EFAULT;                 /* Strange things going on ... */
 500 }
 501
 502 /*
 503  * Simulate trapping 'rdhwr' instructions to provide user accessible
 504  * registers not implemented in hardware.  The only current use of this
 505  * is the thread area pointer.
 506  */
 507 static inline int simulate_rdhwr(struct pt_regs *regs)
 508 {
 509         struct thread_info *ti = current->thread_info;
 510         unsigned int opcode;
 511
 512         if (unlikely(get_insn_opcode(regs, &opcode)))
 513                 return -EFAULT;
 514
 515         if (unlikely(compute_return_epc(regs)))
 516                 return -EFAULT;
 517
 518         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 519                 int rd = (opcode & RD) >> 11;
 520                 int rt = (opcode & RT) >> 16;
 521                 switch (rd) {
 522                         case 29:
 523                                 regs->regs[rt] = ti->tp_value;
 524                                 break;
 525                         default:
 526                                 return -EFAULT;
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532
 533 asmlinkage void do_ov(struct pt_regs *regs)
 534 {
 535         siginfo_t info;
 536
 537         info.si_code = FPE_INTOVF;
 538         info.si_signo = SIGFPE;
 539         info.si_errno = 0;
 540         info.si_addr = (void __user *) regs->cp0_epc;
 541         force_sig_info(SIGFPE, &info, current);
 542 }
 543
 544 /*
 545  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 546  */
 547 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 548 {
 549         if (fcr31 & FPU_CSR_UNI_X) {
 550                 int sig;
 551
 552                 preempt_disable();
 553
 554 #ifdef CONFIG_PREEMPT
 555                 if (!is_fpu_owner()) {
 556                         /* We might lose fpu before disabling preempt... */
 557                         own_fpu();
 558                         BUG_ON(!used_math());
 559                         restore_fp(current);
 560                 }
 561 #endif
 562                 /*
 563                  * Unimplemented operation exception.  If we've got the full
 564                  * software emulator on-board, let's use it...
 565                  *
 566                  * Force FPU to dump state into task/thread context.  We're
 567                  * moving a lot of data here for what is probably a single
 568                  * instruction, but the alternative is to pre-decode the FP
 569                  * register operands before invoking the emulator, which seems
 570                  * a bit extreme for what should be an infrequent event.
 571                  */
 572                 save_fp(current);
 573                 /* Ensure 'resume' not overwrite saved fp context again. */
 574                 lose_fpu();
 575
 576                 preempt_enable();
 577
 578                 /* Run the emulator */
 579                 sig = fpu_emulator_cop1Handler (0, regs,
 580                         &current->thread.fpu.soft);
 581
 582                 preempt_disable();
 583
 584                 own_fpu();      /* Using the FPU again.  */
 585                 /*
 586                  * We can't allow the emulated instruction to leave any of
 587                  * the cause bit set in $fcr31.
 588                  */
 589                 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
 590
 591                 /* Restore the hardware register state */
 592                 restore_fp(current);
 593
 594                 preempt_enable();
 595
 596                 /* If something went wrong, signal */
 597                 if (sig)
 598                         force_sig(sig, current);
 599
 600                 return;
 601         }
 602
 603         force_sig(SIGFPE, current);
 604 }
 605
 606 asmlinkage void do_bp(struct pt_regs *regs)
 607 {
 608         unsigned int opcode, bcode;
 609         siginfo_t info;
 610
 611         die_if_kernel("Break instruction in kernel code", regs);
 612
 613         if (get_insn_opcode(regs, &opcode))
 614                 return;
 615
 616         /*
 617          * There is the ancient bug in the MIPS assemblers that the break
 618          * code starts left to bit 16 instead to bit 6 in the opcode.
 619          * Gas is bug-compatible, but not always, grrr...
 620          * We handle both cases with a simple heuristics.  --macro
 621          */
 622         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 623         if (bcode < (1 << 10))
 624                 bcode <<= 10;
 625
 626         /*
 627          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 628          * insns, even for break codes that indicate arithmetic failures.
 629          * Weird ...)
 630          * But should we continue the brokenness???  --macro
 631          */
 632         switch (bcode) {
 633         case BRK_OVERFLOW << 10:
 634         case BRK_DIVZERO << 10:
 635                 if (bcode == (BRK_DIVZERO << 10))
 636                         info.si_code = FPE_INTDIV;
 637                 else
 638                         info.si_code = FPE_INTOVF;
 639                 info.si_signo = SIGFPE;
 640                 info.si_errno = 0;
 641                 info.si_addr = (void __user *) regs->cp0_epc;
 642                 force_sig_info(SIGFPE, &info, current);
 643                 break;
 644         default:
 645                 force_sig(SIGTRAP, current);
 646         }
 647 }
 648
 649 asmlinkage void do_tr(struct pt_regs *regs)
 650 {
 651         unsigned int opcode, tcode = 0;
 652         siginfo_t info;
 653
 654         die_if_kernel("Trap instruction in kernel code", regs);
 655
 656         if (get_insn_opcode(regs, &opcode))
 657                 return;
 658
 659         /* Immediate versions don't provide a code.  */
 660         if (!(opcode & OPCODE))
 661                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 662
 663         /*
 664          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 665          * insns, even for trap codes that indicate arithmetic failures.
 666          * Weird ...)
 667          * But should we continue the brokenness???  --macro
 668          */
 669         switch (tcode) {
 670         case BRK_OVERFLOW:
 671         case BRK_DIVZERO:
 672                 if (tcode == BRK_DIVZERO)
 673                         info.si_code = FPE_INTDIV;
 674                 else
 675                         info.si_code = FPE_INTOVF;
 676                 info.si_signo = SIGFPE;
 677                 info.si_errno = 0;
 678                 info.si_addr = (void __user *) regs->cp0_epc;
 679                 force_sig_info(SIGFPE, &info, current);
 680                 break;
 681         default:
 682                 force_sig(SIGTRAP, current);
 683         }
 684 }
 685
 686 asmlinkage void do_ri(struct pt_regs *regs)
 687 {
 688         die_if_kernel("Reserved instruction in kernel code", regs);
 689
 690         if (!cpu_has_llsc)
 691                 if (!simulate_llsc(regs))
 692                         return;
 693
 694         if (!simulate_rdhwr(regs))
 695                 return;
 696
 697         force_sig(SIGILL, current);
 698 }
 699
 700 asmlinkage void do_cpu(struct pt_regs *regs)
 701 {
 702         unsigned int cpid;
 703
 704         die_if_kernel("do_cpu invoked from kernel context!", regs);
 705
 706         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 707
 708         switch (cpid) {
 709         case 0:
 710                 if (!cpu_has_llsc)
 711                         if (!simulate_llsc(regs))
 712                                 return;
 713
 714                 if (!simulate_rdhwr(regs))
 715                         return;
 716
 717                 break;
 718
 719         case 1:
 720                 preempt_disable();
 721
 722                 own_fpu();
 723                 if (used_math()) {      /* Using the FPU again.  */
 724                         restore_fp(current);
 725                 } else {                        /* First time FPU user.  */
 726                         init_fpu();
 727                         set_used_math();
 728                 }
 729
 730                 preempt_enable();
 731
 732                 if (!cpu_has_fpu) {
 733                         int sig = fpu_emulator_cop1Handler(0, regs,
 734                                                 &current->thread.fpu.soft);
 735                         if (sig)
 736                                 force_sig(sig, current);
 737                 }
 738
 739                 return;
 740
 741         case 2:
 742         case 3:
 743                 break;
 744         }
 745
 746         force_sig(SIGILL, current);
 747 }
 748
 749 asmlinkage void do_mdmx(struct pt_regs *regs)
 750 {
 751         force_sig(SIGILL, current);
 752 }
 753
 754 asmlinkage void do_watch(struct pt_regs *regs)
 755 {
 756         /*
 757          * We use the watch exception where available to detect stack
 758          * overflows.
 759          */
 760         dump_tlb_all();
 761         show_regs(regs);
 762         panic("Caught WATCH exception - probably caused by stack overflow.");
 763 }
 764
 765 asmlinkage void do_mcheck(struct pt_regs *regs)
 766 {
 767         show_regs(regs);
 768         dump_tlb_all();
 769         /*
 770          * Some chips may have other causes of machine check (e.g. SB1
 771          * graduation timer)
 772          */
 773         panic("Caught Machine Check exception - %scaused by multiple "
 774               "matching entries in the TLB.",
 775               (regs->cp0_status & ST0_TS) ? "" : "not ");
 776 }
 777
 778 asmlinkage void do_reserved(struct pt_regs *regs)
 779 {
 780         /*
 781          * Game over - no way to handle this if it ever occurs.  Most probably
 782          * caused by a new unknown cpu type or after another deadly
 783          * hard/software error.
 784          */
 785         show_regs(regs);
 786         panic("Caught reserved exception %ld - should not happen.",
 787               (regs->cp0_cause & 0x7f) >> 2);
 788 }
 789
 790 /*
 791  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 792  * it different ways.
 793  */
 794 static inline void parity_protection_init(void)
 795 {
 796         switch (current_cpu_data.cputype) {
 797         case CPU_24K:
 798         case CPU_5KC:
 799                 write_c0_ecc(0x80000000);
 800                 back_to_back_c0_hazard();
 801                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 802                 printk(KERN_INFO "Cache parity protection %sabled\n",
 803                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 804                 break;
 805         case CPU_20KC:
 806         case CPU_25KF:
 807                 /* Clear the DE bit (bit 16) in the c0_status register. */
 808                 printk(KERN_INFO "Enable cache parity protection for "
 809                        "MIPS 20KC/25KF CPUs.\n");
 810                 clear_c0_status(ST0_DE);
 811                 break;
 812         default:
 813                 break;
 814         }
 815 }
 816
 817 asmlinkage void cache_parity_error(void)
 818 {
 819         const int field = 2 * sizeof(unsigned long);
 820         unsigned int reg_val;
 821
 822         /* For the moment, report the problem and hang. */
 823         printk("Cache error exception:\n");
 824         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 825         reg_val = read_c0_cacheerr();
 826         printk("c0_cacheerr == %08x\n", reg_val);
 827
 828         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 829                reg_val & (1<<30) ? "secondary" : "primary",
 830                reg_val & (1<<31) ? "data" : "insn");
 831         printk("Error bits: %s%s%s%s%s%s%s\n",
 832                reg_val & (1<<29) ? "ED " : "",
 833                reg_val & (1<<28) ? "ET " : "",
 834                reg_val & (1<<26) ? "EE " : "",
 835                reg_val & (1<<25) ? "EB " : "",
 836                reg_val & (1<<24) ? "EI " : "",
 837                reg_val & (1<<23) ? "E1 " : "",
 838                reg_val & (1<<22) ? "E0 " : "");
 839         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 840
 841 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
 842         if (reg_val & (1<<22))
 843                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
 844
 845         if (reg_val & (1<<23))
 846                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
 847 #endif
 848
 849         panic("Can't handle the cache error!");
 850 }
 851
 852 /*
 853  * SDBBP EJTAG debug exception handler.
 854  * We skip the instruction and return to the next instruction.
 855  */
 856 void ejtag_exception_handler(struct pt_regs *regs)
 857 {
 858         const int field = 2 * sizeof(unsigned long);
 859         unsigned long depc, old_epc;
 860         unsigned int debug;
 861
 862         printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
 863         depc = read_c0_depc();
 864         debug = read_c0_debug();
 865         printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
 866         if (debug & 0x80000000) {
 867                 /*
 868                  * In branch delay slot.
 869                  * We cheat a little bit here and use EPC to calculate the
 870                  * debug return address (DEPC). EPC is restored after the
 871                  * calculation.
 872                  */
 873                 old_epc = regs->cp0_epc;
 874                 regs->cp0_epc = depc;
 875                 __compute_return_epc(regs);
 876                 depc = regs->cp0_epc;
 877                 regs->cp0_epc = old_epc;
 878         } else
 879                 depc += 4;
 880         write_c0_depc(depc);
 881
 882 #if 0
 883         printk("\n\n----- Enable EJTAG single stepping ----\n\n");
 884         write_c0_debug(debug | 0x100);
 885 #endif
 886 }
 887
 888 /*
 889  * NMI exception handler.
 890  */
 891 void nmi_exception_handler(struct pt_regs *regs)
 892 {
 893         printk("NMI taken!!!!\n");
 894         die("NMI", regs);
 895         while(1) ;
 896 }
 897
 898 unsigned long exception_handlers[32];
 899
 900 /*
 901  * As a side effect of the way this is implemented we're limited
 902  * to interrupt handlers in the address range from
 903  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
 904  */
 905 void *set_except_vector(int n, void *addr)
 906 {
 907         unsigned long handler = (unsigned long) addr;
 908         unsigned long old_handler = exception_handlers[n];
 909
 910         exception_handlers[n] = handler;
 911         if (n == 0 && cpu_has_divec) {
 912                 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
 913                                                  (0x03ffffff & (handler >> 2));
 914                 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
 915         }
 916         return (void *)old_handler;
 917 }
 918
 919 /*
 920  * This is used by native signal handling
 921  */
 922 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
 923 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
 924
 925 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
 926 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
 927
 928 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
 929 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
 930
 931 static inline void signal_init(void)
 932 {
 933         if (cpu_has_fpu) {
 934                 save_fp_context = _save_fp_context;
 935                 restore_fp_context = _restore_fp_context;
 936         } else {
 937                 save_fp_context = fpu_emulator_save_context;
 938                 restore_fp_context = fpu_emulator_restore_context;
 939         }
 940 }
 941
 942 #ifdef CONFIG_MIPS32_COMPAT
 943
 944 /*
 945  * This is used by 32-bit signal stuff on the 64-bit kernel
 946  */
 947 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
 948 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
 949
 950 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
 951 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
 952
 953 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
 954 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
 955
 956 static inline void signal32_init(void)
 957 {
 958         if (cpu_has_fpu) {
 959                 save_fp_context32 = _save_fp_context32;
 960                 restore_fp_context32 = _restore_fp_context32;
 961         } else {
 962                 save_fp_context32 = fpu_emulator_save_context32;
 963                 restore_fp_context32 = fpu_emulator_restore_context32;
 964         }
 965 }
 966 #endif
 967
 968 extern void cpu_cache_init(void);
 969 extern void tlb_init(void);
 970
 971 void __init per_cpu_trap_init(void)
 972 {
 973         unsigned int cpu = smp_processor_id();
 974         unsigned int status_set = ST0_CU0;
 975
 976         /*
 977          * Disable coprocessors and select 32-bit or 64-bit addressing
 978          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
 979          * flag that some firmware may have left set and the TS bit (for
 980          * IP27).  Set XX for ISA IV code to work.
 981          */
 982 #ifdef CONFIG_64BIT
 983         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 984 #endif
 985         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
 986                 status_set |= ST0_XX;
 987         change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
 988                          status_set);
 989
 990         /*
 991          * Some MIPS CPUs have a dedicated interrupt vector which reduces the
 992          * interrupt processing overhead.  Use it where available.
 993          */
 994         if (cpu_has_divec)
 995                 set_c0_cause(CAUSEF_IV);
 996
 997         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 998         TLBMISS_HANDLER_SETUP();
 999
1000         atomic_inc(&init_mm.mm_count);
1001         current->active_mm = &init_mm;
1002         BUG_ON(current->mm);
1003         enter_lazy_tlb(&init_mm, current);
1004
1005         cpu_cache_init();
1006         tlb_init();
1007 }
1008
1009 void __init trap_init(void)
1010 {
1011         extern char except_vec3_generic, except_vec3_r4000;
1012         extern char except_vec_ejtag_debug;
1013         extern char except_vec4;
1014         unsigned long i;
1015
1016         per_cpu_trap_init();
1017
1018         /*
1019          * Copy the generic exception handlers to their final destination.
1020          * This will be overriden later as suitable for a particular
1021          * configuration.
1022          */
1023         memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1024
1025         /*
1026          * Setup default vectors
1027          */
1028         for (i = 0; i <= 31; i++)
1029                 set_except_vector(i, handle_reserved);
1030
1031         /*
1032          * Copy the EJTAG debug exception vector handler code to it's final
1033          * destination.
1034          */
1035         if (cpu_has_ejtag)
1036                 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
1037
1038         /*
1039          * Only some CPUs have the watch exceptions.
1040          */
1041         if (cpu_has_watch)
1042                 set_except_vector(23, handle_watch);
1043
1044         /*
1045          * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1046          * interrupt processing overhead.  Use it where available.
1047          */
1048         if (cpu_has_divec)
1049                 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
1050
1051         /*
1052          * Some CPUs can enable/disable for cache parity detection, but does
1053          * it different ways.
1054          */
1055         parity_protection_init();
1056
1057         /*
1058          * The Data Bus Errors / Instruction Bus Errors are signaled
1059          * by external hardware.  Therefore these two exceptions
1060          * may have board specific handlers.
1061          */
1062         if (board_be_init)
1063                 board_be_init();
1064
1065         set_except_vector(1, handle_tlbm);
1066         set_except_vector(2, handle_tlbl);
1067         set_except_vector(3, handle_tlbs);
1068
1069         set_except_vector(4, handle_adel);
1070         set_except_vector(5, handle_ades);
1071
1072         set_except_vector(6, handle_ibe);
1073         set_except_vector(7, handle_dbe);
1074
1075         set_except_vector(8, handle_sys);
1076         set_except_vector(9, handle_bp);
1077         set_except_vector(10, handle_ri);
1078         set_except_vector(11, handle_cpu);
1079         set_except_vector(12, handle_ov);
1080         set_except_vector(13, handle_tr);
1081         set_except_vector(22, handle_mdmx);
1082
1083         if (cpu_has_fpu && !cpu_has_nofpuex)
1084                 set_except_vector(15, handle_fpe);
1085
1086         if (cpu_has_mcheck)
1087                 set_except_vector(24, handle_mcheck);
1088
1089         if (cpu_has_vce)
1090                 /* Special exception: R4[04]00 uses also the divec space. */
1091                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1092         else if (cpu_has_4kex)
1093                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1094         else
1095                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1096
1097         if (current_cpu_data.cputype == CPU_R6000 ||
1098             current_cpu_data.cputype == CPU_R6000A) {
1099                 /*
1100                  * The R6000 is the only R-series CPU that features a machine
1101                  * check exception (similar to the R4000 cache error) and
1102                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1103                  * written yet.  Well, anyway there is no R6000 machine on the
1104                  * current list of targets for Linux/MIPS.
1105                  * (Duh, crap, there is someone with a triple R6k machine)
1106                  */
1107                 //set_except_vector(14, handle_mc);
1108                 //set_except_vector(15, handle_ndc);
1109         }
1110
1111         signal_init();
1112 #ifdef CONFIG_MIPS32_COMPAT
1113         signal32_init();
1114 #endif
1115
1116         flush_icache_range(CAC_BASE, CAC_BASE + 0x400);
1117 }