2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
30 #include <asm/module.h>
31 #include <asm/pgtable.h>
32 #include <asm/ptrace.h>
33 #include <asm/sections.h>
34 #include <asm/system.h>
35 #include <asm/tlbdebug.h>
36 #include <asm/traps.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/watch.h>
40 #include <asm/types.h>
42 extern asmlinkage
void handle_tlbm(void);
43 extern asmlinkage
void handle_tlbl(void);
44 extern asmlinkage
void handle_tlbs(void);
45 extern asmlinkage
void handle_adel(void);
46 extern asmlinkage
void handle_ades(void);
47 extern asmlinkage
void handle_ibe(void);
48 extern asmlinkage
void handle_dbe(void);
49 extern asmlinkage
void handle_sys(void);
50 extern asmlinkage
void handle_bp(void);
51 extern asmlinkage
void handle_ri(void);
52 extern asmlinkage
void handle_cpu(void);
53 extern asmlinkage
void handle_ov(void);
54 extern asmlinkage
void handle_tr(void);
55 extern asmlinkage
void handle_fpe(void);
56 extern asmlinkage
void handle_mdmx(void);
57 extern asmlinkage
void handle_watch(void);
58 extern asmlinkage
void handle_dsp(void);
59 extern asmlinkage
void handle_mcheck(void);
60 extern asmlinkage
void handle_reserved(void);
62 extern int fpu_emulator_cop1Handler(int xcptno
, struct pt_regs
*xcp
,
63 struct mips_fpu_soft_struct
*ctx
);
65 void (*board_be_init
)(void);
66 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
69 * These constant is for searching for possible module text segments.
70 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
72 #define MODULE_RANGE (8*1024*1024)
75 * This routine abuses get_user()/put_user() to reference pointers
76 * with at least a bit of error checking ...
78 void show_stack(struct task_struct
*task
, unsigned long *sp
)
80 const int field
= 2 * sizeof(unsigned long);
85 if (task
&& task
!= current
)
86 sp
= (unsigned long *) task
->thread
.reg29
;
88 sp
= (unsigned long *) &sp
;
93 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
94 if (i
&& ((i
% (64 / field
)) == 0))
101 if (__get_user(stackdata
, sp
++)) {
102 printk(" (Bad stack address)");
106 printk(" %0*lx", field
, stackdata
);
112 void show_trace(struct task_struct
*task
, unsigned long *stack
)
114 const int field
= 2 * sizeof(unsigned long);
118 if (task
&& task
!= current
)
119 stack
= (unsigned long *) task
->thread
.reg29
;
121 stack
= (unsigned long *) &stack
;
124 printk("Call Trace:");
125 #ifdef CONFIG_KALLSYMS
128 while (!kstack_end(stack
)) {
130 if (__kernel_text_address(addr
)) {
131 printk(" [<%0*lx>] ", field
, addr
);
132 print_symbol("%s\n", addr
);
139 * The architecture-independent dump_stack generator
141 void dump_stack(void)
145 show_trace(current
, &stack
);
148 EXPORT_SYMBOL(dump_stack
);
150 void show_code(unsigned int *pc
)
156 for(i
= -3 ; i
< 6 ; i
++) {
158 if (__get_user(insn
, pc
+ i
)) {
159 printk(" (Bad address in epc)\n");
162 printk("%c%08x%c", (i
?' ':'<'), insn
, (i
?' ':'>'));
166 void show_regs(struct pt_regs
*regs
)
168 const int field
= 2 * sizeof(unsigned long);
169 unsigned int cause
= regs
->cp0_cause
;
172 printk("Cpu %d\n", smp_processor_id());
175 * Saved main processor registers
177 for (i
= 0; i
< 32; ) {
181 printk(" %0*lx", field
, 0UL);
182 else if (i
== 26 || i
== 27)
183 printk(" %*s", field
, "");
185 printk(" %0*lx", field
, regs
->regs
[i
]);
192 printk("Hi : %0*lx\n", field
, regs
->hi
);
193 printk("Lo : %0*lx\n", field
, regs
->lo
);
196 * Saved cp0 registers
198 printk("epc : %0*lx ", field
, regs
->cp0_epc
);
199 print_symbol("%s ", regs
->cp0_epc
);
200 printk(" %s\n", print_tainted());
201 printk("ra : %0*lx ", field
, regs
->regs
[31]);
202 print_symbol("%s\n", regs
->regs
[31]);
204 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
206 if (regs
->cp0_status
& ST0_KX
)
208 if (regs
->cp0_status
& ST0_SX
)
210 if (regs
->cp0_status
& ST0_UX
)
212 switch (regs
->cp0_status
& ST0_KSU
) {
217 printk("SUPERVISOR ");
226 if (regs
->cp0_status
& ST0_ERL
)
228 if (regs
->cp0_status
& ST0_EXL
)
230 if (regs
->cp0_status
& ST0_IE
)
234 printk("Cause : %08x\n", cause
);
236 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
237 if (1 <= cause
&& cause
<= 5)
238 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
240 printk("PrId : %08x\n", read_c0_prid());
243 void show_registers(struct pt_regs
*regs
)
247 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
248 current
->comm
, current
->pid
, current_thread_info(), current
);
249 show_stack(current
, (long *) regs
->regs
[29]);
250 show_trace(current
, (long *) regs
->regs
[29]);
251 show_code((unsigned int *) regs
->cp0_epc
);
255 static DEFINE_SPINLOCK(die_lock
);
257 NORET_TYPE
void __die(const char * str
, struct pt_regs
* regs
,
258 const char * file
, const char * func
, unsigned long line
)
260 static int die_counter
;
263 spin_lock_irq(&die_lock
);
266 printk(" in %s:%s, line %ld", file
, func
, line
);
267 printk("[#%d]:\n", ++die_counter
);
268 show_registers(regs
);
269 spin_unlock_irq(&die_lock
);
273 void __die_if_kernel(const char * str
, struct pt_regs
* regs
,
274 const char * file
, const char * func
, unsigned long line
)
276 if (!user_mode(regs
))
277 __die(str
, regs
, file
, func
, line
);
280 extern const struct exception_table_entry __start___dbe_table
[];
281 extern const struct exception_table_entry __stop___dbe_table
[];
283 void __declare_dbe_table(void)
285 __asm__
__volatile__(
286 ".section\t__dbe_table,\"a\"\n\t"
291 /* Given an address, look for it in the exception tables. */
292 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
294 const struct exception_table_entry
*e
;
296 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
298 e
= search_module_dbetables(addr
);
302 asmlinkage
void do_be(struct pt_regs
*regs
)
304 const int field
= 2 * sizeof(unsigned long);
305 const struct exception_table_entry
*fixup
= NULL
;
306 int data
= regs
->cp0_cause
& 4;
307 int action
= MIPS_BE_FATAL
;
309 /* XXX For now. Fixme, this searches the wrong table ... */
310 if (data
&& !user_mode(regs
))
311 fixup
= search_dbe_tables(exception_epc(regs
));
314 action
= MIPS_BE_FIXUP
;
316 if (board_be_handler
)
317 action
= board_be_handler(regs
, fixup
!= 0);
320 case MIPS_BE_DISCARD
:
324 regs
->cp0_epc
= fixup
->nextinsn
;
333 * Assume it would be too dangerous to continue ...
335 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
336 data
? "Data" : "Instruction",
337 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
338 die_if_kernel("Oops", regs
);
339 force_sig(SIGBUS
, current
);
342 static inline int get_insn_opcode(struct pt_regs
*regs
, unsigned int *opcode
)
344 unsigned int __user
*epc
;
346 epc
= (unsigned int __user
*) regs
->cp0_epc
+
347 ((regs
->cp0_cause
& CAUSEF_BD
) != 0);
348 if (!get_user(*opcode
, epc
))
351 force_sig(SIGSEGV
, current
);
359 #define OPCODE 0xfc000000
360 #define BASE 0x03e00000
361 #define RT 0x001f0000
362 #define OFFSET 0x0000ffff
363 #define LL 0xc0000000
364 #define SC 0xe0000000
365 #define SPEC3 0x7c000000
366 #define RD 0x0000f800
367 #define FUNC 0x0000003f
368 #define RDHWR 0x0000003b
371 * The ll_bit is cleared by r*_switch.S
374 unsigned long ll_bit
;
376 static struct task_struct
*ll_task
= NULL
;
378 static inline void simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
380 unsigned long value
, __user
*vaddr
;
385 * analyse the ll instruction that just caused a ri exception
386 * and put the referenced address to addr.
389 /* sign extend offset */
390 offset
= opcode
& OFFSET
;
394 vaddr
= (unsigned long __user
*)
395 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
397 if ((unsigned long)vaddr
& 3) {
401 if (get_user(value
, vaddr
)) {
408 if (ll_task
== NULL
|| ll_task
== current
) {
417 compute_return_epc(regs
);
419 regs
->regs
[(opcode
& RT
) >> 16] = value
;
424 force_sig(signal
, current
);
427 static inline void simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
429 unsigned long __user
*vaddr
;
435 * analyse the sc instruction that just caused a ri exception
436 * and put the referenced address to addr.
439 /* sign extend offset */
440 offset
= opcode
& OFFSET
;
444 vaddr
= (unsigned long __user
*)
445 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
446 reg
= (opcode
& RT
) >> 16;
448 if ((unsigned long)vaddr
& 3) {
455 if (ll_bit
== 0 || ll_task
!= current
) {
456 compute_return_epc(regs
);
464 if (put_user(regs
->regs
[reg
], vaddr
)) {
469 compute_return_epc(regs
);
475 force_sig(signal
, current
);
479 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
480 * opcodes are supposed to result in coprocessor unusable exceptions if
481 * executed on ll/sc-less processors. That's the theory. In practice a
482 * few processors such as NEC's VR4100 throw reserved instruction exceptions
483 * instead, so we're doing the emulation thing in both exception handlers.
485 static inline int simulate_llsc(struct pt_regs
*regs
)
489 if (unlikely(get_insn_opcode(regs
, &opcode
)))
492 if ((opcode
& OPCODE
) == LL
) {
493 simulate_ll(regs
, opcode
);
496 if ((opcode
& OPCODE
) == SC
) {
497 simulate_sc(regs
, opcode
);
501 return -EFAULT
; /* Strange things going on ... */
505 * Simulate trapping 'rdhwr' instructions to provide user accessible
506 * registers not implemented in hardware. The only current use of this
507 * is the thread area pointer.
509 static inline int simulate_rdhwr(struct pt_regs
*regs
)
511 struct thread_info
*ti
= current
->thread_info
;
514 if (unlikely(get_insn_opcode(regs
, &opcode
)))
517 if (unlikely(compute_return_epc(regs
)))
520 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
521 int rd
= (opcode
& RD
) >> 11;
522 int rt
= (opcode
& RT
) >> 16;
525 regs
->regs
[rt
] = ti
->tp_value
;
535 asmlinkage
void do_ov(struct pt_regs
*regs
)
539 info
.si_code
= FPE_INTOVF
;
540 info
.si_signo
= SIGFPE
;
542 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
543 force_sig_info(SIGFPE
, &info
, current
);
547 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
549 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
551 if (fcr31
& FPU_CSR_UNI_X
) {
556 #ifdef CONFIG_PREEMPT
557 if (!is_fpu_owner()) {
558 /* We might lose fpu before disabling preempt... */
560 BUG_ON(!used_math());
565 * Unimplemented operation exception. If we've got the full
566 * software emulator on-board, let's use it...
568 * Force FPU to dump state into task/thread context. We're
569 * moving a lot of data here for what is probably a single
570 * instruction, but the alternative is to pre-decode the FP
571 * register operands before invoking the emulator, which seems
572 * a bit extreme for what should be an infrequent event.
575 /* Ensure 'resume' not overwrite saved fp context again. */
580 /* Run the emulator */
581 sig
= fpu_emulator_cop1Handler (0, regs
,
582 ¤t
->thread
.fpu
.soft
);
586 own_fpu(); /* Using the FPU again. */
588 * We can't allow the emulated instruction to leave any of
589 * the cause bit set in $fcr31.
591 current
->thread
.fpu
.soft
.fcr31
&= ~FPU_CSR_ALL_X
;
593 /* Restore the hardware register state */
598 /* If something went wrong, signal */
600 force_sig(sig
, current
);
605 force_sig(SIGFPE
, current
);
608 asmlinkage
void do_bp(struct pt_regs
*regs
)
610 unsigned int opcode
, bcode
;
613 die_if_kernel("Break instruction in kernel code", regs
);
615 if (get_insn_opcode(regs
, &opcode
))
619 * There is the ancient bug in the MIPS assemblers that the break
620 * code starts left to bit 16 instead to bit 6 in the opcode.
621 * Gas is bug-compatible, but not always, grrr...
622 * We handle both cases with a simple heuristics. --macro
624 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
625 if (bcode
< (1 << 10))
629 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
630 * insns, even for break codes that indicate arithmetic failures.
632 * But should we continue the brokenness??? --macro
635 case BRK_OVERFLOW
<< 10:
636 case BRK_DIVZERO
<< 10:
637 if (bcode
== (BRK_DIVZERO
<< 10))
638 info
.si_code
= FPE_INTDIV
;
640 info
.si_code
= FPE_INTOVF
;
641 info
.si_signo
= SIGFPE
;
643 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
644 force_sig_info(SIGFPE
, &info
, current
);
647 force_sig(SIGTRAP
, current
);
651 asmlinkage
void do_tr(struct pt_regs
*regs
)
653 unsigned int opcode
, tcode
= 0;
656 die_if_kernel("Trap instruction in kernel code", regs
);
658 if (get_insn_opcode(regs
, &opcode
))
661 /* Immediate versions don't provide a code. */
662 if (!(opcode
& OPCODE
))
663 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
666 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
667 * insns, even for trap codes that indicate arithmetic failures.
669 * But should we continue the brokenness??? --macro
674 if (tcode
== BRK_DIVZERO
)
675 info
.si_code
= FPE_INTDIV
;
677 info
.si_code
= FPE_INTOVF
;
678 info
.si_signo
= SIGFPE
;
680 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
681 force_sig_info(SIGFPE
, &info
, current
);
684 force_sig(SIGTRAP
, current
);
688 asmlinkage
void do_ri(struct pt_regs
*regs
)
690 die_if_kernel("Reserved instruction in kernel code", regs
);
693 if (!simulate_llsc(regs
))
696 if (!simulate_rdhwr(regs
))
699 force_sig(SIGILL
, current
);
702 asmlinkage
void do_cpu(struct pt_regs
*regs
)
706 die_if_kernel("do_cpu invoked from kernel context!", regs
);
708 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
713 if (!simulate_llsc(regs
))
716 if (!simulate_rdhwr(regs
))
725 if (used_math()) { /* Using the FPU again. */
727 } else { /* First time FPU user. */
735 int sig
= fpu_emulator_cop1Handler(0, regs
,
736 ¤t
->thread
.fpu
.soft
);
738 force_sig(sig
, current
);
748 force_sig(SIGILL
, current
);
751 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
753 force_sig(SIGILL
, current
);
756 asmlinkage
void do_watch(struct pt_regs
*regs
)
759 * We use the watch exception where available to detect stack
764 panic("Caught WATCH exception - probably caused by stack overflow.");
767 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
772 * Some chips may have other causes of machine check (e.g. SB1
775 panic("Caught Machine Check exception - %scaused by multiple "
776 "matching entries in the TLB.",
777 (regs
->cp0_status
& ST0_TS
) ? "" : "not ");
780 asmlinkage
void do_dsp(struct pt_regs
*regs
)
783 panic("Unexpected DSP exception\n");
785 force_sig(SIGILL
, current
);
788 asmlinkage
void do_reserved(struct pt_regs
*regs
)
791 * Game over - no way to handle this if it ever occurs. Most probably
792 * caused by a new unknown cpu type or after another deadly
793 * hard/software error.
796 panic("Caught reserved exception %ld - should not happen.",
797 (regs
->cp0_cause
& 0x7f) >> 2);
801 * Some MIPS CPUs can enable/disable for cache parity detection, but do
804 static inline void parity_protection_init(void)
806 switch (current_cpu_data
.cputype
) {
809 write_c0_ecc(0x80000000);
810 back_to_back_c0_hazard();
811 /* Set the PE bit (bit 31) in the c0_errctl register. */
812 printk(KERN_INFO
"Cache parity protection %sabled\n",
813 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
817 /* Clear the DE bit (bit 16) in the c0_status register. */
818 printk(KERN_INFO
"Enable cache parity protection for "
819 "MIPS 20KC/25KF CPUs.\n");
820 clear_c0_status(ST0_DE
);
827 asmlinkage
void cache_parity_error(void)
829 const int field
= 2 * sizeof(unsigned long);
830 unsigned int reg_val
;
832 /* For the moment, report the problem and hang. */
833 printk("Cache error exception:\n");
834 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
835 reg_val
= read_c0_cacheerr();
836 printk("c0_cacheerr == %08x\n", reg_val
);
838 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
839 reg_val
& (1<<30) ? "secondary" : "primary",
840 reg_val
& (1<<31) ? "data" : "insn");
841 printk("Error bits: %s%s%s%s%s%s%s\n",
842 reg_val
& (1<<29) ? "ED " : "",
843 reg_val
& (1<<28) ? "ET " : "",
844 reg_val
& (1<<26) ? "EE " : "",
845 reg_val
& (1<<25) ? "EB " : "",
846 reg_val
& (1<<24) ? "EI " : "",
847 reg_val
& (1<<23) ? "E1 " : "",
848 reg_val
& (1<<22) ? "E0 " : "");
849 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
851 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
852 if (reg_val
& (1<<22))
853 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
855 if (reg_val
& (1<<23))
856 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
859 panic("Can't handle the cache error!");
863 * SDBBP EJTAG debug exception handler.
864 * We skip the instruction and return to the next instruction.
866 void ejtag_exception_handler(struct pt_regs
*regs
)
868 const int field
= 2 * sizeof(unsigned long);
869 unsigned long depc
, old_epc
;
872 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
873 depc
= read_c0_depc();
874 debug
= read_c0_debug();
875 printk("c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
876 if (debug
& 0x80000000) {
878 * In branch delay slot.
879 * We cheat a little bit here and use EPC to calculate the
880 * debug return address (DEPC). EPC is restored after the
883 old_epc
= regs
->cp0_epc
;
884 regs
->cp0_epc
= depc
;
885 __compute_return_epc(regs
);
886 depc
= regs
->cp0_epc
;
887 regs
->cp0_epc
= old_epc
;
893 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
894 write_c0_debug(debug
| 0x100);
899 * NMI exception handler.
901 void nmi_exception_handler(struct pt_regs
*regs
)
903 printk("NMI taken!!!!\n");
908 unsigned long exception_handlers
[32];
911 * As a side effect of the way this is implemented we're limited
912 * to interrupt handlers in the address range from
913 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
915 void *set_except_vector(int n
, void *addr
)
917 unsigned long handler
= (unsigned long) addr
;
918 unsigned long old_handler
= exception_handlers
[n
];
920 exception_handlers
[n
] = handler
;
921 if (n
== 0 && cpu_has_divec
) {
922 *(volatile u32
*)(CAC_BASE
+ 0x200) = 0x08000000 |
923 (0x03ffffff & (handler
>> 2));
924 flush_icache_range(CAC_BASE
+ 0x200, CAC_BASE
+ 0x204);
926 return (void *)old_handler
;
930 * This is used by native signal handling
932 asmlinkage
int (*save_fp_context
)(struct sigcontext
*sc
);
933 asmlinkage
int (*restore_fp_context
)(struct sigcontext
*sc
);
935 extern asmlinkage
int _save_fp_context(struct sigcontext
*sc
);
936 extern asmlinkage
int _restore_fp_context(struct sigcontext
*sc
);
938 extern asmlinkage
int fpu_emulator_save_context(struct sigcontext
*sc
);
939 extern asmlinkage
int fpu_emulator_restore_context(struct sigcontext
*sc
);
941 static inline void signal_init(void)
944 save_fp_context
= _save_fp_context
;
945 restore_fp_context
= _restore_fp_context
;
947 save_fp_context
= fpu_emulator_save_context
;
948 restore_fp_context
= fpu_emulator_restore_context
;
952 #ifdef CONFIG_MIPS32_COMPAT
955 * This is used by 32-bit signal stuff on the 64-bit kernel
957 asmlinkage
int (*save_fp_context32
)(struct sigcontext32
*sc
);
958 asmlinkage
int (*restore_fp_context32
)(struct sigcontext32
*sc
);
960 extern asmlinkage
int _save_fp_context32(struct sigcontext32
*sc
);
961 extern asmlinkage
int _restore_fp_context32(struct sigcontext32
*sc
);
963 extern asmlinkage
int fpu_emulator_save_context32(struct sigcontext32
*sc
);
964 extern asmlinkage
int fpu_emulator_restore_context32(struct sigcontext32
*sc
);
966 static inline void signal32_init(void)
969 save_fp_context32
= _save_fp_context32
;
970 restore_fp_context32
= _restore_fp_context32
;
972 save_fp_context32
= fpu_emulator_save_context32
;
973 restore_fp_context32
= fpu_emulator_restore_context32
;
978 extern void cpu_cache_init(void);
979 extern void tlb_init(void);
981 void __init
per_cpu_trap_init(void)
983 unsigned int cpu
= smp_processor_id();
984 unsigned int status_set
= ST0_CU0
;
987 * Disable coprocessors and select 32-bit or 64-bit addressing
988 * and the 16/32 or 32/32 FPR register model. Reset the BEV
989 * flag that some firmware may have left set and the TS bit (for
990 * IP27). Set XX for ISA IV code to work.
993 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
995 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_IV
)
996 status_set
|= ST0_XX
;
997 change_c0_status(ST0_CU
|ST0_MX
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1001 set_c0_status(ST0_MX
);
1004 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1005 * interrupt processing overhead. Use it where available.
1008 set_c0_cause(CAUSEF_IV
);
1010 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1011 TLBMISS_HANDLER_SETUP();
1013 atomic_inc(&init_mm
.mm_count
);
1014 current
->active_mm
= &init_mm
;
1015 BUG_ON(current
->mm
);
1016 enter_lazy_tlb(&init_mm
, current
);
1022 void __init
trap_init(void)
1024 extern char except_vec3_generic
, except_vec3_r4000
;
1025 extern char except_vec_ejtag_debug
;
1026 extern char except_vec4
;
1029 per_cpu_trap_init();
1032 * Copy the generic exception handlers to their final destination.
1033 * This will be overriden later as suitable for a particular
1036 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
1039 * Setup default vectors
1041 for (i
= 0; i
<= 31; i
++)
1042 set_except_vector(i
, handle_reserved
);
1045 * Copy the EJTAG debug exception vector handler code to it's final
1049 memcpy((void *)(CAC_BASE
+ 0x300), &except_vec_ejtag_debug
, 0x80);
1052 * Only some CPUs have the watch exceptions.
1055 set_except_vector(23, handle_watch
);
1058 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1059 * interrupt processing overhead. Use it where available.
1062 memcpy((void *)(CAC_BASE
+ 0x200), &except_vec4
, 0x8);
1065 * Some CPUs can enable/disable for cache parity detection, but does
1066 * it different ways.
1068 parity_protection_init();
1071 * The Data Bus Errors / Instruction Bus Errors are signaled
1072 * by external hardware. Therefore these two exceptions
1073 * may have board specific handlers.
1078 set_except_vector(1, handle_tlbm
);
1079 set_except_vector(2, handle_tlbl
);
1080 set_except_vector(3, handle_tlbs
);
1082 set_except_vector(4, handle_adel
);
1083 set_except_vector(5, handle_ades
);
1085 set_except_vector(6, handle_ibe
);
1086 set_except_vector(7, handle_dbe
);
1088 set_except_vector(8, handle_sys
);
1089 set_except_vector(9, handle_bp
);
1090 set_except_vector(10, handle_ri
);
1091 set_except_vector(11, handle_cpu
);
1092 set_except_vector(12, handle_ov
);
1093 set_except_vector(13, handle_tr
);
1095 if (current_cpu_data
.cputype
== CPU_R6000
||
1096 current_cpu_data
.cputype
== CPU_R6000A
) {
1098 * The R6000 is the only R-series CPU that features a machine
1099 * check exception (similar to the R4000 cache error) and
1100 * unaligned ldc1/sdc1 exception. The handlers have not been
1101 * written yet. Well, anyway there is no R6000 machine on the
1102 * current list of targets for Linux/MIPS.
1103 * (Duh, crap, there is someone with a triple R6k machine)
1105 //set_except_vector(14, handle_mc);
1106 //set_except_vector(15, handle_ndc);
1109 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1110 set_except_vector(15, handle_fpe
);
1112 set_except_vector(22, handle_mdmx
);
1115 set_except_vector(24, handle_mcheck
);
1118 set_except_vector(26, handle_dsp
);
1121 /* Special exception: R4[04]00 uses also the divec space. */
1122 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_r4000
, 0x100);
1123 else if (cpu_has_4kex
)
1124 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
1126 memcpy((void *)(CAC_BASE
+ 0x080), &except_vec3_generic
, 0x80);
1129 #ifdef CONFIG_MIPS32_COMPAT
1133 flush_icache_range(CAC_BASE
, CAC_BASE
+ 0x400);