arch/mips/kvm/dyntrans.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/module.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/fs.h>
  18 #include <linux/bootmem.h>
  19 #include <asm/cacheflush.h>
  20
  21 #include "commpage.h"
  22
  23 /**
  24  * kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
  25  * @vcpu:       Virtual CPU.
  26  * @opc:        PC of instruction to replace.
  27  * @replace:    Instruction to write
  28  */
  29 static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc,
  30                                   union mips_instruction replace)
  31 {
  32         unsigned long kseg0_opc, flags;
  33
  34         if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
  35                 kseg0_opc =
  36                     CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
  37                                (vcpu, (unsigned long) opc));
  38                 memcpy((void *)kseg0_opc, (void *)&replace, sizeof(u32));
  39                 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
  40         } else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
  41                 local_irq_save(flags);
  42                 memcpy((void *)opc, (void *)&replace, sizeof(u32));
  43                 local_flush_icache_range((unsigned long)opc,
  44                                          (unsigned long)opc + 32);
  45                 local_irq_restore(flags);
  46         } else {
  47                 kvm_err("%s: Invalid address: %p\n", __func__, opc);
  48                 return -EFAULT;
  49         }
  50
  51         return 0;
  52 }
  53
  54 int kvm_mips_trans_cache_index(union mips_instruction inst, u32 *opc,
  55                                struct kvm_vcpu *vcpu)
  56 {
  57         union mips_instruction nop_inst = { 0 };
  58
  59         /* Replace the CACHE instruction, with a NOP */
  60         return kvm_mips_trans_replace(vcpu, opc, nop_inst);
  61 }
  62
  63 /*
  64  * Address based CACHE instructions are transformed into synci(s). A little
  65  * heavy for just D-cache invalidates, but avoids an expensive trap
  66  */
  67 int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
  68                             struct kvm_vcpu *vcpu)
  69 {
  70         union mips_instruction synci_inst = { 0 };
  71
  72         synci_inst.i_format.opcode = bcond_op;
  73         synci_inst.i_format.rs = inst.i_format.rs;
  74         synci_inst.i_format.rt = synci_op;
  75         synci_inst.i_format.simmediate = inst.i_format.simmediate;
  76
  77         return kvm_mips_trans_replace(vcpu, opc, synci_inst);
  78 }
  79
  80 int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
  81                         struct kvm_vcpu *vcpu)
  82 {
  83         union mips_instruction mfc0_inst = { 0 };
  84         u32 rd, sel;
  85
  86         rd = inst.c0r_format.rd;
  87         sel = inst.c0r_format.sel;
  88
  89         if (rd == MIPS_CP0_ERRCTL && sel == 0) {
  90                 mfc0_inst.r_format.opcode = spec_op;
  91                 mfc0_inst.r_format.rd = inst.c0r_format.rt;
  92                 mfc0_inst.r_format.func = add_op;
  93         } else {
  94                 mfc0_inst.i_format.opcode = lw_op;
  95                 mfc0_inst.i_format.rt = inst.c0r_format.rt;
  96                 mfc0_inst.i_format.simmediate =
  97                         offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
  98         }
  99
 100         return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
 101 }
 102
 103 int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
 104                         struct kvm_vcpu *vcpu)
 105 {
 106         union mips_instruction mtc0_inst = { 0 };
 107         u32 rd, sel;
 108
 109         rd = inst.c0r_format.rd;
 110         sel = inst.c0r_format.sel;
 111
 112         mtc0_inst.i_format.opcode = sw_op;
 113         mtc0_inst.i_format.rt = inst.c0r_format.rt;
 114         mtc0_inst.i_format.simmediate =
 115                 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
 116
 117         return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
 118 }