2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kvm_host.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
18 #include <linux/bootmem.h>
19 #include <asm/cacheflush.h>
24 * kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
26 * @opc: PC of instruction to replace.
27 * @replace: Instruction to write
29 static int kvm_mips_trans_replace(struct kvm_vcpu
*vcpu
, u32
*opc
,
30 union mips_instruction replace
)
32 unsigned long kseg0_opc
, flags
;
34 if (KVM_GUEST_KSEGX(opc
) == KVM_GUEST_KSEG0
) {
36 CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
37 (vcpu
, (unsigned long) opc
));
38 memcpy((void *)kseg0_opc
, (void *)&replace
, sizeof(u32
));
39 local_flush_icache_range(kseg0_opc
, kseg0_opc
+ 32);
40 } else if (KVM_GUEST_KSEGX((unsigned long) opc
) == KVM_GUEST_KSEG23
) {
41 local_irq_save(flags
);
42 memcpy((void *)opc
, (void *)&replace
, sizeof(u32
));
43 local_flush_icache_range((unsigned long)opc
,
44 (unsigned long)opc
+ 32);
45 local_irq_restore(flags
);
47 kvm_err("%s: Invalid address: %p\n", __func__
, opc
);
54 int kvm_mips_trans_cache_index(union mips_instruction inst
, u32
*opc
,
55 struct kvm_vcpu
*vcpu
)
57 union mips_instruction nop_inst
= { 0 };
59 /* Replace the CACHE instruction, with a NOP */
60 return kvm_mips_trans_replace(vcpu
, opc
, nop_inst
);
64 * Address based CACHE instructions are transformed into synci(s). A little
65 * heavy for just D-cache invalidates, but avoids an expensive trap
67 int kvm_mips_trans_cache_va(union mips_instruction inst
, u32
*opc
,
68 struct kvm_vcpu
*vcpu
)
70 union mips_instruction synci_inst
= { 0 };
72 synci_inst
.i_format
.opcode
= bcond_op
;
73 synci_inst
.i_format
.rs
= inst
.i_format
.rs
;
74 synci_inst
.i_format
.rt
= synci_op
;
76 synci_inst
.i_format
.simmediate
= inst
.spec3_format
.simmediate
;
78 synci_inst
.i_format
.simmediate
= inst
.i_format
.simmediate
;
80 return kvm_mips_trans_replace(vcpu
, opc
, synci_inst
);
83 int kvm_mips_trans_mfc0(union mips_instruction inst
, u32
*opc
,
84 struct kvm_vcpu
*vcpu
)
86 union mips_instruction mfc0_inst
= { 0 };
89 rd
= inst
.c0r_format
.rd
;
90 sel
= inst
.c0r_format
.sel
;
92 if (rd
== MIPS_CP0_ERRCTL
&& sel
== 0) {
93 mfc0_inst
.r_format
.opcode
= spec_op
;
94 mfc0_inst
.r_format
.rd
= inst
.c0r_format
.rt
;
95 mfc0_inst
.r_format
.func
= add_op
;
97 mfc0_inst
.i_format
.opcode
= lw_op
;
98 mfc0_inst
.i_format
.rt
= inst
.c0r_format
.rt
;
99 mfc0_inst
.i_format
.simmediate
= KVM_GUEST_COMMPAGE_ADDR
|
100 offsetof(struct kvm_mips_commpage
, cop0
.reg
[rd
][sel
]);
103 return kvm_mips_trans_replace(vcpu
, opc
, mfc0_inst
);
106 int kvm_mips_trans_mtc0(union mips_instruction inst
, u32
*opc
,
107 struct kvm_vcpu
*vcpu
)
109 union mips_instruction mtc0_inst
= { 0 };
112 rd
= inst
.c0r_format
.rd
;
113 sel
= inst
.c0r_format
.sel
;
115 mtc0_inst
.i_format
.opcode
= sw_op
;
116 mtc0_inst
.i_format
.rt
= inst
.c0r_format
.rt
;
117 mtc0_inst
.i_format
.simmediate
= KVM_GUEST_COMMPAGE_ADDR
|
118 offsetof(struct kvm_mips_commpage
, cop0
.reg
[rd
][sel
]);
120 return kvm_mips_trans_replace(vcpu
, opc
, mtc0_inst
);