arch/mips/kvm/dyntrans.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/module.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/fs.h>
  18 #include <linux/bootmem.h>
  19 #include <asm/cacheflush.h>
  20
  21 #include "commpage.h"
  22
  23 #define SYNCI_TEMPLATE  0x041f0000
  24 #define SYNCI_BASE(x)   (((x) >> 21) & 0x1f)
  25 #define SYNCI_OFFSET    ((x) & 0xffff)
  26
  27 #define LW_TEMPLATE     0x8c000000
  28 #define CLEAR_TEMPLATE  0x00000020
  29 #define SW_TEMPLATE     0xac000000
  30
  31 /**
  32  * kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
  33  * @vcpu:       Virtual CPU.
  34  * @opc:        PC of instruction to replace.
  35  * @replace:    Instruction to write
  36  */
  37 static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc, u32 replace)
  38 {
  39         unsigned long kseg0_opc, flags;
  40
  41         if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
  42                 kseg0_opc =
  43                     CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
  44                                (vcpu, (unsigned long) opc));
  45                 memcpy((void *)kseg0_opc, (void *)&replace, sizeof(u32));
  46                 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
  47         } else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
  48                 local_irq_save(flags);
  49                 memcpy((void *)opc, (void *)&replace, sizeof(u32));
  50                 local_flush_icache_range((unsigned long)opc,
  51                                          (unsigned long)opc + 32);
  52                 local_irq_restore(flags);
  53         } else {
  54                 kvm_err("%s: Invalid address: %p\n", __func__, opc);
  55                 return -EFAULT;
  56         }
  57
  58         return 0;
  59 }
  60
  61 int kvm_mips_trans_cache_index(u32 inst, u32 *opc,
  62                                struct kvm_vcpu *vcpu)
  63 {
  64         /* Replace the CACHE instruction, with a NOP */
  65         return kvm_mips_trans_replace(vcpu, opc, 0x00000000);
  66 }
  67
  68 /*
  69  * Address based CACHE instructions are transformed into synci(s). A little
  70  * heavy for just D-cache invalidates, but avoids an expensive trap
  71  */
  72 int kvm_mips_trans_cache_va(u32 inst, u32 *opc,
  73                             struct kvm_vcpu *vcpu)
  74 {
  75         u32 synci_inst = SYNCI_TEMPLATE, base, offset;
  76
  77         base = (inst >> 21) & 0x1f;
  78         offset = inst & 0xffff;
  79         synci_inst |= (base << 21);
  80         synci_inst |= offset;
  81
  82         return kvm_mips_trans_replace(vcpu, opc, synci_inst);
  83 }
  84
  85 int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu)
  86 {
  87         u32 rt, rd, sel;
  88         u32 mfc0_inst;
  89
  90         rt = (inst >> 16) & 0x1f;
  91         rd = (inst >> 11) & 0x1f;
  92         sel = inst & 0x7;
  93
  94         if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
  95                 mfc0_inst = CLEAR_TEMPLATE;
  96                 mfc0_inst |= ((rt & 0x1f) << 11);
  97         } else {
  98                 mfc0_inst = LW_TEMPLATE;
  99                 mfc0_inst |= ((rt & 0x1f) << 16);
 100                 mfc0_inst |= offsetof(struct kvm_mips_commpage,
 101                                       cop0.reg[rd][sel]);
 102         }
 103
 104         return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
 105 }
 106
 107 int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu)
 108 {
 109         u32 rt, rd, sel;
 110         u32 mtc0_inst = SW_TEMPLATE;
 111
 112         rt = (inst >> 16) & 0x1f;
 113         rd = (inst >> 11) & 0x1f;
 114         sel = inst & 0x7;
 115
 116         mtc0_inst |= ((rt & 0x1f) << 16);
 117         mtc0_inst |= offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
 118
 119         return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
 120 }