arch/mips/kvm/dyntrans.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/highmem.h>
  15 #include <linux/kvm_host.h>
  16 #include <linux/module.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/fs.h>
  19 #include <linux/bootmem.h>
  20 #include <asm/cacheflush.h>
  21
  22 #include "commpage.h"
  23
  24 /**
  25  * kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
  26  * @vcpu:       Virtual CPU.
  27  * @opc:        PC of instruction to replace.
  28  * @replace:    Instruction to write
  29  */
  30 static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc,
  31                                   union mips_instruction replace)
  32 {
  33         unsigned long paddr, flags;
  34         void *vaddr;
  35
  36         if (KVM_GUEST_KSEGX((unsigned long)opc) == KVM_GUEST_KSEG0) {
  37                 paddr = kvm_mips_translate_guest_kseg0_to_hpa(vcpu,
  38                                                             (unsigned long)opc);
  39                 vaddr = kmap_atomic(pfn_to_page(PHYS_PFN(paddr)));
  40                 vaddr += paddr & ~PAGE_MASK;
  41                 memcpy(vaddr, (void *)&replace, sizeof(u32));
  42                 local_flush_icache_range((unsigned long)vaddr,
  43                                          (unsigned long)vaddr + 32);
  44                 kunmap_atomic(vaddr);
  45         } else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
  46                 local_irq_save(flags);
  47                 memcpy((void *)opc, (void *)&replace, sizeof(u32));
  48                 local_flush_icache_range((unsigned long)opc,
  49                                          (unsigned long)opc + 32);
  50                 local_irq_restore(flags);
  51         } else {
  52                 kvm_err("%s: Invalid address: %p\n", __func__, opc);
  53                 return -EFAULT;
  54         }
  55
  56         return 0;
  57 }
  58
  59 int kvm_mips_trans_cache_index(union mips_instruction inst, u32 *opc,
  60                                struct kvm_vcpu *vcpu)
  61 {
  62         union mips_instruction nop_inst = { 0 };
  63
  64         /* Replace the CACHE instruction, with a NOP */
  65         return kvm_mips_trans_replace(vcpu, opc, nop_inst);
  66 }
  67
  68 /*
  69  * Address based CACHE instructions are transformed into synci(s). A little
  70  * heavy for just D-cache invalidates, but avoids an expensive trap
  71  */
  72 int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
  73                             struct kvm_vcpu *vcpu)
  74 {
  75         union mips_instruction synci_inst = { 0 };
  76
  77         synci_inst.i_format.opcode = bcond_op;
  78         synci_inst.i_format.rs = inst.i_format.rs;
  79         synci_inst.i_format.rt = synci_op;
  80         if (cpu_has_mips_r6)
  81                 synci_inst.i_format.simmediate = inst.spec3_format.simmediate;
  82         else
  83                 synci_inst.i_format.simmediate = inst.i_format.simmediate;
  84
  85         return kvm_mips_trans_replace(vcpu, opc, synci_inst);
  86 }
  87
  88 int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
  89                         struct kvm_vcpu *vcpu)
  90 {
  91         union mips_instruction mfc0_inst = { 0 };
  92         u32 rd, sel;
  93
  94         rd = inst.c0r_format.rd;
  95         sel = inst.c0r_format.sel;
  96
  97         if (rd == MIPS_CP0_ERRCTL && sel == 0) {
  98                 mfc0_inst.r_format.opcode = spec_op;
  99                 mfc0_inst.r_format.rd = inst.c0r_format.rt;
 100                 mfc0_inst.r_format.func = add_op;
 101         } else {
 102                 mfc0_inst.i_format.opcode = lw_op;
 103                 mfc0_inst.i_format.rt = inst.c0r_format.rt;
 104                 mfc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
 105                         offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
 106 #ifdef CONFIG_CPU_BIG_ENDIAN
 107                 if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
 108                         mfc0_inst.i_format.simmediate |= 4;
 109 #endif
 110         }
 111
 112         return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
 113 }
 114
 115 int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
 116                         struct kvm_vcpu *vcpu)
 117 {
 118         union mips_instruction mtc0_inst = { 0 };
 119         u32 rd, sel;
 120
 121         rd = inst.c0r_format.rd;
 122         sel = inst.c0r_format.sel;
 123
 124         mtc0_inst.i_format.opcode = sw_op;
 125         mtc0_inst.i_format.rt = inst.c0r_format.rt;
 126         mtc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
 127                 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
 128 #ifdef CONFIG_CPU_BIG_ENDIAN
 129         if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
 130                 mtc0_inst.i_format.simmediate |= 4;
 131 #endif
 132
 133         return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
 134 }