2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Generation of main entry point for the guest, exception handling.
8 * Copyright (C) 2012 MIPS Technologies, Inc.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
11 * Copyright (C) 2016 Imagination Technologies Ltd.
14 #include <linux/kvm_host.h>
16 #include <asm/setup.h>
27 #if _MIPS_SIM == _MIPS_SIM_ABI32
32 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
34 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
39 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
50 /* Some CP0 registers */
51 #define C0_HWRENA 7, 0
52 #define C0_BADVADDR 8, 0
53 #define C0_ENTRYHI 10, 0
54 #define C0_STATUS 12, 0
55 #define C0_CAUSE 13, 0
57 #define C0_EBASE 15, 1
58 #define C0_CONFIG5 16, 5
59 #define C0_DDATA_LO 28, 3
60 #define C0_ERROREPC 30, 0
62 #define CALLFRAME_SIZ 32
64 static unsigned int scratch_vcpu
[2] = { C0_DDATA_LO
};
65 static unsigned int scratch_tmp
[2] = { C0_ERROREPC
};
77 UASM_L_LA(_return_to_host
)
78 UASM_L_LA(_kernel_asid
)
79 UASM_L_LA(_exit_common
)
81 static void *kvm_mips_build_enter_guest(void *addr
);
82 static void *kvm_mips_build_ret_from_exit(void *addr
);
83 static void *kvm_mips_build_ret_to_guest(void *addr
);
84 static void *kvm_mips_build_ret_to_host(void *addr
);
87 * kvm_mips_entry_setup() - Perform global setup for entry code.
89 * Perform global setup for entry code, such as choosing a scratch register.
91 * Returns: 0 on success.
94 int kvm_mips_entry_setup(void)
97 * We prefer to use KScratchN registers if they are available over the
98 * defaults above, which may not work on all cores.
100 unsigned int kscratch_mask
= cpu_data
[0].kscratch_mask
& 0xfc;
102 /* Pick a scratch register for storing VCPU */
104 scratch_vcpu
[0] = 31;
105 scratch_vcpu
[1] = ffs(kscratch_mask
) - 1;
106 kscratch_mask
&= ~BIT(scratch_vcpu
[1]);
109 /* Pick a scratch register to use as a temp for saving state */
112 scratch_tmp
[1] = ffs(kscratch_mask
) - 1;
113 kscratch_mask
&= ~BIT(scratch_tmp
[1]);
119 static void kvm_mips_build_save_scratch(u32
**p
, unsigned int tmp
,
122 /* Save the VCPU scratch register value in cp0_epc of the stack frame */
123 uasm_i_mfc0(p
, tmp
, scratch_vcpu
[0], scratch_vcpu
[1]);
124 UASM_i_SW(p
, tmp
, offsetof(struct pt_regs
, cp0_epc
), frame
);
126 /* Save the temp scratch register value in cp0_cause of stack frame */
127 if (scratch_tmp
[0] == 31) {
128 uasm_i_mfc0(p
, tmp
, scratch_tmp
[0], scratch_tmp
[1]);
129 UASM_i_SW(p
, tmp
, offsetof(struct pt_regs
, cp0_cause
), frame
);
133 static void kvm_mips_build_restore_scratch(u32
**p
, unsigned int tmp
,
137 * Restore host scratch register values saved by
138 * kvm_mips_build_save_scratch().
140 UASM_i_LW(p
, tmp
, offsetof(struct pt_regs
, cp0_epc
), frame
);
141 uasm_i_mtc0(p
, tmp
, scratch_vcpu
[0], scratch_vcpu
[1]);
143 if (scratch_tmp
[0] == 31) {
144 UASM_i_LW(p
, tmp
, offsetof(struct pt_regs
, cp0_cause
), frame
);
145 uasm_i_mtc0(p
, tmp
, scratch_tmp
[0], scratch_tmp
[1]);
150 * kvm_mips_build_vcpu_run() - Assemble function to start running a guest VCPU.
151 * @addr: Address to start writing code.
153 * Assemble the start of the vcpu_run function to run a guest VCPU. The function
154 * conforms to the following prototype:
156 * int vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
158 * The exit from the guest and return to the caller is handled by the code
159 * generated by kvm_mips_build_ret_to_host().
161 * Returns: Next address after end of written function.
163 void *kvm_mips_build_vcpu_run(void *addr
)
173 /* k0/k1 not being used in host kernel context */
174 uasm_i_addiu(&p
, K1
, SP
, -(int)sizeof(struct pt_regs
));
175 for (i
= 16; i
< 32; ++i
) {
178 UASM_i_SW(&p
, i
, offsetof(struct pt_regs
, regs
[i
]), K1
);
181 /* Save host status */
182 uasm_i_mfc0(&p
, V0
, C0_STATUS
);
183 UASM_i_SW(&p
, V0
, offsetof(struct pt_regs
, cp0_status
), K1
);
185 /* Save scratch registers, will be used to store pointer to vcpu etc */
186 kvm_mips_build_save_scratch(&p
, V1
, K1
);
188 /* VCPU scratch register has pointer to vcpu */
189 uasm_i_mtc0(&p
, A1
, scratch_vcpu
[0], scratch_vcpu
[1]);
191 /* Offset into vcpu->arch */
192 uasm_i_addiu(&p
, K1
, A1
, offsetof(struct kvm_vcpu
, arch
));
195 * Save the host stack to VCPU, used for exception processing
196 * when we exit from the Guest
198 UASM_i_SW(&p
, SP
, offsetof(struct kvm_vcpu_arch
, host_stack
), K1
);
200 /* Save the kernel gp as well */
201 UASM_i_SW(&p
, GP
, offsetof(struct kvm_vcpu_arch
, host_gp
), K1
);
204 * Setup status register for running the guest in UM, interrupts
207 UASM_i_LA(&p
, K0
, ST0_EXL
| KSU_USER
| ST0_BEV
);
208 uasm_i_mtc0(&p
, K0
, C0_STATUS
);
211 /* load up the new EBASE */
212 UASM_i_LW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, guest_ebase
), K1
);
213 uasm_i_mtc0(&p
, K0
, C0_EBASE
);
216 * Now that the new EBASE has been loaded, unset BEV, set
217 * interrupt mask as it was but make sure that timer interrupts
220 uasm_i_addiu(&p
, K0
, ZERO
, ST0_EXL
| KSU_USER
| ST0_IE
);
221 uasm_i_andi(&p
, V0
, V0
, ST0_IM
);
222 uasm_i_or(&p
, K0
, K0
, V0
);
223 uasm_i_mtc0(&p
, K0
, C0_STATUS
);
226 p
= kvm_mips_build_enter_guest(p
);
232 * kvm_mips_build_enter_guest() - Assemble code to resume guest execution.
233 * @addr: Address to start writing code.
235 * Assemble the code to resume guest execution. This code is common between the
236 * initial entry into the guest from the host, and returning from the exit
237 * handler back to the guest.
239 * Returns: Next address after end of written function.
241 static void *kvm_mips_build_enter_guest(void *addr
)
245 struct uasm_label labels
[2];
246 struct uasm_reloc relocs
[2];
247 struct uasm_label
*l
= labels
;
248 struct uasm_reloc
*r
= relocs
;
250 memset(labels
, 0, sizeof(labels
));
251 memset(relocs
, 0, sizeof(relocs
));
254 UASM_i_LW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, pc
), K1
);
255 uasm_i_mtc0(&p
, T0
, C0_EPC
);
257 /* Set the ASID for the Guest Kernel */
258 UASM_i_LW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, cop0
), K1
);
259 UASM_i_LW(&p
, T0
, offsetof(struct mips_coproc
, reg
[MIPS_CP0_STATUS
][0]),
261 uasm_i_andi(&p
, T0
, T0
, KSU_USER
| ST0_ERL
| ST0_EXL
);
262 uasm_i_xori(&p
, T0
, T0
, KSU_USER
);
263 uasm_il_bnez(&p
, &r
, T0
, label_kernel_asid
);
264 uasm_i_addiu(&p
, T1
, K1
,
265 offsetof(struct kvm_vcpu_arch
, guest_kernel_asid
));
267 uasm_i_addiu(&p
, T1
, K1
,
268 offsetof(struct kvm_vcpu_arch
, guest_user_asid
));
269 uasm_l_kernel_asid(&l
, p
);
271 /* t1: contains the base of the ASID array, need to get the cpu id */
272 /* smp_processor_id */
273 UASM_i_LW(&p
, T2
, offsetof(struct thread_info
, cpu
), GP
);
275 uasm_i_sll(&p
, T2
, T2
, 2);
276 UASM_i_ADDU(&p
, T3
, T1
, T2
);
277 UASM_i_LW(&p
, K0
, 0, T3
);
278 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
279 /* x sizeof(struct cpuinfo_mips)/4 */
280 uasm_i_addiu(&p
, T3
, ZERO
, sizeof(struct cpuinfo_mips
)/4);
281 uasm_i_mul(&p
, T2
, T2
, T3
);
283 UASM_i_LA_mostly(&p
, AT
, (long)&cpu_data
[0].asid_mask
);
284 UASM_i_ADDU(&p
, AT
, AT
, T2
);
285 UASM_i_LW(&p
, T2
, uasm_rel_lo((long)&cpu_data
[0].asid_mask
), AT
);
286 uasm_i_and(&p
, K0
, K0
, T2
);
288 uasm_i_andi(&p
, K0
, K0
, MIPS_ENTRYHI_ASID
);
290 uasm_i_mtc0(&p
, K0
, C0_ENTRYHI
);
293 /* Disable RDHWR access */
294 uasm_i_mtc0(&p
, ZERO
, C0_HWRENA
);
296 /* load the guest context from VCPU and return */
297 for (i
= 1; i
< 32; ++i
) {
298 /* Guest k0/k1 loaded later */
299 if (i
== K0
|| i
== K1
)
301 UASM_i_LW(&p
, i
, offsetof(struct kvm_vcpu_arch
, gprs
[i
]), K1
);
304 #ifndef CONFIG_CPU_MIPSR6
306 UASM_i_LW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, hi
), K1
);
309 UASM_i_LW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, lo
), K1
);
313 /* Restore the guest's k0/k1 registers */
314 UASM_i_LW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, gprs
[K0
]), K1
);
315 UASM_i_LW(&p
, K1
, offsetof(struct kvm_vcpu_arch
, gprs
[K1
]), K1
);
320 uasm_resolve_relocs(relocs
, labels
);
326 * kvm_mips_build_exception() - Assemble first level guest exception handler.
327 * @addr: Address to start writing code.
328 * @handler: Address of common handler (within range of @addr).
330 * Assemble exception vector code for guest execution. The generated vector will
331 * branch to the common exception handler generated by kvm_mips_build_exit().
333 * Returns: Next address after end of written function.
335 void *kvm_mips_build_exception(void *addr
, void *handler
)
338 struct uasm_label labels
[2];
339 struct uasm_reloc relocs
[2];
340 struct uasm_label
*l
= labels
;
341 struct uasm_reloc
*r
= relocs
;
343 memset(labels
, 0, sizeof(labels
));
344 memset(relocs
, 0, sizeof(relocs
));
346 /* Save guest k1 into scratch register */
347 uasm_i_mtc0(&p
, K1
, scratch_tmp
[0], scratch_tmp
[1]);
349 /* Get the VCPU pointer from the VCPU scratch register */
350 uasm_i_mfc0(&p
, K1
, scratch_vcpu
[0], scratch_vcpu
[1]);
351 uasm_i_addiu(&p
, K1
, K1
, offsetof(struct kvm_vcpu
, arch
));
353 /* Save guest k0 into VCPU structure */
354 UASM_i_SW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, gprs
[K0
]), K1
);
356 /* Branch to the common handler */
357 uasm_il_b(&p
, &r
, label_exit_common
);
360 uasm_l_exit_common(&l
, handler
);
361 uasm_resolve_relocs(relocs
, labels
);
367 * kvm_mips_build_exit() - Assemble common guest exit handler.
368 * @addr: Address to start writing code.
370 * Assemble the generic guest exit handling code. This is called by the
371 * exception vectors (generated by kvm_mips_build_exception()), and calls
372 * kvm_mips_handle_exit(), then either resumes the guest or returns to the host
373 * depending on the return value.
375 * Returns: Next address after end of written function.
377 void *kvm_mips_build_exit(void *addr
)
381 struct uasm_label labels
[3];
382 struct uasm_reloc relocs
[3];
383 struct uasm_label
*l
= labels
;
384 struct uasm_reloc
*r
= relocs
;
386 memset(labels
, 0, sizeof(labels
));
387 memset(relocs
, 0, sizeof(relocs
));
390 * Generic Guest exception handler. We end up here when the guest
391 * does something that causes a trap to kernel mode.
393 * Both k0/k1 registers will have already been saved (k0 into the vcpu
394 * structure, and k1 into the scratch_tmp register).
396 * The k1 register will already contain the kvm_vcpu_arch pointer.
399 /* Start saving Guest context to VCPU */
400 for (i
= 0; i
< 32; ++i
) {
401 /* Guest k0/k1 saved later */
402 if (i
== K0
|| i
== K1
)
404 UASM_i_SW(&p
, i
, offsetof(struct kvm_vcpu_arch
, gprs
[i
]), K1
);
407 #ifndef CONFIG_CPU_MIPSR6
408 /* We need to save hi/lo and restore them on the way out */
410 UASM_i_SW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, hi
), K1
);
413 UASM_i_SW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, lo
), K1
);
416 /* Finally save guest k1 to VCPU */
418 uasm_i_mfc0(&p
, T0
, scratch_tmp
[0], scratch_tmp
[1]);
419 UASM_i_SW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, gprs
[K1
]), K1
);
421 /* Now that context has been saved, we can use other registers */
424 uasm_i_mfc0(&p
, A1
, scratch_vcpu
[0], scratch_vcpu
[1]);
425 uasm_i_move(&p
, S1
, A1
);
427 /* Restore run (vcpu->run) */
428 UASM_i_LW(&p
, A0
, offsetof(struct kvm_vcpu
, run
), A1
);
429 /* Save pointer to run in s0, will be saved by the compiler */
430 uasm_i_move(&p
, S0
, A0
);
433 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to process
436 uasm_i_mfc0(&p
, K0
, C0_EPC
);
437 UASM_i_SW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, pc
), K1
);
439 uasm_i_mfc0(&p
, K0
, C0_BADVADDR
);
440 UASM_i_SW(&p
, K0
, offsetof(struct kvm_vcpu_arch
, host_cp0_badvaddr
),
443 uasm_i_mfc0(&p
, K0
, C0_CAUSE
);
444 uasm_i_sw(&p
, K0
, offsetof(struct kvm_vcpu_arch
, host_cp0_cause
), K1
);
446 /* Now restore the host state just enough to run the handlers */
448 /* Switch EBASE to the one used by Linux */
449 /* load up the host EBASE */
450 uasm_i_mfc0(&p
, V0
, C0_STATUS
);
452 uasm_i_lui(&p
, AT
, ST0_BEV
>> 16);
453 uasm_i_or(&p
, K0
, V0
, AT
);
455 uasm_i_mtc0(&p
, K0
, C0_STATUS
);
458 UASM_i_LA_mostly(&p
, K0
, (long)&ebase
);
459 UASM_i_LW(&p
, K0
, uasm_rel_lo((long)&ebase
), K0
);
460 uasm_i_mtc0(&p
, K0
, C0_EBASE
);
462 if (raw_cpu_has_fpu
) {
464 * If FPU is enabled, save FCR31 and clear it so that later
465 * ctc1's don't trigger FPE for pending exceptions.
467 uasm_i_lui(&p
, AT
, ST0_CU1
>> 16);
468 uasm_i_and(&p
, V1
, V0
, AT
);
469 uasm_il_beqz(&p
, &r
, V1
, label_fpu_1
);
471 uasm_i_cfc1(&p
, T0
, 31);
472 uasm_i_sw(&p
, T0
, offsetof(struct kvm_vcpu_arch
, fpu
.fcr31
),
474 uasm_i_ctc1(&p
, ZERO
, 31);
480 * If MSA is enabled, save MSACSR and clear it so that later
481 * instructions don't trigger MSAFPE for pending exceptions.
483 uasm_i_mfc0(&p
, T0
, C0_CONFIG5
);
484 uasm_i_ext(&p
, T0
, T0
, 27, 1); /* MIPS_CONF5_MSAEN */
485 uasm_il_beqz(&p
, &r
, T0
, label_msa_1
);
487 uasm_i_cfcmsa(&p
, T0
, MSA_CSR
);
488 uasm_i_sw(&p
, T0
, offsetof(struct kvm_vcpu_arch
, fpu
.msacsr
),
490 uasm_i_ctcmsa(&p
, MSA_CSR
, ZERO
);
494 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
495 uasm_i_addiu(&p
, AT
, ZERO
, ~(ST0_EXL
| KSU_USER
| ST0_IE
));
496 uasm_i_and(&p
, V0
, V0
, AT
);
497 uasm_i_lui(&p
, AT
, ST0_CU0
>> 16);
498 uasm_i_or(&p
, V0
, V0
, AT
);
499 uasm_i_mtc0(&p
, V0
, C0_STATUS
);
502 /* Load up host GP */
503 UASM_i_LW(&p
, GP
, offsetof(struct kvm_vcpu_arch
, host_gp
), K1
);
505 /* Need a stack before we can jump to "C" */
506 UASM_i_LW(&p
, SP
, offsetof(struct kvm_vcpu_arch
, host_stack
), K1
);
508 /* Saved host state */
509 uasm_i_addiu(&p
, SP
, SP
, -(int)sizeof(struct pt_regs
));
512 * XXXKYMA do we need to load the host ASID, maybe not because the
513 * kernel entries are marked GLOBAL, need to verify
516 /* Restore host scratch registers, as we'll have clobbered them */
517 kvm_mips_build_restore_scratch(&p
, K0
, SP
);
519 /* Restore RDHWR access */
520 UASM_i_LA_mostly(&p
, K0
, (long)&hwrena
);
521 uasm_i_lw(&p
, K0
, uasm_rel_lo((long)&hwrena
), K0
);
522 uasm_i_mtc0(&p
, K0
, C0_HWRENA
);
524 /* Jump to handler */
526 * XXXKYMA: not sure if this is safe, how large is the stack??
527 * Now jump to the kvm_mips_handle_exit() to see if we can deal
528 * with this in the kernel
530 UASM_i_LA(&p
, T9
, (unsigned long)kvm_mips_handle_exit
);
531 uasm_i_jalr(&p
, RA
, T9
);
532 uasm_i_addiu(&p
, SP
, SP
, -CALLFRAME_SIZ
);
534 uasm_resolve_relocs(relocs
, labels
);
536 p
= kvm_mips_build_ret_from_exit(p
);
542 * kvm_mips_build_ret_from_exit() - Assemble guest exit return handler.
543 * @addr: Address to start writing code.
545 * Assemble the code to handle the return from kvm_mips_handle_exit(), either
546 * resuming the guest or returning to the host depending on the return value.
548 * Returns: Next address after end of written function.
550 static void *kvm_mips_build_ret_from_exit(void *addr
)
553 struct uasm_label labels
[2];
554 struct uasm_reloc relocs
[2];
555 struct uasm_label
*l
= labels
;
556 struct uasm_reloc
*r
= relocs
;
558 memset(labels
, 0, sizeof(labels
));
559 memset(relocs
, 0, sizeof(relocs
));
561 /* Return from handler Make sure interrupts are disabled */
566 * XXXKYMA: k0/k1 could have been blown away if we processed
567 * an exception while we were handling the exception from the
571 uasm_i_move(&p
, K1
, S1
);
572 uasm_i_addiu(&p
, K1
, K1
, offsetof(struct kvm_vcpu
, arch
));
575 * Check return value, should tell us if we are returning to the
576 * host (handle I/O etc)or resuming the guest
578 uasm_i_andi(&p
, T0
, V0
, RESUME_HOST
);
579 uasm_il_bnez(&p
, &r
, T0
, label_return_to_host
);
582 p
= kvm_mips_build_ret_to_guest(p
);
584 uasm_l_return_to_host(&l
, p
);
585 p
= kvm_mips_build_ret_to_host(p
);
587 uasm_resolve_relocs(relocs
, labels
);
593 * kvm_mips_build_ret_to_guest() - Assemble code to return to the guest.
594 * @addr: Address to start writing code.
596 * Assemble the code to handle return from the guest exit handler
597 * (kvm_mips_handle_exit()) back to the guest.
599 * Returns: Next address after end of written function.
601 static void *kvm_mips_build_ret_to_guest(void *addr
)
605 /* Put the saved pointer to vcpu (s1) back into the scratch register */
606 uasm_i_mtc0(&p
, S1
, scratch_vcpu
[0], scratch_vcpu
[1]);
608 /* Load up the Guest EBASE to minimize the window where BEV is set */
609 UASM_i_LW(&p
, T0
, offsetof(struct kvm_vcpu_arch
, guest_ebase
), K1
);
611 /* Switch EBASE back to the one used by KVM */
612 uasm_i_mfc0(&p
, V1
, C0_STATUS
);
613 uasm_i_lui(&p
, AT
, ST0_BEV
>> 16);
614 uasm_i_or(&p
, K0
, V1
, AT
);
615 uasm_i_mtc0(&p
, K0
, C0_STATUS
);
617 uasm_i_mtc0(&p
, T0
, C0_EBASE
);
619 /* Setup status register for running guest in UM */
620 uasm_i_ori(&p
, V1
, V1
, ST0_EXL
| KSU_USER
| ST0_IE
);
621 UASM_i_LA(&p
, AT
, ~(ST0_CU0
| ST0_MX
));
622 uasm_i_and(&p
, V1
, V1
, AT
);
623 uasm_i_mtc0(&p
, V1
, C0_STATUS
);
626 p
= kvm_mips_build_enter_guest(p
);
632 * kvm_mips_build_ret_to_host() - Assemble code to return to the host.
633 * @addr: Address to start writing code.
635 * Assemble the code to handle return from the guest exit handler
636 * (kvm_mips_handle_exit()) back to the host, i.e. to the caller of the vcpu_run
637 * function generated by kvm_mips_build_vcpu_run().
639 * Returns: Next address after end of written function.
641 static void *kvm_mips_build_ret_to_host(void *addr
)
646 /* EBASE is already pointing to Linux */
647 UASM_i_LW(&p
, K1
, offsetof(struct kvm_vcpu_arch
, host_stack
), K1
);
648 uasm_i_addiu(&p
, K1
, K1
, -(int)sizeof(struct pt_regs
));
651 * r2/v0 is the return code, shift it down by 2 (arithmetic)
652 * to recover the err code
654 uasm_i_sra(&p
, K0
, V0
, 2);
655 uasm_i_move(&p
, V0
, K0
);
657 /* Load context saved on the host stack */
658 for (i
= 16; i
< 31; ++i
) {
661 UASM_i_LW(&p
, i
, offsetof(struct pt_regs
, regs
[i
]), K1
);
664 /* Restore RDHWR access */
665 UASM_i_LA_mostly(&p
, K0
, (long)&hwrena
);
666 uasm_i_lw(&p
, K0
, uasm_rel_lo((long)&hwrena
), K0
);
667 uasm_i_mtc0(&p
, K0
, C0_HWRENA
);
669 /* Restore RA, which is the address we will return to */
670 UASM_i_LW(&p
, RA
, offsetof(struct pt_regs
, regs
[RA
]), K1
);
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