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MIPS: KVM: Dynamically choose scratch registers
[deliverable/linux.git] / arch / mips / kvm / mips.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <asm/fpu.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25
26 #include <linux/kvm_host.h>
27
28 #include "interrupt.h"
29 #include "commpage.h"
30
31 #define CREATE_TRACE_POINTS
32 #include "trace.h"
33
34 #ifndef VECTORSPACING
35 #define VECTORSPACING 0x100 /* for EI/VI mode */
36 #endif
37
38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
39 struct kvm_stats_debugfs_item debugfs_entries[] = {
40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
62 {NULL}
63 };
64
65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
66 {
67 int i;
68
69 for_each_possible_cpu(i) {
70 vcpu->arch.guest_kernel_asid[i] = 0;
71 vcpu->arch.guest_user_asid[i] = 0;
72 }
73
74 return 0;
75 }
76
77 /*
78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
79 * Config7, so we are "runnable" if interrupts are pending
80 */
81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
82 {
83 return !!(vcpu->arch.pending_exceptions);
84 }
85
86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
87 {
88 return 1;
89 }
90
91 int kvm_arch_hardware_enable(void)
92 {
93 return 0;
94 }
95
96 int kvm_arch_hardware_setup(void)
97 {
98 return 0;
99 }
100
101 void kvm_arch_check_processor_compat(void *rtn)
102 {
103 *(int *)rtn = 0;
104 }
105
106 static void kvm_mips_init_tlbs(struct kvm *kvm)
107 {
108 unsigned long wired;
109
110 /*
111 * Add a wired entry to the TLB, it is used to map the commpage to
112 * the Guest kernel
113 */
114 wired = read_c0_wired();
115 write_c0_wired(wired + 1);
116 mtc0_tlbw_hazard();
117 kvm->arch.commpage_tlb = wired;
118
119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
120 kvm->arch.commpage_tlb);
121 }
122
123 static void kvm_mips_init_vm_percpu(void *arg)
124 {
125 struct kvm *kvm = (struct kvm *)arg;
126
127 kvm_mips_init_tlbs(kvm);
128 kvm_mips_callbacks->vm_init(kvm);
129
130 }
131
132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
133 {
134 if (atomic_inc_return(&kvm_mips_instance) == 1) {
135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
136 __func__);
137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
138 }
139
140 return 0;
141 }
142
143 void kvm_mips_free_vcpus(struct kvm *kvm)
144 {
145 unsigned int i;
146 struct kvm_vcpu *vcpu;
147
148 /* Put the pages we reserved for the guest pmap */
149 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
150 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
151 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
152 }
153 kfree(kvm->arch.guest_pmap);
154
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 kvm_arch_vcpu_free(vcpu);
157 }
158
159 mutex_lock(&kvm->lock);
160
161 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
162 kvm->vcpus[i] = NULL;
163
164 atomic_set(&kvm->online_vcpus, 0);
165
166 mutex_unlock(&kvm->lock);
167 }
168
169 static void kvm_mips_uninit_tlbs(void *arg)
170 {
171 /* Restore wired count */
172 write_c0_wired(0);
173 mtc0_tlbw_hazard();
174 /* Clear out all the TLBs */
175 kvm_local_flush_tlb_all();
176 }
177
178 void kvm_arch_destroy_vm(struct kvm *kvm)
179 {
180 kvm_mips_free_vcpus(kvm);
181
182 /* If this is the last instance, restore wired count */
183 if (atomic_dec_return(&kvm_mips_instance) == 0) {
184 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
185 __func__);
186 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
187 }
188 }
189
190 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
191 unsigned long arg)
192 {
193 return -ENOIOCTLCMD;
194 }
195
196 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
197 unsigned long npages)
198 {
199 return 0;
200 }
201
202 int kvm_arch_prepare_memory_region(struct kvm *kvm,
203 struct kvm_memory_slot *memslot,
204 const struct kvm_userspace_memory_region *mem,
205 enum kvm_mr_change change)
206 {
207 return 0;
208 }
209
210 void kvm_arch_commit_memory_region(struct kvm *kvm,
211 const struct kvm_userspace_memory_region *mem,
212 const struct kvm_memory_slot *old,
213 const struct kvm_memory_slot *new,
214 enum kvm_mr_change change)
215 {
216 unsigned long npages = 0;
217 int i;
218
219 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
220 __func__, kvm, mem->slot, mem->guest_phys_addr,
221 mem->memory_size, mem->userspace_addr);
222
223 /* Setup Guest PMAP table */
224 if (!kvm->arch.guest_pmap) {
225 if (mem->slot == 0)
226 npages = mem->memory_size >> PAGE_SHIFT;
227
228 if (npages) {
229 kvm->arch.guest_pmap_npages = npages;
230 kvm->arch.guest_pmap =
231 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
232
233 if (!kvm->arch.guest_pmap) {
234 kvm_err("Failed to allocate guest PMAP\n");
235 return;
236 }
237
238 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
239 npages, kvm->arch.guest_pmap);
240
241 /* Now setup the page table */
242 for (i = 0; i < npages; i++)
243 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
244 }
245 }
246 }
247
248 static inline void dump_handler(const char *symbol, void *start, void *end)
249 {
250 u32 *p;
251
252 pr_debug("LEAF(%s)\n", symbol);
253
254 pr_debug("\t.set push\n");
255 pr_debug("\t.set noreorder\n");
256
257 for (p = start; p < (u32 *)end; ++p)
258 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
259
260 pr_debug("\t.set\tpop\n");
261
262 pr_debug("\tEND(%s)\n", symbol);
263 }
264
265 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
266 {
267 int err, size;
268 void *gebase, *p;
269 int i;
270
271 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
272
273 if (!vcpu) {
274 err = -ENOMEM;
275 goto out;
276 }
277
278 err = kvm_vcpu_init(vcpu, kvm, id);
279
280 if (err)
281 goto out_free_cpu;
282
283 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
284
285 /*
286 * Allocate space for host mode exception handlers that handle
287 * guest mode exits
288 */
289 if (cpu_has_veic || cpu_has_vint)
290 size = 0x200 + VECTORSPACING * 64;
291 else
292 size = 0x4000;
293
294 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
295
296 if (!gebase) {
297 err = -ENOMEM;
298 goto out_uninit_cpu;
299 }
300 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
301 ALIGN(size, PAGE_SIZE), gebase);
302
303 /* Save new ebase */
304 vcpu->arch.guest_ebase = gebase;
305
306 /* Build guest exception vectors dynamically in unmapped memory */
307
308 /* TLB Refill, EXL = 0 */
309 kvm_mips_build_exception(gebase);
310
311 /* General Exception Entry point */
312 kvm_mips_build_exception(gebase + 0x180);
313
314 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
315 for (i = 0; i < 8; i++) {
316 kvm_debug("L1 Vectored handler @ %p\n",
317 gebase + 0x200 + (i * VECTORSPACING));
318 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING);
319 }
320
321 /* General exit handler */
322 p = gebase + 0x2000;
323 p = kvm_mips_build_exit(p);
324
325 /* Guest entry routine */
326 vcpu->arch.vcpu_run = p;
327 p = kvm_mips_build_vcpu_run(p);
328
329 /* Dump the generated code */
330 pr_debug("#include <asm/asm.h>\n");
331 pr_debug("#include <asm/regdef.h>\n");
332 pr_debug("\n");
333 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
334 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
335 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
336
337 /* Invalidate the icache for these ranges */
338 local_flush_icache_range((unsigned long)gebase,
339 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
340
341 /*
342 * Allocate comm page for guest kernel, a TLB will be reserved for
343 * mapping GVA @ 0xFFFF8000 to this page
344 */
345 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
346
347 if (!vcpu->arch.kseg0_commpage) {
348 err = -ENOMEM;
349 goto out_free_gebase;
350 }
351
352 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
353 kvm_mips_commpage_init(vcpu);
354
355 /* Init */
356 vcpu->arch.last_sched_cpu = -1;
357
358 /* Start off the timer */
359 kvm_mips_init_count(vcpu);
360
361 return vcpu;
362
363 out_free_gebase:
364 kfree(gebase);
365
366 out_uninit_cpu:
367 kvm_vcpu_uninit(vcpu);
368
369 out_free_cpu:
370 kfree(vcpu);
371
372 out:
373 return ERR_PTR(err);
374 }
375
376 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
377 {
378 hrtimer_cancel(&vcpu->arch.comparecount_timer);
379
380 kvm_vcpu_uninit(vcpu);
381
382 kvm_mips_dump_stats(vcpu);
383
384 kfree(vcpu->arch.guest_ebase);
385 kfree(vcpu->arch.kseg0_commpage);
386 kfree(vcpu);
387 }
388
389 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
390 {
391 kvm_arch_vcpu_free(vcpu);
392 }
393
394 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
395 struct kvm_guest_debug *dbg)
396 {
397 return -ENOIOCTLCMD;
398 }
399
400 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
401 {
402 int r = 0;
403 sigset_t sigsaved;
404
405 if (vcpu->sigset_active)
406 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
407
408 if (vcpu->mmio_needed) {
409 if (!vcpu->mmio_is_write)
410 kvm_mips_complete_mmio_load(vcpu, run);
411 vcpu->mmio_needed = 0;
412 }
413
414 lose_fpu(1);
415
416 local_irq_disable();
417 /* Check if we have any exceptions/interrupts pending */
418 kvm_mips_deliver_interrupts(vcpu,
419 kvm_read_c0_guest_cause(vcpu->arch.cop0));
420
421 guest_enter_irqoff();
422
423 /* Disable hardware page table walking while in guest */
424 htw_stop();
425
426 trace_kvm_enter(vcpu);
427 r = vcpu->arch.vcpu_run(run, vcpu);
428 trace_kvm_out(vcpu);
429
430 /* Re-enable HTW before enabling interrupts */
431 htw_start();
432
433 guest_exit_irqoff();
434 local_irq_enable();
435
436 if (vcpu->sigset_active)
437 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
438
439 return r;
440 }
441
442 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
443 struct kvm_mips_interrupt *irq)
444 {
445 int intr = (int)irq->irq;
446 struct kvm_vcpu *dvcpu = NULL;
447
448 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
449 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
450 (int)intr);
451
452 if (irq->cpu == -1)
453 dvcpu = vcpu;
454 else
455 dvcpu = vcpu->kvm->vcpus[irq->cpu];
456
457 if (intr == 2 || intr == 3 || intr == 4) {
458 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
459
460 } else if (intr == -2 || intr == -3 || intr == -4) {
461 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
462 } else {
463 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
464 irq->cpu, irq->irq);
465 return -EINVAL;
466 }
467
468 dvcpu->arch.wait = 0;
469
470 if (swait_active(&dvcpu->wq))
471 swake_up(&dvcpu->wq);
472
473 return 0;
474 }
475
476 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
477 struct kvm_mp_state *mp_state)
478 {
479 return -ENOIOCTLCMD;
480 }
481
482 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
483 struct kvm_mp_state *mp_state)
484 {
485 return -ENOIOCTLCMD;
486 }
487
488 static u64 kvm_mips_get_one_regs[] = {
489 KVM_REG_MIPS_R0,
490 KVM_REG_MIPS_R1,
491 KVM_REG_MIPS_R2,
492 KVM_REG_MIPS_R3,
493 KVM_REG_MIPS_R4,
494 KVM_REG_MIPS_R5,
495 KVM_REG_MIPS_R6,
496 KVM_REG_MIPS_R7,
497 KVM_REG_MIPS_R8,
498 KVM_REG_MIPS_R9,
499 KVM_REG_MIPS_R10,
500 KVM_REG_MIPS_R11,
501 KVM_REG_MIPS_R12,
502 KVM_REG_MIPS_R13,
503 KVM_REG_MIPS_R14,
504 KVM_REG_MIPS_R15,
505 KVM_REG_MIPS_R16,
506 KVM_REG_MIPS_R17,
507 KVM_REG_MIPS_R18,
508 KVM_REG_MIPS_R19,
509 KVM_REG_MIPS_R20,
510 KVM_REG_MIPS_R21,
511 KVM_REG_MIPS_R22,
512 KVM_REG_MIPS_R23,
513 KVM_REG_MIPS_R24,
514 KVM_REG_MIPS_R25,
515 KVM_REG_MIPS_R26,
516 KVM_REG_MIPS_R27,
517 KVM_REG_MIPS_R28,
518 KVM_REG_MIPS_R29,
519 KVM_REG_MIPS_R30,
520 KVM_REG_MIPS_R31,
521
522 KVM_REG_MIPS_HI,
523 KVM_REG_MIPS_LO,
524 KVM_REG_MIPS_PC,
525
526 KVM_REG_MIPS_CP0_INDEX,
527 KVM_REG_MIPS_CP0_CONTEXT,
528 KVM_REG_MIPS_CP0_USERLOCAL,
529 KVM_REG_MIPS_CP0_PAGEMASK,
530 KVM_REG_MIPS_CP0_WIRED,
531 KVM_REG_MIPS_CP0_HWRENA,
532 KVM_REG_MIPS_CP0_BADVADDR,
533 KVM_REG_MIPS_CP0_COUNT,
534 KVM_REG_MIPS_CP0_ENTRYHI,
535 KVM_REG_MIPS_CP0_COMPARE,
536 KVM_REG_MIPS_CP0_STATUS,
537 KVM_REG_MIPS_CP0_CAUSE,
538 KVM_REG_MIPS_CP0_EPC,
539 KVM_REG_MIPS_CP0_PRID,
540 KVM_REG_MIPS_CP0_CONFIG,
541 KVM_REG_MIPS_CP0_CONFIG1,
542 KVM_REG_MIPS_CP0_CONFIG2,
543 KVM_REG_MIPS_CP0_CONFIG3,
544 KVM_REG_MIPS_CP0_CONFIG4,
545 KVM_REG_MIPS_CP0_CONFIG5,
546 KVM_REG_MIPS_CP0_CONFIG7,
547 KVM_REG_MIPS_CP0_ERROREPC,
548
549 KVM_REG_MIPS_COUNT_CTL,
550 KVM_REG_MIPS_COUNT_RESUME,
551 KVM_REG_MIPS_COUNT_HZ,
552 };
553
554 static u64 kvm_mips_get_one_regs_fpu[] = {
555 KVM_REG_MIPS_FCR_IR,
556 KVM_REG_MIPS_FCR_CSR,
557 };
558
559 static u64 kvm_mips_get_one_regs_msa[] = {
560 KVM_REG_MIPS_MSA_IR,
561 KVM_REG_MIPS_MSA_CSR,
562 };
563
564 static u64 kvm_mips_get_one_regs_kscratch[] = {
565 KVM_REG_MIPS_CP0_KSCRATCH1,
566 KVM_REG_MIPS_CP0_KSCRATCH2,
567 KVM_REG_MIPS_CP0_KSCRATCH3,
568 KVM_REG_MIPS_CP0_KSCRATCH4,
569 KVM_REG_MIPS_CP0_KSCRATCH5,
570 KVM_REG_MIPS_CP0_KSCRATCH6,
571 };
572
573 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
574 {
575 unsigned long ret;
576
577 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
578 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
579 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
580 /* odd doubles */
581 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
582 ret += 16;
583 }
584 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
585 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
586 ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
587 ret += kvm_mips_callbacks->num_regs(vcpu);
588
589 return ret;
590 }
591
592 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
593 {
594 u64 index;
595 unsigned int i;
596
597 if (copy_to_user(indices, kvm_mips_get_one_regs,
598 sizeof(kvm_mips_get_one_regs)))
599 return -EFAULT;
600 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
601
602 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
603 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
604 sizeof(kvm_mips_get_one_regs_fpu)))
605 return -EFAULT;
606 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
607
608 for (i = 0; i < 32; ++i) {
609 index = KVM_REG_MIPS_FPR_32(i);
610 if (copy_to_user(indices, &index, sizeof(index)))
611 return -EFAULT;
612 ++indices;
613
614 /* skip odd doubles if no F64 */
615 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
616 continue;
617
618 index = KVM_REG_MIPS_FPR_64(i);
619 if (copy_to_user(indices, &index, sizeof(index)))
620 return -EFAULT;
621 ++indices;
622 }
623 }
624
625 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
626 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
627 sizeof(kvm_mips_get_one_regs_msa)))
628 return -EFAULT;
629 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
630
631 for (i = 0; i < 32; ++i) {
632 index = KVM_REG_MIPS_VEC_128(i);
633 if (copy_to_user(indices, &index, sizeof(index)))
634 return -EFAULT;
635 ++indices;
636 }
637 }
638
639 for (i = 0; i < 6; ++i) {
640 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
641 continue;
642
643 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
644 sizeof(kvm_mips_get_one_regs_kscratch[i])))
645 return -EFAULT;
646 ++indices;
647 }
648
649 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
650 }
651
652 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
653 const struct kvm_one_reg *reg)
654 {
655 struct mips_coproc *cop0 = vcpu->arch.cop0;
656 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
657 int ret;
658 s64 v;
659 s64 vs[2];
660 unsigned int idx;
661
662 switch (reg->id) {
663 /* General purpose registers */
664 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
665 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
666 break;
667 case KVM_REG_MIPS_HI:
668 v = (long)vcpu->arch.hi;
669 break;
670 case KVM_REG_MIPS_LO:
671 v = (long)vcpu->arch.lo;
672 break;
673 case KVM_REG_MIPS_PC:
674 v = (long)vcpu->arch.pc;
675 break;
676
677 /* Floating point registers */
678 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
679 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
680 return -EINVAL;
681 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
682 /* Odd singles in top of even double when FR=0 */
683 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
684 v = get_fpr32(&fpu->fpr[idx], 0);
685 else
686 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
687 break;
688 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
689 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
690 return -EINVAL;
691 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
692 /* Can't access odd doubles in FR=0 mode */
693 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
694 return -EINVAL;
695 v = get_fpr64(&fpu->fpr[idx], 0);
696 break;
697 case KVM_REG_MIPS_FCR_IR:
698 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
699 return -EINVAL;
700 v = boot_cpu_data.fpu_id;
701 break;
702 case KVM_REG_MIPS_FCR_CSR:
703 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
704 return -EINVAL;
705 v = fpu->fcr31;
706 break;
707
708 /* MIPS SIMD Architecture (MSA) registers */
709 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
710 if (!kvm_mips_guest_has_msa(&vcpu->arch))
711 return -EINVAL;
712 /* Can't access MSA registers in FR=0 mode */
713 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
714 return -EINVAL;
715 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
716 #ifdef CONFIG_CPU_LITTLE_ENDIAN
717 /* least significant byte first */
718 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
719 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
720 #else
721 /* most significant byte first */
722 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
723 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
724 #endif
725 break;
726 case KVM_REG_MIPS_MSA_IR:
727 if (!kvm_mips_guest_has_msa(&vcpu->arch))
728 return -EINVAL;
729 v = boot_cpu_data.msa_id;
730 break;
731 case KVM_REG_MIPS_MSA_CSR:
732 if (!kvm_mips_guest_has_msa(&vcpu->arch))
733 return -EINVAL;
734 v = fpu->msacsr;
735 break;
736
737 /* Co-processor 0 registers */
738 case KVM_REG_MIPS_CP0_INDEX:
739 v = (long)kvm_read_c0_guest_index(cop0);
740 break;
741 case KVM_REG_MIPS_CP0_CONTEXT:
742 v = (long)kvm_read_c0_guest_context(cop0);
743 break;
744 case KVM_REG_MIPS_CP0_USERLOCAL:
745 v = (long)kvm_read_c0_guest_userlocal(cop0);
746 break;
747 case KVM_REG_MIPS_CP0_PAGEMASK:
748 v = (long)kvm_read_c0_guest_pagemask(cop0);
749 break;
750 case KVM_REG_MIPS_CP0_WIRED:
751 v = (long)kvm_read_c0_guest_wired(cop0);
752 break;
753 case KVM_REG_MIPS_CP0_HWRENA:
754 v = (long)kvm_read_c0_guest_hwrena(cop0);
755 break;
756 case KVM_REG_MIPS_CP0_BADVADDR:
757 v = (long)kvm_read_c0_guest_badvaddr(cop0);
758 break;
759 case KVM_REG_MIPS_CP0_ENTRYHI:
760 v = (long)kvm_read_c0_guest_entryhi(cop0);
761 break;
762 case KVM_REG_MIPS_CP0_COMPARE:
763 v = (long)kvm_read_c0_guest_compare(cop0);
764 break;
765 case KVM_REG_MIPS_CP0_STATUS:
766 v = (long)kvm_read_c0_guest_status(cop0);
767 break;
768 case KVM_REG_MIPS_CP0_CAUSE:
769 v = (long)kvm_read_c0_guest_cause(cop0);
770 break;
771 case KVM_REG_MIPS_CP0_EPC:
772 v = (long)kvm_read_c0_guest_epc(cop0);
773 break;
774 case KVM_REG_MIPS_CP0_PRID:
775 v = (long)kvm_read_c0_guest_prid(cop0);
776 break;
777 case KVM_REG_MIPS_CP0_CONFIG:
778 v = (long)kvm_read_c0_guest_config(cop0);
779 break;
780 case KVM_REG_MIPS_CP0_CONFIG1:
781 v = (long)kvm_read_c0_guest_config1(cop0);
782 break;
783 case KVM_REG_MIPS_CP0_CONFIG2:
784 v = (long)kvm_read_c0_guest_config2(cop0);
785 break;
786 case KVM_REG_MIPS_CP0_CONFIG3:
787 v = (long)kvm_read_c0_guest_config3(cop0);
788 break;
789 case KVM_REG_MIPS_CP0_CONFIG4:
790 v = (long)kvm_read_c0_guest_config4(cop0);
791 break;
792 case KVM_REG_MIPS_CP0_CONFIG5:
793 v = (long)kvm_read_c0_guest_config5(cop0);
794 break;
795 case KVM_REG_MIPS_CP0_CONFIG7:
796 v = (long)kvm_read_c0_guest_config7(cop0);
797 break;
798 case KVM_REG_MIPS_CP0_ERROREPC:
799 v = (long)kvm_read_c0_guest_errorepc(cop0);
800 break;
801 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
802 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
803 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
804 return -EINVAL;
805 switch (idx) {
806 case 2:
807 v = (long)kvm_read_c0_guest_kscratch1(cop0);
808 break;
809 case 3:
810 v = (long)kvm_read_c0_guest_kscratch2(cop0);
811 break;
812 case 4:
813 v = (long)kvm_read_c0_guest_kscratch3(cop0);
814 break;
815 case 5:
816 v = (long)kvm_read_c0_guest_kscratch4(cop0);
817 break;
818 case 6:
819 v = (long)kvm_read_c0_guest_kscratch5(cop0);
820 break;
821 case 7:
822 v = (long)kvm_read_c0_guest_kscratch6(cop0);
823 break;
824 }
825 break;
826 /* registers to be handled specially */
827 default:
828 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
829 if (ret)
830 return ret;
831 break;
832 }
833 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
834 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
835
836 return put_user(v, uaddr64);
837 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
838 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
839 u32 v32 = (u32)v;
840
841 return put_user(v32, uaddr32);
842 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
843 void __user *uaddr = (void __user *)(long)reg->addr;
844
845 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
846 } else {
847 return -EINVAL;
848 }
849 }
850
851 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
852 const struct kvm_one_reg *reg)
853 {
854 struct mips_coproc *cop0 = vcpu->arch.cop0;
855 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
856 s64 v;
857 s64 vs[2];
858 unsigned int idx;
859
860 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
861 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
862
863 if (get_user(v, uaddr64) != 0)
864 return -EFAULT;
865 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
866 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
867 s32 v32;
868
869 if (get_user(v32, uaddr32) != 0)
870 return -EFAULT;
871 v = (s64)v32;
872 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
873 void __user *uaddr = (void __user *)(long)reg->addr;
874
875 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
876 } else {
877 return -EINVAL;
878 }
879
880 switch (reg->id) {
881 /* General purpose registers */
882 case KVM_REG_MIPS_R0:
883 /* Silently ignore requests to set $0 */
884 break;
885 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
886 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
887 break;
888 case KVM_REG_MIPS_HI:
889 vcpu->arch.hi = v;
890 break;
891 case KVM_REG_MIPS_LO:
892 vcpu->arch.lo = v;
893 break;
894 case KVM_REG_MIPS_PC:
895 vcpu->arch.pc = v;
896 break;
897
898 /* Floating point registers */
899 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
900 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
901 return -EINVAL;
902 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
903 /* Odd singles in top of even double when FR=0 */
904 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
905 set_fpr32(&fpu->fpr[idx], 0, v);
906 else
907 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
908 break;
909 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
910 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
911 return -EINVAL;
912 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
913 /* Can't access odd doubles in FR=0 mode */
914 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
915 return -EINVAL;
916 set_fpr64(&fpu->fpr[idx], 0, v);
917 break;
918 case KVM_REG_MIPS_FCR_IR:
919 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
920 return -EINVAL;
921 /* Read-only */
922 break;
923 case KVM_REG_MIPS_FCR_CSR:
924 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
925 return -EINVAL;
926 fpu->fcr31 = v;
927 break;
928
929 /* MIPS SIMD Architecture (MSA) registers */
930 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
931 if (!kvm_mips_guest_has_msa(&vcpu->arch))
932 return -EINVAL;
933 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
934 #ifdef CONFIG_CPU_LITTLE_ENDIAN
935 /* least significant byte first */
936 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
937 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
938 #else
939 /* most significant byte first */
940 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
941 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
942 #endif
943 break;
944 case KVM_REG_MIPS_MSA_IR:
945 if (!kvm_mips_guest_has_msa(&vcpu->arch))
946 return -EINVAL;
947 /* Read-only */
948 break;
949 case KVM_REG_MIPS_MSA_CSR:
950 if (!kvm_mips_guest_has_msa(&vcpu->arch))
951 return -EINVAL;
952 fpu->msacsr = v;
953 break;
954
955 /* Co-processor 0 registers */
956 case KVM_REG_MIPS_CP0_INDEX:
957 kvm_write_c0_guest_index(cop0, v);
958 break;
959 case KVM_REG_MIPS_CP0_CONTEXT:
960 kvm_write_c0_guest_context(cop0, v);
961 break;
962 case KVM_REG_MIPS_CP0_USERLOCAL:
963 kvm_write_c0_guest_userlocal(cop0, v);
964 break;
965 case KVM_REG_MIPS_CP0_PAGEMASK:
966 kvm_write_c0_guest_pagemask(cop0, v);
967 break;
968 case KVM_REG_MIPS_CP0_WIRED:
969 kvm_write_c0_guest_wired(cop0, v);
970 break;
971 case KVM_REG_MIPS_CP0_HWRENA:
972 kvm_write_c0_guest_hwrena(cop0, v);
973 break;
974 case KVM_REG_MIPS_CP0_BADVADDR:
975 kvm_write_c0_guest_badvaddr(cop0, v);
976 break;
977 case KVM_REG_MIPS_CP0_ENTRYHI:
978 kvm_write_c0_guest_entryhi(cop0, v);
979 break;
980 case KVM_REG_MIPS_CP0_STATUS:
981 kvm_write_c0_guest_status(cop0, v);
982 break;
983 case KVM_REG_MIPS_CP0_EPC:
984 kvm_write_c0_guest_epc(cop0, v);
985 break;
986 case KVM_REG_MIPS_CP0_PRID:
987 kvm_write_c0_guest_prid(cop0, v);
988 break;
989 case KVM_REG_MIPS_CP0_ERROREPC:
990 kvm_write_c0_guest_errorepc(cop0, v);
991 break;
992 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
993 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
994 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
995 return -EINVAL;
996 switch (idx) {
997 case 2:
998 kvm_write_c0_guest_kscratch1(cop0, v);
999 break;
1000 case 3:
1001 kvm_write_c0_guest_kscratch2(cop0, v);
1002 break;
1003 case 4:
1004 kvm_write_c0_guest_kscratch3(cop0, v);
1005 break;
1006 case 5:
1007 kvm_write_c0_guest_kscratch4(cop0, v);
1008 break;
1009 case 6:
1010 kvm_write_c0_guest_kscratch5(cop0, v);
1011 break;
1012 case 7:
1013 kvm_write_c0_guest_kscratch6(cop0, v);
1014 break;
1015 }
1016 break;
1017 /* registers to be handled specially */
1018 default:
1019 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1020 }
1021 return 0;
1022 }
1023
1024 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1025 struct kvm_enable_cap *cap)
1026 {
1027 int r = 0;
1028
1029 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1030 return -EINVAL;
1031 if (cap->flags)
1032 return -EINVAL;
1033 if (cap->args[0])
1034 return -EINVAL;
1035
1036 switch (cap->cap) {
1037 case KVM_CAP_MIPS_FPU:
1038 vcpu->arch.fpu_enabled = true;
1039 break;
1040 case KVM_CAP_MIPS_MSA:
1041 vcpu->arch.msa_enabled = true;
1042 break;
1043 default:
1044 r = -EINVAL;
1045 break;
1046 }
1047
1048 return r;
1049 }
1050
1051 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1052 unsigned long arg)
1053 {
1054 struct kvm_vcpu *vcpu = filp->private_data;
1055 void __user *argp = (void __user *)arg;
1056 long r;
1057
1058 switch (ioctl) {
1059 case KVM_SET_ONE_REG:
1060 case KVM_GET_ONE_REG: {
1061 struct kvm_one_reg reg;
1062
1063 if (copy_from_user(&reg, argp, sizeof(reg)))
1064 return -EFAULT;
1065 if (ioctl == KVM_SET_ONE_REG)
1066 return kvm_mips_set_reg(vcpu, &reg);
1067 else
1068 return kvm_mips_get_reg(vcpu, &reg);
1069 }
1070 case KVM_GET_REG_LIST: {
1071 struct kvm_reg_list __user *user_list = argp;
1072 struct kvm_reg_list reg_list;
1073 unsigned n;
1074
1075 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1076 return -EFAULT;
1077 n = reg_list.n;
1078 reg_list.n = kvm_mips_num_regs(vcpu);
1079 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1080 return -EFAULT;
1081 if (n < reg_list.n)
1082 return -E2BIG;
1083 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1084 }
1085 case KVM_NMI:
1086 /* Treat the NMI as a CPU reset */
1087 r = kvm_mips_reset_vcpu(vcpu);
1088 break;
1089 case KVM_INTERRUPT:
1090 {
1091 struct kvm_mips_interrupt irq;
1092
1093 r = -EFAULT;
1094 if (copy_from_user(&irq, argp, sizeof(irq)))
1095 goto out;
1096
1097 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1098 irq.irq);
1099
1100 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1101 break;
1102 }
1103 case KVM_ENABLE_CAP: {
1104 struct kvm_enable_cap cap;
1105
1106 r = -EFAULT;
1107 if (copy_from_user(&cap, argp, sizeof(cap)))
1108 goto out;
1109 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1110 break;
1111 }
1112 default:
1113 r = -ENOIOCTLCMD;
1114 }
1115
1116 out:
1117 return r;
1118 }
1119
1120 /* Get (and clear) the dirty memory log for a memory slot. */
1121 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1122 {
1123 struct kvm_memslots *slots;
1124 struct kvm_memory_slot *memslot;
1125 unsigned long ga, ga_end;
1126 int is_dirty = 0;
1127 int r;
1128 unsigned long n;
1129
1130 mutex_lock(&kvm->slots_lock);
1131
1132 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1133 if (r)
1134 goto out;
1135
1136 /* If nothing is dirty, don't bother messing with page tables. */
1137 if (is_dirty) {
1138 slots = kvm_memslots(kvm);
1139 memslot = id_to_memslot(slots, log->slot);
1140
1141 ga = memslot->base_gfn << PAGE_SHIFT;
1142 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1143
1144 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1145 ga_end);
1146
1147 n = kvm_dirty_bitmap_bytes(memslot);
1148 memset(memslot->dirty_bitmap, 0, n);
1149 }
1150
1151 r = 0;
1152 out:
1153 mutex_unlock(&kvm->slots_lock);
1154 return r;
1155
1156 }
1157
1158 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1159 {
1160 long r;
1161
1162 switch (ioctl) {
1163 default:
1164 r = -ENOIOCTLCMD;
1165 }
1166
1167 return r;
1168 }
1169
1170 int kvm_arch_init(void *opaque)
1171 {
1172 if (kvm_mips_callbacks) {
1173 kvm_err("kvm: module already exists\n");
1174 return -EEXIST;
1175 }
1176
1177 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1178 }
1179
1180 void kvm_arch_exit(void)
1181 {
1182 kvm_mips_callbacks = NULL;
1183 }
1184
1185 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1186 struct kvm_sregs *sregs)
1187 {
1188 return -ENOIOCTLCMD;
1189 }
1190
1191 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1192 struct kvm_sregs *sregs)
1193 {
1194 return -ENOIOCTLCMD;
1195 }
1196
1197 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1198 {
1199 }
1200
1201 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1202 {
1203 return -ENOIOCTLCMD;
1204 }
1205
1206 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1207 {
1208 return -ENOIOCTLCMD;
1209 }
1210
1211 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1212 {
1213 return VM_FAULT_SIGBUS;
1214 }
1215
1216 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1217 {
1218 int r;
1219
1220 switch (ext) {
1221 case KVM_CAP_ONE_REG:
1222 case KVM_CAP_ENABLE_CAP:
1223 r = 1;
1224 break;
1225 case KVM_CAP_COALESCED_MMIO:
1226 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1227 break;
1228 case KVM_CAP_MIPS_FPU:
1229 /* We don't handle systems with inconsistent cpu_has_fpu */
1230 r = !!raw_cpu_has_fpu;
1231 break;
1232 case KVM_CAP_MIPS_MSA:
1233 /*
1234 * We don't support MSA vector partitioning yet:
1235 * 1) It would require explicit support which can't be tested
1236 * yet due to lack of support in current hardware.
1237 * 2) It extends the state that would need to be saved/restored
1238 * by e.g. QEMU for migration.
1239 *
1240 * When vector partitioning hardware becomes available, support
1241 * could be added by requiring a flag when enabling
1242 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1243 * to save/restore the appropriate extra state.
1244 */
1245 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1246 break;
1247 default:
1248 r = 0;
1249 break;
1250 }
1251 return r;
1252 }
1253
1254 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1255 {
1256 return kvm_mips_pending_timer(vcpu);
1257 }
1258
1259 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1260 {
1261 int i;
1262 struct mips_coproc *cop0;
1263
1264 if (!vcpu)
1265 return -1;
1266
1267 kvm_debug("VCPU Register Dump:\n");
1268 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1269 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1270
1271 for (i = 0; i < 32; i += 4) {
1272 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1273 vcpu->arch.gprs[i],
1274 vcpu->arch.gprs[i + 1],
1275 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1276 }
1277 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1278 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1279
1280 cop0 = vcpu->arch.cop0;
1281 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1282 kvm_read_c0_guest_status(cop0),
1283 kvm_read_c0_guest_cause(cop0));
1284
1285 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1286
1287 return 0;
1288 }
1289
1290 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1291 {
1292 int i;
1293
1294 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1295 vcpu->arch.gprs[i] = regs->gpr[i];
1296 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1297 vcpu->arch.hi = regs->hi;
1298 vcpu->arch.lo = regs->lo;
1299 vcpu->arch.pc = regs->pc;
1300
1301 return 0;
1302 }
1303
1304 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1305 {
1306 int i;
1307
1308 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1309 regs->gpr[i] = vcpu->arch.gprs[i];
1310
1311 regs->hi = vcpu->arch.hi;
1312 regs->lo = vcpu->arch.lo;
1313 regs->pc = vcpu->arch.pc;
1314
1315 return 0;
1316 }
1317
1318 static void kvm_mips_comparecount_func(unsigned long data)
1319 {
1320 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1321
1322 kvm_mips_callbacks->queue_timer_int(vcpu);
1323
1324 vcpu->arch.wait = 0;
1325 if (swait_active(&vcpu->wq))
1326 swake_up(&vcpu->wq);
1327 }
1328
1329 /* low level hrtimer wake routine */
1330 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1331 {
1332 struct kvm_vcpu *vcpu;
1333
1334 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1335 kvm_mips_comparecount_func((unsigned long) vcpu);
1336 return kvm_mips_count_timeout(vcpu);
1337 }
1338
1339 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1340 {
1341 kvm_mips_callbacks->vcpu_init(vcpu);
1342 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1343 HRTIMER_MODE_REL);
1344 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1345 return 0;
1346 }
1347
1348 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1349 struct kvm_translation *tr)
1350 {
1351 return 0;
1352 }
1353
1354 /* Initial guest state */
1355 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1356 {
1357 return kvm_mips_callbacks->vcpu_setup(vcpu);
1358 }
1359
1360 static void kvm_mips_set_c0_status(void)
1361 {
1362 u32 status = read_c0_status();
1363
1364 if (cpu_has_dsp)
1365 status |= (ST0_MX);
1366
1367 write_c0_status(status);
1368 ehb();
1369 }
1370
1371 /*
1372 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1373 */
1374 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1375 {
1376 u32 cause = vcpu->arch.host_cp0_cause;
1377 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1378 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1379 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1380 enum emulation_result er = EMULATE_DONE;
1381 int ret = RESUME_GUEST;
1382
1383 /* re-enable HTW before enabling interrupts */
1384 htw_start();
1385
1386 /* Set a default exit reason */
1387 run->exit_reason = KVM_EXIT_UNKNOWN;
1388 run->ready_for_interrupt_injection = 1;
1389
1390 /*
1391 * Set the appropriate status bits based on host CPU features,
1392 * before we hit the scheduler
1393 */
1394 kvm_mips_set_c0_status();
1395
1396 local_irq_enable();
1397
1398 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1399 cause, opc, run, vcpu);
1400 trace_kvm_exit(vcpu, exccode);
1401
1402 /*
1403 * Do a privilege check, if in UM most of these exit conditions end up
1404 * causing an exception to be delivered to the Guest Kernel
1405 */
1406 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1407 if (er == EMULATE_PRIV_FAIL) {
1408 goto skip_emul;
1409 } else if (er == EMULATE_FAIL) {
1410 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1411 ret = RESUME_HOST;
1412 goto skip_emul;
1413 }
1414
1415 switch (exccode) {
1416 case EXCCODE_INT:
1417 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1418
1419 ++vcpu->stat.int_exits;
1420
1421 if (need_resched())
1422 cond_resched();
1423
1424 ret = RESUME_GUEST;
1425 break;
1426
1427 case EXCCODE_CPU:
1428 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1429
1430 ++vcpu->stat.cop_unusable_exits;
1431 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1432 /* XXXKYMA: Might need to return to user space */
1433 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1434 ret = RESUME_HOST;
1435 break;
1436
1437 case EXCCODE_MOD:
1438 ++vcpu->stat.tlbmod_exits;
1439 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1440 break;
1441
1442 case EXCCODE_TLBS:
1443 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1444 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1445 badvaddr);
1446
1447 ++vcpu->stat.tlbmiss_st_exits;
1448 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1449 break;
1450
1451 case EXCCODE_TLBL:
1452 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1453 cause, opc, badvaddr);
1454
1455 ++vcpu->stat.tlbmiss_ld_exits;
1456 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1457 break;
1458
1459 case EXCCODE_ADES:
1460 ++vcpu->stat.addrerr_st_exits;
1461 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1462 break;
1463
1464 case EXCCODE_ADEL:
1465 ++vcpu->stat.addrerr_ld_exits;
1466 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1467 break;
1468
1469 case EXCCODE_SYS:
1470 ++vcpu->stat.syscall_exits;
1471 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1472 break;
1473
1474 case EXCCODE_RI:
1475 ++vcpu->stat.resvd_inst_exits;
1476 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1477 break;
1478
1479 case EXCCODE_BP:
1480 ++vcpu->stat.break_inst_exits;
1481 ret = kvm_mips_callbacks->handle_break(vcpu);
1482 break;
1483
1484 case EXCCODE_TR:
1485 ++vcpu->stat.trap_inst_exits;
1486 ret = kvm_mips_callbacks->handle_trap(vcpu);
1487 break;
1488
1489 case EXCCODE_MSAFPE:
1490 ++vcpu->stat.msa_fpe_exits;
1491 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1492 break;
1493
1494 case EXCCODE_FPE:
1495 ++vcpu->stat.fpe_exits;
1496 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1497 break;
1498
1499 case EXCCODE_MSADIS:
1500 ++vcpu->stat.msa_disabled_exits;
1501 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1502 break;
1503
1504 default:
1505 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1506 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1507 kvm_read_c0_guest_status(vcpu->arch.cop0));
1508 kvm_arch_vcpu_dump_regs(vcpu);
1509 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1510 ret = RESUME_HOST;
1511 break;
1512
1513 }
1514
1515 skip_emul:
1516 local_irq_disable();
1517
1518 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1519 kvm_mips_deliver_interrupts(vcpu, cause);
1520
1521 if (!(ret & RESUME_HOST)) {
1522 /* Only check for signals if not already exiting to userspace */
1523 if (signal_pending(current)) {
1524 run->exit_reason = KVM_EXIT_INTR;
1525 ret = (-EINTR << 2) | RESUME_HOST;
1526 ++vcpu->stat.signal_exits;
1527 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1528 }
1529 }
1530
1531 if (ret == RESUME_GUEST) {
1532 trace_kvm_reenter(vcpu);
1533
1534 /*
1535 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1536 * is live), restore FCR31 / MSACSR.
1537 *
1538 * This should be before returning to the guest exception
1539 * vector, as it may well cause an [MSA] FP exception if there
1540 * are pending exception bits unmasked. (see
1541 * kvm_mips_csr_die_notifier() for how that is handled).
1542 */
1543 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1544 read_c0_status() & ST0_CU1)
1545 __kvm_restore_fcsr(&vcpu->arch);
1546
1547 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1548 read_c0_config5() & MIPS_CONF5_MSAEN)
1549 __kvm_restore_msacsr(&vcpu->arch);
1550 }
1551
1552 /* Disable HTW before returning to guest or host */
1553 htw_stop();
1554
1555 return ret;
1556 }
1557
1558 /* Enable FPU for guest and restore context */
1559 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1560 {
1561 struct mips_coproc *cop0 = vcpu->arch.cop0;
1562 unsigned int sr, cfg5;
1563
1564 preempt_disable();
1565
1566 sr = kvm_read_c0_guest_status(cop0);
1567
1568 /*
1569 * If MSA state is already live, it is undefined how it interacts with
1570 * FR=0 FPU state, and we don't want to hit reserved instruction
1571 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1572 * play it safe and save it first.
1573 *
1574 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1575 * get called when guest CU1 is set, however we can't trust the guest
1576 * not to clobber the status register directly via the commpage.
1577 */
1578 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1579 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1580 kvm_lose_fpu(vcpu);
1581
1582 /*
1583 * Enable FPU for guest
1584 * We set FR and FRE according to guest context
1585 */
1586 change_c0_status(ST0_CU1 | ST0_FR, sr);
1587 if (cpu_has_fre) {
1588 cfg5 = kvm_read_c0_guest_config5(cop0);
1589 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1590 }
1591 enable_fpu_hazard();
1592
1593 /* If guest FPU state not active, restore it now */
1594 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1595 __kvm_restore_fpu(&vcpu->arch);
1596 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1597 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1598 } else {
1599 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1600 }
1601
1602 preempt_enable();
1603 }
1604
1605 #ifdef CONFIG_CPU_HAS_MSA
1606 /* Enable MSA for guest and restore context */
1607 void kvm_own_msa(struct kvm_vcpu *vcpu)
1608 {
1609 struct mips_coproc *cop0 = vcpu->arch.cop0;
1610 unsigned int sr, cfg5;
1611
1612 preempt_disable();
1613
1614 /*
1615 * Enable FPU if enabled in guest, since we're restoring FPU context
1616 * anyway. We set FR and FRE according to guest context.
1617 */
1618 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1619 sr = kvm_read_c0_guest_status(cop0);
1620
1621 /*
1622 * If FR=0 FPU state is already live, it is undefined how it
1623 * interacts with MSA state, so play it safe and save it first.
1624 */
1625 if (!(sr & ST0_FR) &&
1626 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1627 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1628 kvm_lose_fpu(vcpu);
1629
1630 change_c0_status(ST0_CU1 | ST0_FR, sr);
1631 if (sr & ST0_CU1 && cpu_has_fre) {
1632 cfg5 = kvm_read_c0_guest_config5(cop0);
1633 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1634 }
1635 }
1636
1637 /* Enable MSA for guest */
1638 set_c0_config5(MIPS_CONF5_MSAEN);
1639 enable_fpu_hazard();
1640
1641 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1642 case KVM_MIPS_AUX_FPU:
1643 /*
1644 * Guest FPU state already loaded, only restore upper MSA state
1645 */
1646 __kvm_restore_msa_upper(&vcpu->arch);
1647 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1648 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1649 break;
1650 case 0:
1651 /* Neither FPU or MSA already active, restore full MSA state */
1652 __kvm_restore_msa(&vcpu->arch);
1653 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1654 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1655 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1656 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1657 KVM_TRACE_AUX_FPU_MSA);
1658 break;
1659 default:
1660 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1661 break;
1662 }
1663
1664 preempt_enable();
1665 }
1666 #endif
1667
1668 /* Drop FPU & MSA without saving it */
1669 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1670 {
1671 preempt_disable();
1672 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1673 disable_msa();
1674 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1675 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1676 }
1677 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1678 clear_c0_status(ST0_CU1 | ST0_FR);
1679 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1680 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1681 }
1682 preempt_enable();
1683 }
1684
1685 /* Save and disable FPU & MSA */
1686 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1687 {
1688 /*
1689 * FPU & MSA get disabled in root context (hardware) when it is disabled
1690 * in guest context (software), but the register state in the hardware
1691 * may still be in use. This is why we explicitly re-enable the hardware
1692 * before saving.
1693 */
1694
1695 preempt_disable();
1696 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1697 set_c0_config5(MIPS_CONF5_MSAEN);
1698 enable_fpu_hazard();
1699
1700 __kvm_save_msa(&vcpu->arch);
1701 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1702
1703 /* Disable MSA & FPU */
1704 disable_msa();
1705 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1706 clear_c0_status(ST0_CU1 | ST0_FR);
1707 disable_fpu_hazard();
1708 }
1709 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1710 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1711 set_c0_status(ST0_CU1);
1712 enable_fpu_hazard();
1713
1714 __kvm_save_fpu(&vcpu->arch);
1715 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1716 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1717
1718 /* Disable FPU */
1719 clear_c0_status(ST0_CU1 | ST0_FR);
1720 disable_fpu_hazard();
1721 }
1722 preempt_enable();
1723 }
1724
1725 /*
1726 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1727 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1728 * exception if cause bits are set in the value being written.
1729 */
1730 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1731 unsigned long cmd, void *ptr)
1732 {
1733 struct die_args *args = (struct die_args *)ptr;
1734 struct pt_regs *regs = args->regs;
1735 unsigned long pc;
1736
1737 /* Only interested in FPE and MSAFPE */
1738 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1739 return NOTIFY_DONE;
1740
1741 /* Return immediately if guest context isn't active */
1742 if (!(current->flags & PF_VCPU))
1743 return NOTIFY_DONE;
1744
1745 /* Should never get here from user mode */
1746 BUG_ON(user_mode(regs));
1747
1748 pc = instruction_pointer(regs);
1749 switch (cmd) {
1750 case DIE_FP:
1751 /* match 2nd instruction in __kvm_restore_fcsr */
1752 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1753 return NOTIFY_DONE;
1754 break;
1755 case DIE_MSAFP:
1756 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1757 if (!cpu_has_msa ||
1758 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1759 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1760 return NOTIFY_DONE;
1761 break;
1762 }
1763
1764 /* Move PC forward a little and continue executing */
1765 instruction_pointer(regs) += 4;
1766
1767 return NOTIFY_STOP;
1768 }
1769
1770 static struct notifier_block kvm_mips_csr_die_notifier = {
1771 .notifier_call = kvm_mips_csr_die_notify,
1772 };
1773
1774 static int __init kvm_mips_init(void)
1775 {
1776 int ret;
1777
1778 ret = kvm_mips_entry_setup();
1779 if (ret)
1780 return ret;
1781
1782 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1783
1784 if (ret)
1785 return ret;
1786
1787 register_die_notifier(&kvm_mips_csr_die_notifier);
1788
1789 return 0;
1790 }
1791
1792 static void __exit kvm_mips_exit(void)
1793 {
1794 kvm_exit();
1795
1796 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1797 }
1798
1799 module_init(kvm_mips_init);
1800 module_exit(kvm_mips_exit);
1801
1802 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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