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MIPS: KVM: Expose FPU registers
[deliverable/linux.git] / arch / mips / kvm / mips.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kdebug.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
17 #include <linux/fs.h>
18 #include <linux/bootmem.h>
19 #include <asm/fpu.h>
20 #include <asm/page.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
23 #include <asm/pgtable.h>
24
25 #include <linux/kvm_host.h>
26
27 #include "interrupt.h"
28 #include "commpage.h"
29
30 #define CREATE_TRACE_POINTS
31 #include "trace.h"
32
33 #ifndef VECTORSPACING
34 #define VECTORSPACING 0x100 /* for EI/VI mode */
35 #endif
36
37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38 struct kvm_stats_debugfs_item debugfs_entries[] = {
39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
53 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
54 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
55 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
56 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
57 {NULL}
58 };
59
60 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
61 {
62 int i;
63
64 for_each_possible_cpu(i) {
65 vcpu->arch.guest_kernel_asid[i] = 0;
66 vcpu->arch.guest_user_asid[i] = 0;
67 }
68
69 return 0;
70 }
71
72 /*
73 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
74 * Config7, so we are "runnable" if interrupts are pending
75 */
76 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
77 {
78 return !!(vcpu->arch.pending_exceptions);
79 }
80
81 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
82 {
83 return 1;
84 }
85
86 int kvm_arch_hardware_enable(void)
87 {
88 return 0;
89 }
90
91 int kvm_arch_hardware_setup(void)
92 {
93 return 0;
94 }
95
96 void kvm_arch_check_processor_compat(void *rtn)
97 {
98 *(int *)rtn = 0;
99 }
100
101 static void kvm_mips_init_tlbs(struct kvm *kvm)
102 {
103 unsigned long wired;
104
105 /*
106 * Add a wired entry to the TLB, it is used to map the commpage to
107 * the Guest kernel
108 */
109 wired = read_c0_wired();
110 write_c0_wired(wired + 1);
111 mtc0_tlbw_hazard();
112 kvm->arch.commpage_tlb = wired;
113
114 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
115 kvm->arch.commpage_tlb);
116 }
117
118 static void kvm_mips_init_vm_percpu(void *arg)
119 {
120 struct kvm *kvm = (struct kvm *)arg;
121
122 kvm_mips_init_tlbs(kvm);
123 kvm_mips_callbacks->vm_init(kvm);
124
125 }
126
127 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
128 {
129 if (atomic_inc_return(&kvm_mips_instance) == 1) {
130 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
131 __func__);
132 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
133 }
134
135 return 0;
136 }
137
138 void kvm_mips_free_vcpus(struct kvm *kvm)
139 {
140 unsigned int i;
141 struct kvm_vcpu *vcpu;
142
143 /* Put the pages we reserved for the guest pmap */
144 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
145 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
146 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
147 }
148 kfree(kvm->arch.guest_pmap);
149
150 kvm_for_each_vcpu(i, vcpu, kvm) {
151 kvm_arch_vcpu_free(vcpu);
152 }
153
154 mutex_lock(&kvm->lock);
155
156 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
157 kvm->vcpus[i] = NULL;
158
159 atomic_set(&kvm->online_vcpus, 0);
160
161 mutex_unlock(&kvm->lock);
162 }
163
164 static void kvm_mips_uninit_tlbs(void *arg)
165 {
166 /* Restore wired count */
167 write_c0_wired(0);
168 mtc0_tlbw_hazard();
169 /* Clear out all the TLBs */
170 kvm_local_flush_tlb_all();
171 }
172
173 void kvm_arch_destroy_vm(struct kvm *kvm)
174 {
175 kvm_mips_free_vcpus(kvm);
176
177 /* If this is the last instance, restore wired count */
178 if (atomic_dec_return(&kvm_mips_instance) == 0) {
179 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
180 __func__);
181 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
182 }
183 }
184
185 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
186 unsigned long arg)
187 {
188 return -ENOIOCTLCMD;
189 }
190
191 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
192 unsigned long npages)
193 {
194 return 0;
195 }
196
197 int kvm_arch_prepare_memory_region(struct kvm *kvm,
198 struct kvm_memory_slot *memslot,
199 struct kvm_userspace_memory_region *mem,
200 enum kvm_mr_change change)
201 {
202 return 0;
203 }
204
205 void kvm_arch_commit_memory_region(struct kvm *kvm,
206 struct kvm_userspace_memory_region *mem,
207 const struct kvm_memory_slot *old,
208 enum kvm_mr_change change)
209 {
210 unsigned long npages = 0;
211 int i;
212
213 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
214 __func__, kvm, mem->slot, mem->guest_phys_addr,
215 mem->memory_size, mem->userspace_addr);
216
217 /* Setup Guest PMAP table */
218 if (!kvm->arch.guest_pmap) {
219 if (mem->slot == 0)
220 npages = mem->memory_size >> PAGE_SHIFT;
221
222 if (npages) {
223 kvm->arch.guest_pmap_npages = npages;
224 kvm->arch.guest_pmap =
225 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
226
227 if (!kvm->arch.guest_pmap) {
228 kvm_err("Failed to allocate guest PMAP");
229 return;
230 }
231
232 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
233 npages, kvm->arch.guest_pmap);
234
235 /* Now setup the page table */
236 for (i = 0; i < npages; i++)
237 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
238 }
239 }
240 }
241
242 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
243 {
244 int err, size, offset;
245 void *gebase;
246 int i;
247
248 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
249
250 if (!vcpu) {
251 err = -ENOMEM;
252 goto out;
253 }
254
255 err = kvm_vcpu_init(vcpu, kvm, id);
256
257 if (err)
258 goto out_free_cpu;
259
260 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
261
262 /*
263 * Allocate space for host mode exception handlers that handle
264 * guest mode exits
265 */
266 if (cpu_has_veic || cpu_has_vint)
267 size = 0x200 + VECTORSPACING * 64;
268 else
269 size = 0x4000;
270
271 /* Save Linux EBASE */
272 vcpu->arch.host_ebase = (void *)read_c0_ebase();
273
274 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
275
276 if (!gebase) {
277 err = -ENOMEM;
278 goto out_free_cpu;
279 }
280 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
281 ALIGN(size, PAGE_SIZE), gebase);
282
283 /* Save new ebase */
284 vcpu->arch.guest_ebase = gebase;
285
286 /* Copy L1 Guest Exception handler to correct offset */
287
288 /* TLB Refill, EXL = 0 */
289 memcpy(gebase, mips32_exception,
290 mips32_exceptionEnd - mips32_exception);
291
292 /* General Exception Entry point */
293 memcpy(gebase + 0x180, mips32_exception,
294 mips32_exceptionEnd - mips32_exception);
295
296 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
297 for (i = 0; i < 8; i++) {
298 kvm_debug("L1 Vectored handler @ %p\n",
299 gebase + 0x200 + (i * VECTORSPACING));
300 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
301 mips32_exceptionEnd - mips32_exception);
302 }
303
304 /* General handler, relocate to unmapped space for sanity's sake */
305 offset = 0x2000;
306 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
307 gebase + offset,
308 mips32_GuestExceptionEnd - mips32_GuestException);
309
310 memcpy(gebase + offset, mips32_GuestException,
311 mips32_GuestExceptionEnd - mips32_GuestException);
312
313 /* Invalidate the icache for these ranges */
314 local_flush_icache_range((unsigned long)gebase,
315 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
316
317 /*
318 * Allocate comm page for guest kernel, a TLB will be reserved for
319 * mapping GVA @ 0xFFFF8000 to this page
320 */
321 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
322
323 if (!vcpu->arch.kseg0_commpage) {
324 err = -ENOMEM;
325 goto out_free_gebase;
326 }
327
328 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
329 kvm_mips_commpage_init(vcpu);
330
331 /* Init */
332 vcpu->arch.last_sched_cpu = -1;
333
334 /* Start off the timer */
335 kvm_mips_init_count(vcpu);
336
337 return vcpu;
338
339 out_free_gebase:
340 kfree(gebase);
341
342 out_free_cpu:
343 kfree(vcpu);
344
345 out:
346 return ERR_PTR(err);
347 }
348
349 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
350 {
351 hrtimer_cancel(&vcpu->arch.comparecount_timer);
352
353 kvm_vcpu_uninit(vcpu);
354
355 kvm_mips_dump_stats(vcpu);
356
357 kfree(vcpu->arch.guest_ebase);
358 kfree(vcpu->arch.kseg0_commpage);
359 kfree(vcpu);
360 }
361
362 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
363 {
364 kvm_arch_vcpu_free(vcpu);
365 }
366
367 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
368 struct kvm_guest_debug *dbg)
369 {
370 return -ENOIOCTLCMD;
371 }
372
373 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
374 {
375 int r = 0;
376 sigset_t sigsaved;
377
378 if (vcpu->sigset_active)
379 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
380
381 if (vcpu->mmio_needed) {
382 if (!vcpu->mmio_is_write)
383 kvm_mips_complete_mmio_load(vcpu, run);
384 vcpu->mmio_needed = 0;
385 }
386
387 lose_fpu(1);
388
389 local_irq_disable();
390 /* Check if we have any exceptions/interrupts pending */
391 kvm_mips_deliver_interrupts(vcpu,
392 kvm_read_c0_guest_cause(vcpu->arch.cop0));
393
394 kvm_guest_enter();
395
396 /* Disable hardware page table walking while in guest */
397 htw_stop();
398
399 r = __kvm_mips_vcpu_run(run, vcpu);
400
401 /* Re-enable HTW before enabling interrupts */
402 htw_start();
403
404 kvm_guest_exit();
405 local_irq_enable();
406
407 if (vcpu->sigset_active)
408 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
409
410 return r;
411 }
412
413 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
414 struct kvm_mips_interrupt *irq)
415 {
416 int intr = (int)irq->irq;
417 struct kvm_vcpu *dvcpu = NULL;
418
419 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
420 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
421 (int)intr);
422
423 if (irq->cpu == -1)
424 dvcpu = vcpu;
425 else
426 dvcpu = vcpu->kvm->vcpus[irq->cpu];
427
428 if (intr == 2 || intr == 3 || intr == 4) {
429 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
430
431 } else if (intr == -2 || intr == -3 || intr == -4) {
432 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
433 } else {
434 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
435 irq->cpu, irq->irq);
436 return -EINVAL;
437 }
438
439 dvcpu->arch.wait = 0;
440
441 if (waitqueue_active(&dvcpu->wq))
442 wake_up_interruptible(&dvcpu->wq);
443
444 return 0;
445 }
446
447 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
448 struct kvm_mp_state *mp_state)
449 {
450 return -ENOIOCTLCMD;
451 }
452
453 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
454 struct kvm_mp_state *mp_state)
455 {
456 return -ENOIOCTLCMD;
457 }
458
459 static u64 kvm_mips_get_one_regs[] = {
460 KVM_REG_MIPS_R0,
461 KVM_REG_MIPS_R1,
462 KVM_REG_MIPS_R2,
463 KVM_REG_MIPS_R3,
464 KVM_REG_MIPS_R4,
465 KVM_REG_MIPS_R5,
466 KVM_REG_MIPS_R6,
467 KVM_REG_MIPS_R7,
468 KVM_REG_MIPS_R8,
469 KVM_REG_MIPS_R9,
470 KVM_REG_MIPS_R10,
471 KVM_REG_MIPS_R11,
472 KVM_REG_MIPS_R12,
473 KVM_REG_MIPS_R13,
474 KVM_REG_MIPS_R14,
475 KVM_REG_MIPS_R15,
476 KVM_REG_MIPS_R16,
477 KVM_REG_MIPS_R17,
478 KVM_REG_MIPS_R18,
479 KVM_REG_MIPS_R19,
480 KVM_REG_MIPS_R20,
481 KVM_REG_MIPS_R21,
482 KVM_REG_MIPS_R22,
483 KVM_REG_MIPS_R23,
484 KVM_REG_MIPS_R24,
485 KVM_REG_MIPS_R25,
486 KVM_REG_MIPS_R26,
487 KVM_REG_MIPS_R27,
488 KVM_REG_MIPS_R28,
489 KVM_REG_MIPS_R29,
490 KVM_REG_MIPS_R30,
491 KVM_REG_MIPS_R31,
492
493 KVM_REG_MIPS_HI,
494 KVM_REG_MIPS_LO,
495 KVM_REG_MIPS_PC,
496
497 KVM_REG_MIPS_CP0_INDEX,
498 KVM_REG_MIPS_CP0_CONTEXT,
499 KVM_REG_MIPS_CP0_USERLOCAL,
500 KVM_REG_MIPS_CP0_PAGEMASK,
501 KVM_REG_MIPS_CP0_WIRED,
502 KVM_REG_MIPS_CP0_HWRENA,
503 KVM_REG_MIPS_CP0_BADVADDR,
504 KVM_REG_MIPS_CP0_COUNT,
505 KVM_REG_MIPS_CP0_ENTRYHI,
506 KVM_REG_MIPS_CP0_COMPARE,
507 KVM_REG_MIPS_CP0_STATUS,
508 KVM_REG_MIPS_CP0_CAUSE,
509 KVM_REG_MIPS_CP0_EPC,
510 KVM_REG_MIPS_CP0_PRID,
511 KVM_REG_MIPS_CP0_CONFIG,
512 KVM_REG_MIPS_CP0_CONFIG1,
513 KVM_REG_MIPS_CP0_CONFIG2,
514 KVM_REG_MIPS_CP0_CONFIG3,
515 KVM_REG_MIPS_CP0_CONFIG4,
516 KVM_REG_MIPS_CP0_CONFIG5,
517 KVM_REG_MIPS_CP0_CONFIG7,
518 KVM_REG_MIPS_CP0_ERROREPC,
519
520 KVM_REG_MIPS_COUNT_CTL,
521 KVM_REG_MIPS_COUNT_RESUME,
522 KVM_REG_MIPS_COUNT_HZ,
523 };
524
525 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
526 const struct kvm_one_reg *reg)
527 {
528 struct mips_coproc *cop0 = vcpu->arch.cop0;
529 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
530 int ret;
531 s64 v;
532 unsigned int idx;
533
534 switch (reg->id) {
535 /* General purpose registers */
536 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
537 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
538 break;
539 case KVM_REG_MIPS_HI:
540 v = (long)vcpu->arch.hi;
541 break;
542 case KVM_REG_MIPS_LO:
543 v = (long)vcpu->arch.lo;
544 break;
545 case KVM_REG_MIPS_PC:
546 v = (long)vcpu->arch.pc;
547 break;
548
549 /* Floating point registers */
550 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
551 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
552 return -EINVAL;
553 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
554 /* Odd singles in top of even double when FR=0 */
555 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
556 v = get_fpr32(&fpu->fpr[idx], 0);
557 else
558 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
559 break;
560 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
561 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
562 return -EINVAL;
563 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
564 /* Can't access odd doubles in FR=0 mode */
565 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
566 return -EINVAL;
567 v = get_fpr64(&fpu->fpr[idx], 0);
568 break;
569 case KVM_REG_MIPS_FCR_IR:
570 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
571 return -EINVAL;
572 v = boot_cpu_data.fpu_id;
573 break;
574 case KVM_REG_MIPS_FCR_CSR:
575 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
576 return -EINVAL;
577 v = fpu->fcr31;
578 break;
579
580 /* Co-processor 0 registers */
581 case KVM_REG_MIPS_CP0_INDEX:
582 v = (long)kvm_read_c0_guest_index(cop0);
583 break;
584 case KVM_REG_MIPS_CP0_CONTEXT:
585 v = (long)kvm_read_c0_guest_context(cop0);
586 break;
587 case KVM_REG_MIPS_CP0_USERLOCAL:
588 v = (long)kvm_read_c0_guest_userlocal(cop0);
589 break;
590 case KVM_REG_MIPS_CP0_PAGEMASK:
591 v = (long)kvm_read_c0_guest_pagemask(cop0);
592 break;
593 case KVM_REG_MIPS_CP0_WIRED:
594 v = (long)kvm_read_c0_guest_wired(cop0);
595 break;
596 case KVM_REG_MIPS_CP0_HWRENA:
597 v = (long)kvm_read_c0_guest_hwrena(cop0);
598 break;
599 case KVM_REG_MIPS_CP0_BADVADDR:
600 v = (long)kvm_read_c0_guest_badvaddr(cop0);
601 break;
602 case KVM_REG_MIPS_CP0_ENTRYHI:
603 v = (long)kvm_read_c0_guest_entryhi(cop0);
604 break;
605 case KVM_REG_MIPS_CP0_COMPARE:
606 v = (long)kvm_read_c0_guest_compare(cop0);
607 break;
608 case KVM_REG_MIPS_CP0_STATUS:
609 v = (long)kvm_read_c0_guest_status(cop0);
610 break;
611 case KVM_REG_MIPS_CP0_CAUSE:
612 v = (long)kvm_read_c0_guest_cause(cop0);
613 break;
614 case KVM_REG_MIPS_CP0_EPC:
615 v = (long)kvm_read_c0_guest_epc(cop0);
616 break;
617 case KVM_REG_MIPS_CP0_PRID:
618 v = (long)kvm_read_c0_guest_prid(cop0);
619 break;
620 case KVM_REG_MIPS_CP0_CONFIG:
621 v = (long)kvm_read_c0_guest_config(cop0);
622 break;
623 case KVM_REG_MIPS_CP0_CONFIG1:
624 v = (long)kvm_read_c0_guest_config1(cop0);
625 break;
626 case KVM_REG_MIPS_CP0_CONFIG2:
627 v = (long)kvm_read_c0_guest_config2(cop0);
628 break;
629 case KVM_REG_MIPS_CP0_CONFIG3:
630 v = (long)kvm_read_c0_guest_config3(cop0);
631 break;
632 case KVM_REG_MIPS_CP0_CONFIG4:
633 v = (long)kvm_read_c0_guest_config4(cop0);
634 break;
635 case KVM_REG_MIPS_CP0_CONFIG5:
636 v = (long)kvm_read_c0_guest_config5(cop0);
637 break;
638 case KVM_REG_MIPS_CP0_CONFIG7:
639 v = (long)kvm_read_c0_guest_config7(cop0);
640 break;
641 case KVM_REG_MIPS_CP0_ERROREPC:
642 v = (long)kvm_read_c0_guest_errorepc(cop0);
643 break;
644 /* registers to be handled specially */
645 case KVM_REG_MIPS_CP0_COUNT:
646 case KVM_REG_MIPS_COUNT_CTL:
647 case KVM_REG_MIPS_COUNT_RESUME:
648 case KVM_REG_MIPS_COUNT_HZ:
649 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
650 if (ret)
651 return ret;
652 break;
653 default:
654 return -EINVAL;
655 }
656 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
657 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
658
659 return put_user(v, uaddr64);
660 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
661 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
662 u32 v32 = (u32)v;
663
664 return put_user(v32, uaddr32);
665 } else {
666 return -EINVAL;
667 }
668 }
669
670 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
671 const struct kvm_one_reg *reg)
672 {
673 struct mips_coproc *cop0 = vcpu->arch.cop0;
674 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
675 s64 v;
676 unsigned int idx;
677
678 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
679 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
680
681 if (get_user(v, uaddr64) != 0)
682 return -EFAULT;
683 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
684 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
685 s32 v32;
686
687 if (get_user(v32, uaddr32) != 0)
688 return -EFAULT;
689 v = (s64)v32;
690 } else {
691 return -EINVAL;
692 }
693
694 switch (reg->id) {
695 /* General purpose registers */
696 case KVM_REG_MIPS_R0:
697 /* Silently ignore requests to set $0 */
698 break;
699 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
700 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
701 break;
702 case KVM_REG_MIPS_HI:
703 vcpu->arch.hi = v;
704 break;
705 case KVM_REG_MIPS_LO:
706 vcpu->arch.lo = v;
707 break;
708 case KVM_REG_MIPS_PC:
709 vcpu->arch.pc = v;
710 break;
711
712 /* Floating point registers */
713 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
714 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
715 return -EINVAL;
716 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
717 /* Odd singles in top of even double when FR=0 */
718 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
719 set_fpr32(&fpu->fpr[idx], 0, v);
720 else
721 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
722 break;
723 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
724 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
725 return -EINVAL;
726 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
727 /* Can't access odd doubles in FR=0 mode */
728 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
729 return -EINVAL;
730 set_fpr64(&fpu->fpr[idx], 0, v);
731 break;
732 case KVM_REG_MIPS_FCR_IR:
733 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
734 return -EINVAL;
735 /* Read-only */
736 break;
737 case KVM_REG_MIPS_FCR_CSR:
738 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
739 return -EINVAL;
740 fpu->fcr31 = v;
741 break;
742
743 /* Co-processor 0 registers */
744 case KVM_REG_MIPS_CP0_INDEX:
745 kvm_write_c0_guest_index(cop0, v);
746 break;
747 case KVM_REG_MIPS_CP0_CONTEXT:
748 kvm_write_c0_guest_context(cop0, v);
749 break;
750 case KVM_REG_MIPS_CP0_USERLOCAL:
751 kvm_write_c0_guest_userlocal(cop0, v);
752 break;
753 case KVM_REG_MIPS_CP0_PAGEMASK:
754 kvm_write_c0_guest_pagemask(cop0, v);
755 break;
756 case KVM_REG_MIPS_CP0_WIRED:
757 kvm_write_c0_guest_wired(cop0, v);
758 break;
759 case KVM_REG_MIPS_CP0_HWRENA:
760 kvm_write_c0_guest_hwrena(cop0, v);
761 break;
762 case KVM_REG_MIPS_CP0_BADVADDR:
763 kvm_write_c0_guest_badvaddr(cop0, v);
764 break;
765 case KVM_REG_MIPS_CP0_ENTRYHI:
766 kvm_write_c0_guest_entryhi(cop0, v);
767 break;
768 case KVM_REG_MIPS_CP0_STATUS:
769 kvm_write_c0_guest_status(cop0, v);
770 break;
771 case KVM_REG_MIPS_CP0_EPC:
772 kvm_write_c0_guest_epc(cop0, v);
773 break;
774 case KVM_REG_MIPS_CP0_PRID:
775 kvm_write_c0_guest_prid(cop0, v);
776 break;
777 case KVM_REG_MIPS_CP0_ERROREPC:
778 kvm_write_c0_guest_errorepc(cop0, v);
779 break;
780 /* registers to be handled specially */
781 case KVM_REG_MIPS_CP0_COUNT:
782 case KVM_REG_MIPS_CP0_COMPARE:
783 case KVM_REG_MIPS_CP0_CAUSE:
784 case KVM_REG_MIPS_CP0_CONFIG:
785 case KVM_REG_MIPS_CP0_CONFIG1:
786 case KVM_REG_MIPS_CP0_CONFIG2:
787 case KVM_REG_MIPS_CP0_CONFIG3:
788 case KVM_REG_MIPS_CP0_CONFIG4:
789 case KVM_REG_MIPS_CP0_CONFIG5:
790 case KVM_REG_MIPS_COUNT_CTL:
791 case KVM_REG_MIPS_COUNT_RESUME:
792 case KVM_REG_MIPS_COUNT_HZ:
793 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
794 default:
795 return -EINVAL;
796 }
797 return 0;
798 }
799
800 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
801 unsigned long arg)
802 {
803 struct kvm_vcpu *vcpu = filp->private_data;
804 void __user *argp = (void __user *)arg;
805 long r;
806
807 switch (ioctl) {
808 case KVM_SET_ONE_REG:
809 case KVM_GET_ONE_REG: {
810 struct kvm_one_reg reg;
811
812 if (copy_from_user(&reg, argp, sizeof(reg)))
813 return -EFAULT;
814 if (ioctl == KVM_SET_ONE_REG)
815 return kvm_mips_set_reg(vcpu, &reg);
816 else
817 return kvm_mips_get_reg(vcpu, &reg);
818 }
819 case KVM_GET_REG_LIST: {
820 struct kvm_reg_list __user *user_list = argp;
821 u64 __user *reg_dest;
822 struct kvm_reg_list reg_list;
823 unsigned n;
824
825 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
826 return -EFAULT;
827 n = reg_list.n;
828 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
829 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
830 return -EFAULT;
831 if (n < reg_list.n)
832 return -E2BIG;
833 reg_dest = user_list->reg;
834 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
835 sizeof(kvm_mips_get_one_regs)))
836 return -EFAULT;
837 return 0;
838 }
839 case KVM_NMI:
840 /* Treat the NMI as a CPU reset */
841 r = kvm_mips_reset_vcpu(vcpu);
842 break;
843 case KVM_INTERRUPT:
844 {
845 struct kvm_mips_interrupt irq;
846
847 r = -EFAULT;
848 if (copy_from_user(&irq, argp, sizeof(irq)))
849 goto out;
850
851 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
852 irq.irq);
853
854 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
855 break;
856 }
857 default:
858 r = -ENOIOCTLCMD;
859 }
860
861 out:
862 return r;
863 }
864
865 /* Get (and clear) the dirty memory log for a memory slot. */
866 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
867 {
868 struct kvm_memory_slot *memslot;
869 unsigned long ga, ga_end;
870 int is_dirty = 0;
871 int r;
872 unsigned long n;
873
874 mutex_lock(&kvm->slots_lock);
875
876 r = kvm_get_dirty_log(kvm, log, &is_dirty);
877 if (r)
878 goto out;
879
880 /* If nothing is dirty, don't bother messing with page tables. */
881 if (is_dirty) {
882 memslot = &kvm->memslots->memslots[log->slot];
883
884 ga = memslot->base_gfn << PAGE_SHIFT;
885 ga_end = ga + (memslot->npages << PAGE_SHIFT);
886
887 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
888 ga_end);
889
890 n = kvm_dirty_bitmap_bytes(memslot);
891 memset(memslot->dirty_bitmap, 0, n);
892 }
893
894 r = 0;
895 out:
896 mutex_unlock(&kvm->slots_lock);
897 return r;
898
899 }
900
901 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
902 {
903 long r;
904
905 switch (ioctl) {
906 default:
907 r = -ENOIOCTLCMD;
908 }
909
910 return r;
911 }
912
913 int kvm_arch_init(void *opaque)
914 {
915 if (kvm_mips_callbacks) {
916 kvm_err("kvm: module already exists\n");
917 return -EEXIST;
918 }
919
920 return kvm_mips_emulation_init(&kvm_mips_callbacks);
921 }
922
923 void kvm_arch_exit(void)
924 {
925 kvm_mips_callbacks = NULL;
926 }
927
928 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
929 struct kvm_sregs *sregs)
930 {
931 return -ENOIOCTLCMD;
932 }
933
934 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
935 struct kvm_sregs *sregs)
936 {
937 return -ENOIOCTLCMD;
938 }
939
940 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
941 {
942 }
943
944 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
945 {
946 return -ENOIOCTLCMD;
947 }
948
949 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
950 {
951 return -ENOIOCTLCMD;
952 }
953
954 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
955 {
956 return VM_FAULT_SIGBUS;
957 }
958
959 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
960 {
961 int r;
962
963 switch (ext) {
964 case KVM_CAP_ONE_REG:
965 r = 1;
966 break;
967 case KVM_CAP_COALESCED_MMIO:
968 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
969 break;
970 default:
971 r = 0;
972 break;
973 }
974 return r;
975 }
976
977 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
978 {
979 return kvm_mips_pending_timer(vcpu);
980 }
981
982 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
983 {
984 int i;
985 struct mips_coproc *cop0;
986
987 if (!vcpu)
988 return -1;
989
990 kvm_debug("VCPU Register Dump:\n");
991 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
992 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
993
994 for (i = 0; i < 32; i += 4) {
995 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
996 vcpu->arch.gprs[i],
997 vcpu->arch.gprs[i + 1],
998 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
999 }
1000 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1001 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1002
1003 cop0 = vcpu->arch.cop0;
1004 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1005 kvm_read_c0_guest_status(cop0),
1006 kvm_read_c0_guest_cause(cop0));
1007
1008 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1009
1010 return 0;
1011 }
1012
1013 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1014 {
1015 int i;
1016
1017 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1018 vcpu->arch.gprs[i] = regs->gpr[i];
1019 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1020 vcpu->arch.hi = regs->hi;
1021 vcpu->arch.lo = regs->lo;
1022 vcpu->arch.pc = regs->pc;
1023
1024 return 0;
1025 }
1026
1027 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1028 {
1029 int i;
1030
1031 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1032 regs->gpr[i] = vcpu->arch.gprs[i];
1033
1034 regs->hi = vcpu->arch.hi;
1035 regs->lo = vcpu->arch.lo;
1036 regs->pc = vcpu->arch.pc;
1037
1038 return 0;
1039 }
1040
1041 static void kvm_mips_comparecount_func(unsigned long data)
1042 {
1043 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1044
1045 kvm_mips_callbacks->queue_timer_int(vcpu);
1046
1047 vcpu->arch.wait = 0;
1048 if (waitqueue_active(&vcpu->wq))
1049 wake_up_interruptible(&vcpu->wq);
1050 }
1051
1052 /* low level hrtimer wake routine */
1053 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1054 {
1055 struct kvm_vcpu *vcpu;
1056
1057 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1058 kvm_mips_comparecount_func((unsigned long) vcpu);
1059 return kvm_mips_count_timeout(vcpu);
1060 }
1061
1062 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1063 {
1064 kvm_mips_callbacks->vcpu_init(vcpu);
1065 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1066 HRTIMER_MODE_REL);
1067 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1068 return 0;
1069 }
1070
1071 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1072 struct kvm_translation *tr)
1073 {
1074 return 0;
1075 }
1076
1077 /* Initial guest state */
1078 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1079 {
1080 return kvm_mips_callbacks->vcpu_setup(vcpu);
1081 }
1082
1083 static void kvm_mips_set_c0_status(void)
1084 {
1085 uint32_t status = read_c0_status();
1086
1087 if (cpu_has_dsp)
1088 status |= (ST0_MX);
1089
1090 write_c0_status(status);
1091 ehb();
1092 }
1093
1094 /*
1095 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1096 */
1097 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1098 {
1099 uint32_t cause = vcpu->arch.host_cp0_cause;
1100 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1101 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1102 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1103 enum emulation_result er = EMULATE_DONE;
1104 int ret = RESUME_GUEST;
1105
1106 /* re-enable HTW before enabling interrupts */
1107 htw_start();
1108
1109 /* Set a default exit reason */
1110 run->exit_reason = KVM_EXIT_UNKNOWN;
1111 run->ready_for_interrupt_injection = 1;
1112
1113 /*
1114 * Set the appropriate status bits based on host CPU features,
1115 * before we hit the scheduler
1116 */
1117 kvm_mips_set_c0_status();
1118
1119 local_irq_enable();
1120
1121 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1122 cause, opc, run, vcpu);
1123
1124 /*
1125 * Do a privilege check, if in UM most of these exit conditions end up
1126 * causing an exception to be delivered to the Guest Kernel
1127 */
1128 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1129 if (er == EMULATE_PRIV_FAIL) {
1130 goto skip_emul;
1131 } else if (er == EMULATE_FAIL) {
1132 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1133 ret = RESUME_HOST;
1134 goto skip_emul;
1135 }
1136
1137 switch (exccode) {
1138 case T_INT:
1139 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
1140
1141 ++vcpu->stat.int_exits;
1142 trace_kvm_exit(vcpu, INT_EXITS);
1143
1144 if (need_resched())
1145 cond_resched();
1146
1147 ret = RESUME_GUEST;
1148 break;
1149
1150 case T_COP_UNUSABLE:
1151 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
1152
1153 ++vcpu->stat.cop_unusable_exits;
1154 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1155 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1156 /* XXXKYMA: Might need to return to user space */
1157 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1158 ret = RESUME_HOST;
1159 break;
1160
1161 case T_TLB_MOD:
1162 ++vcpu->stat.tlbmod_exits;
1163 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1164 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1165 break;
1166
1167 case T_TLB_ST_MISS:
1168 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1169 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1170 badvaddr);
1171
1172 ++vcpu->stat.tlbmiss_st_exits;
1173 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1174 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1175 break;
1176
1177 case T_TLB_LD_MISS:
1178 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1179 cause, opc, badvaddr);
1180
1181 ++vcpu->stat.tlbmiss_ld_exits;
1182 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1183 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1184 break;
1185
1186 case T_ADDR_ERR_ST:
1187 ++vcpu->stat.addrerr_st_exits;
1188 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1189 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1190 break;
1191
1192 case T_ADDR_ERR_LD:
1193 ++vcpu->stat.addrerr_ld_exits;
1194 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1195 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1196 break;
1197
1198 case T_SYSCALL:
1199 ++vcpu->stat.syscall_exits;
1200 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1201 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1202 break;
1203
1204 case T_RES_INST:
1205 ++vcpu->stat.resvd_inst_exits;
1206 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1207 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1208 break;
1209
1210 case T_BREAK:
1211 ++vcpu->stat.break_inst_exits;
1212 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1213 ret = kvm_mips_callbacks->handle_break(vcpu);
1214 break;
1215
1216 case T_TRAP:
1217 ++vcpu->stat.trap_inst_exits;
1218 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1219 ret = kvm_mips_callbacks->handle_trap(vcpu);
1220 break;
1221
1222 case T_FPE:
1223 ++vcpu->stat.fpe_exits;
1224 trace_kvm_exit(vcpu, FPE_EXITS);
1225 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1226 break;
1227
1228 case T_MSADIS:
1229 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1230 break;
1231
1232 default:
1233 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1234 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1235 kvm_read_c0_guest_status(vcpu->arch.cop0));
1236 kvm_arch_vcpu_dump_regs(vcpu);
1237 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1238 ret = RESUME_HOST;
1239 break;
1240
1241 }
1242
1243 skip_emul:
1244 local_irq_disable();
1245
1246 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1247 kvm_mips_deliver_interrupts(vcpu, cause);
1248
1249 if (!(ret & RESUME_HOST)) {
1250 /* Only check for signals if not already exiting to userspace */
1251 if (signal_pending(current)) {
1252 run->exit_reason = KVM_EXIT_INTR;
1253 ret = (-EINTR << 2) | RESUME_HOST;
1254 ++vcpu->stat.signal_exits;
1255 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1256 }
1257 }
1258
1259 if (ret == RESUME_GUEST) {
1260 /*
1261 * If FPU is enabled (i.e. the guest's FPU context is live),
1262 * restore FCR31.
1263 *
1264 * This should be before returning to the guest exception
1265 * vector, as it may well cause an FP exception if there are
1266 * pending exception bits unmasked. (see
1267 * kvm_mips_csr_die_notifier() for how that is handled).
1268 */
1269 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1270 read_c0_status() & ST0_CU1)
1271 __kvm_restore_fcsr(&vcpu->arch);
1272 }
1273
1274 /* Disable HTW before returning to guest or host */
1275 htw_stop();
1276
1277 return ret;
1278 }
1279
1280 /* Enable FPU for guest and restore context */
1281 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1282 {
1283 struct mips_coproc *cop0 = vcpu->arch.cop0;
1284 unsigned int sr, cfg5;
1285
1286 preempt_disable();
1287
1288 /*
1289 * Enable FPU for guest
1290 * We set FR and FRE according to guest context
1291 */
1292 sr = kvm_read_c0_guest_status(cop0);
1293 change_c0_status(ST0_CU1 | ST0_FR, sr);
1294 if (cpu_has_fre) {
1295 cfg5 = kvm_read_c0_guest_config5(cop0);
1296 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1297 }
1298 enable_fpu_hazard();
1299
1300 /* If guest FPU state not active, restore it now */
1301 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1302 __kvm_restore_fpu(&vcpu->arch);
1303 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1304 }
1305
1306 preempt_enable();
1307 }
1308
1309 /* Drop FPU without saving it */
1310 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1311 {
1312 preempt_disable();
1313 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1314 clear_c0_status(ST0_CU1 | ST0_FR);
1315 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1316 }
1317 preempt_enable();
1318 }
1319
1320 /* Save and disable FPU */
1321 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1322 {
1323 /*
1324 * FPU gets disabled in root context (hardware) when it is disabled in
1325 * guest context (software), but the register state in the hardware may
1326 * still be in use. This is why we explicitly re-enable the hardware
1327 * before saving.
1328 */
1329
1330 preempt_disable();
1331 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1332 set_c0_status(ST0_CU1);
1333 enable_fpu_hazard();
1334
1335 __kvm_save_fpu(&vcpu->arch);
1336 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1337
1338 /* Disable FPU */
1339 clear_c0_status(ST0_CU1 | ST0_FR);
1340 }
1341 preempt_enable();
1342 }
1343
1344 /*
1345 * Step over a specific ctc1 to FCSR which is used to restore guest FCSR state
1346 * and may trigger a "harmless" FP exception if cause bits are set in the value
1347 * being written.
1348 */
1349 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1350 unsigned long cmd, void *ptr)
1351 {
1352 struct die_args *args = (struct die_args *)ptr;
1353 struct pt_regs *regs = args->regs;
1354 unsigned long pc;
1355
1356 /* Only interested in FPE */
1357 if (cmd != DIE_FP)
1358 return NOTIFY_DONE;
1359
1360 /* Return immediately if guest context isn't active */
1361 if (!(current->flags & PF_VCPU))
1362 return NOTIFY_DONE;
1363
1364 /* Should never get here from user mode */
1365 BUG_ON(user_mode(regs));
1366
1367 pc = instruction_pointer(regs);
1368 switch (cmd) {
1369 case DIE_FP:
1370 /* match 2nd instruction in __kvm_restore_fcsr */
1371 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1372 return NOTIFY_DONE;
1373 break;
1374 }
1375
1376 /* Move PC forward a little and continue executing */
1377 instruction_pointer(regs) += 4;
1378
1379 return NOTIFY_STOP;
1380 }
1381
1382 static struct notifier_block kvm_mips_csr_die_notifier = {
1383 .notifier_call = kvm_mips_csr_die_notify,
1384 };
1385
1386 int __init kvm_mips_init(void)
1387 {
1388 int ret;
1389
1390 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1391
1392 if (ret)
1393 return ret;
1394
1395 register_die_notifier(&kvm_mips_csr_die_notifier);
1396
1397 /*
1398 * On MIPS, kernel modules are executed from "mapped space", which
1399 * requires TLBs. The TLB handling code is statically linked with
1400 * the rest of the kernel (tlb.c) to avoid the possibility of
1401 * double faulting. The issue is that the TLB code references
1402 * routines that are part of the the KVM module, which are only
1403 * available once the module is loaded.
1404 */
1405 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1406 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1407 kvm_mips_is_error_pfn = is_error_pfn;
1408
1409 return 0;
1410 }
1411
1412 void __exit kvm_mips_exit(void)
1413 {
1414 kvm_exit();
1415
1416 kvm_mips_gfn_to_pfn = NULL;
1417 kvm_mips_release_pfn_clean = NULL;
1418 kvm_mips_is_error_pfn = NULL;
1419
1420 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1421 }
1422
1423 module_init(kvm_mips_init);
1424 module_exit(kvm_mips_exit);
1425
1426 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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