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MIPS; KVM: Convert exception entry to uasm
[deliverable/linux.git] / arch / mips / kvm / mips.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <asm/fpu.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25
26 #include <linux/kvm_host.h>
27
28 #include "interrupt.h"
29 #include "commpage.h"
30
31 #define CREATE_TRACE_POINTS
32 #include "trace.h"
33
34 #ifndef VECTORSPACING
35 #define VECTORSPACING 0x100 /* for EI/VI mode */
36 #endif
37
38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
39 struct kvm_stats_debugfs_item debugfs_entries[] = {
40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
62 {NULL}
63 };
64
65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
66 {
67 int i;
68
69 for_each_possible_cpu(i) {
70 vcpu->arch.guest_kernel_asid[i] = 0;
71 vcpu->arch.guest_user_asid[i] = 0;
72 }
73
74 return 0;
75 }
76
77 /*
78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
79 * Config7, so we are "runnable" if interrupts are pending
80 */
81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
82 {
83 return !!(vcpu->arch.pending_exceptions);
84 }
85
86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
87 {
88 return 1;
89 }
90
91 int kvm_arch_hardware_enable(void)
92 {
93 return 0;
94 }
95
96 int kvm_arch_hardware_setup(void)
97 {
98 return 0;
99 }
100
101 void kvm_arch_check_processor_compat(void *rtn)
102 {
103 *(int *)rtn = 0;
104 }
105
106 static void kvm_mips_init_tlbs(struct kvm *kvm)
107 {
108 unsigned long wired;
109
110 /*
111 * Add a wired entry to the TLB, it is used to map the commpage to
112 * the Guest kernel
113 */
114 wired = read_c0_wired();
115 write_c0_wired(wired + 1);
116 mtc0_tlbw_hazard();
117 kvm->arch.commpage_tlb = wired;
118
119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
120 kvm->arch.commpage_tlb);
121 }
122
123 static void kvm_mips_init_vm_percpu(void *arg)
124 {
125 struct kvm *kvm = (struct kvm *)arg;
126
127 kvm_mips_init_tlbs(kvm);
128 kvm_mips_callbacks->vm_init(kvm);
129
130 }
131
132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
133 {
134 if (atomic_inc_return(&kvm_mips_instance) == 1) {
135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
136 __func__);
137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
138 }
139
140 return 0;
141 }
142
143 void kvm_mips_free_vcpus(struct kvm *kvm)
144 {
145 unsigned int i;
146 struct kvm_vcpu *vcpu;
147
148 /* Put the pages we reserved for the guest pmap */
149 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
150 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
151 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
152 }
153 kfree(kvm->arch.guest_pmap);
154
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 kvm_arch_vcpu_free(vcpu);
157 }
158
159 mutex_lock(&kvm->lock);
160
161 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
162 kvm->vcpus[i] = NULL;
163
164 atomic_set(&kvm->online_vcpus, 0);
165
166 mutex_unlock(&kvm->lock);
167 }
168
169 static void kvm_mips_uninit_tlbs(void *arg)
170 {
171 /* Restore wired count */
172 write_c0_wired(0);
173 mtc0_tlbw_hazard();
174 /* Clear out all the TLBs */
175 kvm_local_flush_tlb_all();
176 }
177
178 void kvm_arch_destroy_vm(struct kvm *kvm)
179 {
180 kvm_mips_free_vcpus(kvm);
181
182 /* If this is the last instance, restore wired count */
183 if (atomic_dec_return(&kvm_mips_instance) == 0) {
184 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
185 __func__);
186 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
187 }
188 }
189
190 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
191 unsigned long arg)
192 {
193 return -ENOIOCTLCMD;
194 }
195
196 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
197 unsigned long npages)
198 {
199 return 0;
200 }
201
202 int kvm_arch_prepare_memory_region(struct kvm *kvm,
203 struct kvm_memory_slot *memslot,
204 const struct kvm_userspace_memory_region *mem,
205 enum kvm_mr_change change)
206 {
207 return 0;
208 }
209
210 void kvm_arch_commit_memory_region(struct kvm *kvm,
211 const struct kvm_userspace_memory_region *mem,
212 const struct kvm_memory_slot *old,
213 const struct kvm_memory_slot *new,
214 enum kvm_mr_change change)
215 {
216 unsigned long npages = 0;
217 int i;
218
219 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
220 __func__, kvm, mem->slot, mem->guest_phys_addr,
221 mem->memory_size, mem->userspace_addr);
222
223 /* Setup Guest PMAP table */
224 if (!kvm->arch.guest_pmap) {
225 if (mem->slot == 0)
226 npages = mem->memory_size >> PAGE_SHIFT;
227
228 if (npages) {
229 kvm->arch.guest_pmap_npages = npages;
230 kvm->arch.guest_pmap =
231 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
232
233 if (!kvm->arch.guest_pmap) {
234 kvm_err("Failed to allocate guest PMAP\n");
235 return;
236 }
237
238 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
239 npages, kvm->arch.guest_pmap);
240
241 /* Now setup the page table */
242 for (i = 0; i < npages; i++)
243 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
244 }
245 }
246 }
247
248 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
249 {
250 int err, size;
251 void *gebase, *p;
252 int i;
253
254 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
255
256 if (!vcpu) {
257 err = -ENOMEM;
258 goto out;
259 }
260
261 err = kvm_vcpu_init(vcpu, kvm, id);
262
263 if (err)
264 goto out_free_cpu;
265
266 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
267
268 /*
269 * Allocate space for host mode exception handlers that handle
270 * guest mode exits
271 */
272 if (cpu_has_veic || cpu_has_vint)
273 size = 0x200 + VECTORSPACING * 64;
274 else
275 size = 0x4000;
276
277 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
278
279 if (!gebase) {
280 err = -ENOMEM;
281 goto out_uninit_cpu;
282 }
283 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
284 ALIGN(size, PAGE_SIZE), gebase);
285
286 /* Save new ebase */
287 vcpu->arch.guest_ebase = gebase;
288
289 /* Build guest exception vectors dynamically in unmapped memory */
290
291 /* TLB Refill, EXL = 0 */
292 kvm_mips_build_exception(gebase);
293
294 /* General Exception Entry point */
295 kvm_mips_build_exception(gebase + 0x180);
296
297 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
298 for (i = 0; i < 8; i++) {
299 kvm_debug("L1 Vectored handler @ %p\n",
300 gebase + 0x200 + (i * VECTORSPACING));
301 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING);
302 }
303
304 /* General exit handler */
305 p = gebase + 0x2000;
306 p = kvm_mips_build_exit(p);
307
308 /* Guest entry routine */
309 vcpu->arch.vcpu_run = p;
310 p = kvm_mips_build_vcpu_run(p);
311
312 /* Invalidate the icache for these ranges */
313 local_flush_icache_range((unsigned long)gebase,
314 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
315
316 /*
317 * Allocate comm page for guest kernel, a TLB will be reserved for
318 * mapping GVA @ 0xFFFF8000 to this page
319 */
320 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
321
322 if (!vcpu->arch.kseg0_commpage) {
323 err = -ENOMEM;
324 goto out_free_gebase;
325 }
326
327 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
328 kvm_mips_commpage_init(vcpu);
329
330 /* Init */
331 vcpu->arch.last_sched_cpu = -1;
332
333 /* Start off the timer */
334 kvm_mips_init_count(vcpu);
335
336 return vcpu;
337
338 out_free_gebase:
339 kfree(gebase);
340
341 out_uninit_cpu:
342 kvm_vcpu_uninit(vcpu);
343
344 out_free_cpu:
345 kfree(vcpu);
346
347 out:
348 return ERR_PTR(err);
349 }
350
351 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
352 {
353 hrtimer_cancel(&vcpu->arch.comparecount_timer);
354
355 kvm_vcpu_uninit(vcpu);
356
357 kvm_mips_dump_stats(vcpu);
358
359 kfree(vcpu->arch.guest_ebase);
360 kfree(vcpu->arch.kseg0_commpage);
361 kfree(vcpu);
362 }
363
364 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
365 {
366 kvm_arch_vcpu_free(vcpu);
367 }
368
369 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
370 struct kvm_guest_debug *dbg)
371 {
372 return -ENOIOCTLCMD;
373 }
374
375 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
376 {
377 int r = 0;
378 sigset_t sigsaved;
379
380 if (vcpu->sigset_active)
381 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
382
383 if (vcpu->mmio_needed) {
384 if (!vcpu->mmio_is_write)
385 kvm_mips_complete_mmio_load(vcpu, run);
386 vcpu->mmio_needed = 0;
387 }
388
389 lose_fpu(1);
390
391 local_irq_disable();
392 /* Check if we have any exceptions/interrupts pending */
393 kvm_mips_deliver_interrupts(vcpu,
394 kvm_read_c0_guest_cause(vcpu->arch.cop0));
395
396 guest_enter_irqoff();
397
398 /* Disable hardware page table walking while in guest */
399 htw_stop();
400
401 trace_kvm_enter(vcpu);
402 r = vcpu->arch.vcpu_run(run, vcpu);
403 trace_kvm_out(vcpu);
404
405 /* Re-enable HTW before enabling interrupts */
406 htw_start();
407
408 guest_exit_irqoff();
409 local_irq_enable();
410
411 if (vcpu->sigset_active)
412 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
413
414 return r;
415 }
416
417 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
418 struct kvm_mips_interrupt *irq)
419 {
420 int intr = (int)irq->irq;
421 struct kvm_vcpu *dvcpu = NULL;
422
423 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
424 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
425 (int)intr);
426
427 if (irq->cpu == -1)
428 dvcpu = vcpu;
429 else
430 dvcpu = vcpu->kvm->vcpus[irq->cpu];
431
432 if (intr == 2 || intr == 3 || intr == 4) {
433 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
434
435 } else if (intr == -2 || intr == -3 || intr == -4) {
436 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
437 } else {
438 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
439 irq->cpu, irq->irq);
440 return -EINVAL;
441 }
442
443 dvcpu->arch.wait = 0;
444
445 if (swait_active(&dvcpu->wq))
446 swake_up(&dvcpu->wq);
447
448 return 0;
449 }
450
451 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
452 struct kvm_mp_state *mp_state)
453 {
454 return -ENOIOCTLCMD;
455 }
456
457 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
458 struct kvm_mp_state *mp_state)
459 {
460 return -ENOIOCTLCMD;
461 }
462
463 static u64 kvm_mips_get_one_regs[] = {
464 KVM_REG_MIPS_R0,
465 KVM_REG_MIPS_R1,
466 KVM_REG_MIPS_R2,
467 KVM_REG_MIPS_R3,
468 KVM_REG_MIPS_R4,
469 KVM_REG_MIPS_R5,
470 KVM_REG_MIPS_R6,
471 KVM_REG_MIPS_R7,
472 KVM_REG_MIPS_R8,
473 KVM_REG_MIPS_R9,
474 KVM_REG_MIPS_R10,
475 KVM_REG_MIPS_R11,
476 KVM_REG_MIPS_R12,
477 KVM_REG_MIPS_R13,
478 KVM_REG_MIPS_R14,
479 KVM_REG_MIPS_R15,
480 KVM_REG_MIPS_R16,
481 KVM_REG_MIPS_R17,
482 KVM_REG_MIPS_R18,
483 KVM_REG_MIPS_R19,
484 KVM_REG_MIPS_R20,
485 KVM_REG_MIPS_R21,
486 KVM_REG_MIPS_R22,
487 KVM_REG_MIPS_R23,
488 KVM_REG_MIPS_R24,
489 KVM_REG_MIPS_R25,
490 KVM_REG_MIPS_R26,
491 KVM_REG_MIPS_R27,
492 KVM_REG_MIPS_R28,
493 KVM_REG_MIPS_R29,
494 KVM_REG_MIPS_R30,
495 KVM_REG_MIPS_R31,
496
497 KVM_REG_MIPS_HI,
498 KVM_REG_MIPS_LO,
499 KVM_REG_MIPS_PC,
500
501 KVM_REG_MIPS_CP0_INDEX,
502 KVM_REG_MIPS_CP0_CONTEXT,
503 KVM_REG_MIPS_CP0_USERLOCAL,
504 KVM_REG_MIPS_CP0_PAGEMASK,
505 KVM_REG_MIPS_CP0_WIRED,
506 KVM_REG_MIPS_CP0_HWRENA,
507 KVM_REG_MIPS_CP0_BADVADDR,
508 KVM_REG_MIPS_CP0_COUNT,
509 KVM_REG_MIPS_CP0_ENTRYHI,
510 KVM_REG_MIPS_CP0_COMPARE,
511 KVM_REG_MIPS_CP0_STATUS,
512 KVM_REG_MIPS_CP0_CAUSE,
513 KVM_REG_MIPS_CP0_EPC,
514 KVM_REG_MIPS_CP0_PRID,
515 KVM_REG_MIPS_CP0_CONFIG,
516 KVM_REG_MIPS_CP0_CONFIG1,
517 KVM_REG_MIPS_CP0_CONFIG2,
518 KVM_REG_MIPS_CP0_CONFIG3,
519 KVM_REG_MIPS_CP0_CONFIG4,
520 KVM_REG_MIPS_CP0_CONFIG5,
521 KVM_REG_MIPS_CP0_CONFIG7,
522 KVM_REG_MIPS_CP0_ERROREPC,
523
524 KVM_REG_MIPS_COUNT_CTL,
525 KVM_REG_MIPS_COUNT_RESUME,
526 KVM_REG_MIPS_COUNT_HZ,
527 };
528
529 static u64 kvm_mips_get_one_regs_fpu[] = {
530 KVM_REG_MIPS_FCR_IR,
531 KVM_REG_MIPS_FCR_CSR,
532 };
533
534 static u64 kvm_mips_get_one_regs_msa[] = {
535 KVM_REG_MIPS_MSA_IR,
536 KVM_REG_MIPS_MSA_CSR,
537 };
538
539 static u64 kvm_mips_get_one_regs_kscratch[] = {
540 KVM_REG_MIPS_CP0_KSCRATCH1,
541 KVM_REG_MIPS_CP0_KSCRATCH2,
542 KVM_REG_MIPS_CP0_KSCRATCH3,
543 KVM_REG_MIPS_CP0_KSCRATCH4,
544 KVM_REG_MIPS_CP0_KSCRATCH5,
545 KVM_REG_MIPS_CP0_KSCRATCH6,
546 };
547
548 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
549 {
550 unsigned long ret;
551
552 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
553 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
554 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
555 /* odd doubles */
556 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
557 ret += 16;
558 }
559 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
560 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
561 ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
562 ret += kvm_mips_callbacks->num_regs(vcpu);
563
564 return ret;
565 }
566
567 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
568 {
569 u64 index;
570 unsigned int i;
571
572 if (copy_to_user(indices, kvm_mips_get_one_regs,
573 sizeof(kvm_mips_get_one_regs)))
574 return -EFAULT;
575 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
576
577 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
578 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
579 sizeof(kvm_mips_get_one_regs_fpu)))
580 return -EFAULT;
581 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
582
583 for (i = 0; i < 32; ++i) {
584 index = KVM_REG_MIPS_FPR_32(i);
585 if (copy_to_user(indices, &index, sizeof(index)))
586 return -EFAULT;
587 ++indices;
588
589 /* skip odd doubles if no F64 */
590 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
591 continue;
592
593 index = KVM_REG_MIPS_FPR_64(i);
594 if (copy_to_user(indices, &index, sizeof(index)))
595 return -EFAULT;
596 ++indices;
597 }
598 }
599
600 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
601 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
602 sizeof(kvm_mips_get_one_regs_msa)))
603 return -EFAULT;
604 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
605
606 for (i = 0; i < 32; ++i) {
607 index = KVM_REG_MIPS_VEC_128(i);
608 if (copy_to_user(indices, &index, sizeof(index)))
609 return -EFAULT;
610 ++indices;
611 }
612 }
613
614 for (i = 0; i < 6; ++i) {
615 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
616 continue;
617
618 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
619 sizeof(kvm_mips_get_one_regs_kscratch[i])))
620 return -EFAULT;
621 ++indices;
622 }
623
624 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
625 }
626
627 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
628 const struct kvm_one_reg *reg)
629 {
630 struct mips_coproc *cop0 = vcpu->arch.cop0;
631 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
632 int ret;
633 s64 v;
634 s64 vs[2];
635 unsigned int idx;
636
637 switch (reg->id) {
638 /* General purpose registers */
639 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
640 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
641 break;
642 case KVM_REG_MIPS_HI:
643 v = (long)vcpu->arch.hi;
644 break;
645 case KVM_REG_MIPS_LO:
646 v = (long)vcpu->arch.lo;
647 break;
648 case KVM_REG_MIPS_PC:
649 v = (long)vcpu->arch.pc;
650 break;
651
652 /* Floating point registers */
653 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
654 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
655 return -EINVAL;
656 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
657 /* Odd singles in top of even double when FR=0 */
658 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
659 v = get_fpr32(&fpu->fpr[idx], 0);
660 else
661 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
662 break;
663 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
664 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
665 return -EINVAL;
666 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
667 /* Can't access odd doubles in FR=0 mode */
668 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
669 return -EINVAL;
670 v = get_fpr64(&fpu->fpr[idx], 0);
671 break;
672 case KVM_REG_MIPS_FCR_IR:
673 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
674 return -EINVAL;
675 v = boot_cpu_data.fpu_id;
676 break;
677 case KVM_REG_MIPS_FCR_CSR:
678 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
679 return -EINVAL;
680 v = fpu->fcr31;
681 break;
682
683 /* MIPS SIMD Architecture (MSA) registers */
684 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
685 if (!kvm_mips_guest_has_msa(&vcpu->arch))
686 return -EINVAL;
687 /* Can't access MSA registers in FR=0 mode */
688 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
689 return -EINVAL;
690 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
691 #ifdef CONFIG_CPU_LITTLE_ENDIAN
692 /* least significant byte first */
693 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
694 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
695 #else
696 /* most significant byte first */
697 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
698 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
699 #endif
700 break;
701 case KVM_REG_MIPS_MSA_IR:
702 if (!kvm_mips_guest_has_msa(&vcpu->arch))
703 return -EINVAL;
704 v = boot_cpu_data.msa_id;
705 break;
706 case KVM_REG_MIPS_MSA_CSR:
707 if (!kvm_mips_guest_has_msa(&vcpu->arch))
708 return -EINVAL;
709 v = fpu->msacsr;
710 break;
711
712 /* Co-processor 0 registers */
713 case KVM_REG_MIPS_CP0_INDEX:
714 v = (long)kvm_read_c0_guest_index(cop0);
715 break;
716 case KVM_REG_MIPS_CP0_CONTEXT:
717 v = (long)kvm_read_c0_guest_context(cop0);
718 break;
719 case KVM_REG_MIPS_CP0_USERLOCAL:
720 v = (long)kvm_read_c0_guest_userlocal(cop0);
721 break;
722 case KVM_REG_MIPS_CP0_PAGEMASK:
723 v = (long)kvm_read_c0_guest_pagemask(cop0);
724 break;
725 case KVM_REG_MIPS_CP0_WIRED:
726 v = (long)kvm_read_c0_guest_wired(cop0);
727 break;
728 case KVM_REG_MIPS_CP0_HWRENA:
729 v = (long)kvm_read_c0_guest_hwrena(cop0);
730 break;
731 case KVM_REG_MIPS_CP0_BADVADDR:
732 v = (long)kvm_read_c0_guest_badvaddr(cop0);
733 break;
734 case KVM_REG_MIPS_CP0_ENTRYHI:
735 v = (long)kvm_read_c0_guest_entryhi(cop0);
736 break;
737 case KVM_REG_MIPS_CP0_COMPARE:
738 v = (long)kvm_read_c0_guest_compare(cop0);
739 break;
740 case KVM_REG_MIPS_CP0_STATUS:
741 v = (long)kvm_read_c0_guest_status(cop0);
742 break;
743 case KVM_REG_MIPS_CP0_CAUSE:
744 v = (long)kvm_read_c0_guest_cause(cop0);
745 break;
746 case KVM_REG_MIPS_CP0_EPC:
747 v = (long)kvm_read_c0_guest_epc(cop0);
748 break;
749 case KVM_REG_MIPS_CP0_PRID:
750 v = (long)kvm_read_c0_guest_prid(cop0);
751 break;
752 case KVM_REG_MIPS_CP0_CONFIG:
753 v = (long)kvm_read_c0_guest_config(cop0);
754 break;
755 case KVM_REG_MIPS_CP0_CONFIG1:
756 v = (long)kvm_read_c0_guest_config1(cop0);
757 break;
758 case KVM_REG_MIPS_CP0_CONFIG2:
759 v = (long)kvm_read_c0_guest_config2(cop0);
760 break;
761 case KVM_REG_MIPS_CP0_CONFIG3:
762 v = (long)kvm_read_c0_guest_config3(cop0);
763 break;
764 case KVM_REG_MIPS_CP0_CONFIG4:
765 v = (long)kvm_read_c0_guest_config4(cop0);
766 break;
767 case KVM_REG_MIPS_CP0_CONFIG5:
768 v = (long)kvm_read_c0_guest_config5(cop0);
769 break;
770 case KVM_REG_MIPS_CP0_CONFIG7:
771 v = (long)kvm_read_c0_guest_config7(cop0);
772 break;
773 case KVM_REG_MIPS_CP0_ERROREPC:
774 v = (long)kvm_read_c0_guest_errorepc(cop0);
775 break;
776 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
777 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
778 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
779 return -EINVAL;
780 switch (idx) {
781 case 2:
782 v = (long)kvm_read_c0_guest_kscratch1(cop0);
783 break;
784 case 3:
785 v = (long)kvm_read_c0_guest_kscratch2(cop0);
786 break;
787 case 4:
788 v = (long)kvm_read_c0_guest_kscratch3(cop0);
789 break;
790 case 5:
791 v = (long)kvm_read_c0_guest_kscratch4(cop0);
792 break;
793 case 6:
794 v = (long)kvm_read_c0_guest_kscratch5(cop0);
795 break;
796 case 7:
797 v = (long)kvm_read_c0_guest_kscratch6(cop0);
798 break;
799 }
800 break;
801 /* registers to be handled specially */
802 default:
803 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
804 if (ret)
805 return ret;
806 break;
807 }
808 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
809 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
810
811 return put_user(v, uaddr64);
812 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
813 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
814 u32 v32 = (u32)v;
815
816 return put_user(v32, uaddr32);
817 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
818 void __user *uaddr = (void __user *)(long)reg->addr;
819
820 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
821 } else {
822 return -EINVAL;
823 }
824 }
825
826 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
827 const struct kvm_one_reg *reg)
828 {
829 struct mips_coproc *cop0 = vcpu->arch.cop0;
830 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
831 s64 v;
832 s64 vs[2];
833 unsigned int idx;
834
835 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
836 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
837
838 if (get_user(v, uaddr64) != 0)
839 return -EFAULT;
840 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
841 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
842 s32 v32;
843
844 if (get_user(v32, uaddr32) != 0)
845 return -EFAULT;
846 v = (s64)v32;
847 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
848 void __user *uaddr = (void __user *)(long)reg->addr;
849
850 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
851 } else {
852 return -EINVAL;
853 }
854
855 switch (reg->id) {
856 /* General purpose registers */
857 case KVM_REG_MIPS_R0:
858 /* Silently ignore requests to set $0 */
859 break;
860 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
861 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
862 break;
863 case KVM_REG_MIPS_HI:
864 vcpu->arch.hi = v;
865 break;
866 case KVM_REG_MIPS_LO:
867 vcpu->arch.lo = v;
868 break;
869 case KVM_REG_MIPS_PC:
870 vcpu->arch.pc = v;
871 break;
872
873 /* Floating point registers */
874 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
875 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
876 return -EINVAL;
877 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
878 /* Odd singles in top of even double when FR=0 */
879 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
880 set_fpr32(&fpu->fpr[idx], 0, v);
881 else
882 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
883 break;
884 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
885 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
886 return -EINVAL;
887 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
888 /* Can't access odd doubles in FR=0 mode */
889 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
890 return -EINVAL;
891 set_fpr64(&fpu->fpr[idx], 0, v);
892 break;
893 case KVM_REG_MIPS_FCR_IR:
894 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
895 return -EINVAL;
896 /* Read-only */
897 break;
898 case KVM_REG_MIPS_FCR_CSR:
899 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
900 return -EINVAL;
901 fpu->fcr31 = v;
902 break;
903
904 /* MIPS SIMD Architecture (MSA) registers */
905 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
906 if (!kvm_mips_guest_has_msa(&vcpu->arch))
907 return -EINVAL;
908 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
909 #ifdef CONFIG_CPU_LITTLE_ENDIAN
910 /* least significant byte first */
911 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
912 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
913 #else
914 /* most significant byte first */
915 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
916 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
917 #endif
918 break;
919 case KVM_REG_MIPS_MSA_IR:
920 if (!kvm_mips_guest_has_msa(&vcpu->arch))
921 return -EINVAL;
922 /* Read-only */
923 break;
924 case KVM_REG_MIPS_MSA_CSR:
925 if (!kvm_mips_guest_has_msa(&vcpu->arch))
926 return -EINVAL;
927 fpu->msacsr = v;
928 break;
929
930 /* Co-processor 0 registers */
931 case KVM_REG_MIPS_CP0_INDEX:
932 kvm_write_c0_guest_index(cop0, v);
933 break;
934 case KVM_REG_MIPS_CP0_CONTEXT:
935 kvm_write_c0_guest_context(cop0, v);
936 break;
937 case KVM_REG_MIPS_CP0_USERLOCAL:
938 kvm_write_c0_guest_userlocal(cop0, v);
939 break;
940 case KVM_REG_MIPS_CP0_PAGEMASK:
941 kvm_write_c0_guest_pagemask(cop0, v);
942 break;
943 case KVM_REG_MIPS_CP0_WIRED:
944 kvm_write_c0_guest_wired(cop0, v);
945 break;
946 case KVM_REG_MIPS_CP0_HWRENA:
947 kvm_write_c0_guest_hwrena(cop0, v);
948 break;
949 case KVM_REG_MIPS_CP0_BADVADDR:
950 kvm_write_c0_guest_badvaddr(cop0, v);
951 break;
952 case KVM_REG_MIPS_CP0_ENTRYHI:
953 kvm_write_c0_guest_entryhi(cop0, v);
954 break;
955 case KVM_REG_MIPS_CP0_STATUS:
956 kvm_write_c0_guest_status(cop0, v);
957 break;
958 case KVM_REG_MIPS_CP0_EPC:
959 kvm_write_c0_guest_epc(cop0, v);
960 break;
961 case KVM_REG_MIPS_CP0_PRID:
962 kvm_write_c0_guest_prid(cop0, v);
963 break;
964 case KVM_REG_MIPS_CP0_ERROREPC:
965 kvm_write_c0_guest_errorepc(cop0, v);
966 break;
967 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
968 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
969 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
970 return -EINVAL;
971 switch (idx) {
972 case 2:
973 kvm_write_c0_guest_kscratch1(cop0, v);
974 break;
975 case 3:
976 kvm_write_c0_guest_kscratch2(cop0, v);
977 break;
978 case 4:
979 kvm_write_c0_guest_kscratch3(cop0, v);
980 break;
981 case 5:
982 kvm_write_c0_guest_kscratch4(cop0, v);
983 break;
984 case 6:
985 kvm_write_c0_guest_kscratch5(cop0, v);
986 break;
987 case 7:
988 kvm_write_c0_guest_kscratch6(cop0, v);
989 break;
990 }
991 break;
992 /* registers to be handled specially */
993 default:
994 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
995 }
996 return 0;
997 }
998
999 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1000 struct kvm_enable_cap *cap)
1001 {
1002 int r = 0;
1003
1004 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1005 return -EINVAL;
1006 if (cap->flags)
1007 return -EINVAL;
1008 if (cap->args[0])
1009 return -EINVAL;
1010
1011 switch (cap->cap) {
1012 case KVM_CAP_MIPS_FPU:
1013 vcpu->arch.fpu_enabled = true;
1014 break;
1015 case KVM_CAP_MIPS_MSA:
1016 vcpu->arch.msa_enabled = true;
1017 break;
1018 default:
1019 r = -EINVAL;
1020 break;
1021 }
1022
1023 return r;
1024 }
1025
1026 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1027 unsigned long arg)
1028 {
1029 struct kvm_vcpu *vcpu = filp->private_data;
1030 void __user *argp = (void __user *)arg;
1031 long r;
1032
1033 switch (ioctl) {
1034 case KVM_SET_ONE_REG:
1035 case KVM_GET_ONE_REG: {
1036 struct kvm_one_reg reg;
1037
1038 if (copy_from_user(&reg, argp, sizeof(reg)))
1039 return -EFAULT;
1040 if (ioctl == KVM_SET_ONE_REG)
1041 return kvm_mips_set_reg(vcpu, &reg);
1042 else
1043 return kvm_mips_get_reg(vcpu, &reg);
1044 }
1045 case KVM_GET_REG_LIST: {
1046 struct kvm_reg_list __user *user_list = argp;
1047 struct kvm_reg_list reg_list;
1048 unsigned n;
1049
1050 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1051 return -EFAULT;
1052 n = reg_list.n;
1053 reg_list.n = kvm_mips_num_regs(vcpu);
1054 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1055 return -EFAULT;
1056 if (n < reg_list.n)
1057 return -E2BIG;
1058 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1059 }
1060 case KVM_NMI:
1061 /* Treat the NMI as a CPU reset */
1062 r = kvm_mips_reset_vcpu(vcpu);
1063 break;
1064 case KVM_INTERRUPT:
1065 {
1066 struct kvm_mips_interrupt irq;
1067
1068 r = -EFAULT;
1069 if (copy_from_user(&irq, argp, sizeof(irq)))
1070 goto out;
1071
1072 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1073 irq.irq);
1074
1075 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1076 break;
1077 }
1078 case KVM_ENABLE_CAP: {
1079 struct kvm_enable_cap cap;
1080
1081 r = -EFAULT;
1082 if (copy_from_user(&cap, argp, sizeof(cap)))
1083 goto out;
1084 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1085 break;
1086 }
1087 default:
1088 r = -ENOIOCTLCMD;
1089 }
1090
1091 out:
1092 return r;
1093 }
1094
1095 /* Get (and clear) the dirty memory log for a memory slot. */
1096 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1097 {
1098 struct kvm_memslots *slots;
1099 struct kvm_memory_slot *memslot;
1100 unsigned long ga, ga_end;
1101 int is_dirty = 0;
1102 int r;
1103 unsigned long n;
1104
1105 mutex_lock(&kvm->slots_lock);
1106
1107 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1108 if (r)
1109 goto out;
1110
1111 /* If nothing is dirty, don't bother messing with page tables. */
1112 if (is_dirty) {
1113 slots = kvm_memslots(kvm);
1114 memslot = id_to_memslot(slots, log->slot);
1115
1116 ga = memslot->base_gfn << PAGE_SHIFT;
1117 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1118
1119 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1120 ga_end);
1121
1122 n = kvm_dirty_bitmap_bytes(memslot);
1123 memset(memslot->dirty_bitmap, 0, n);
1124 }
1125
1126 r = 0;
1127 out:
1128 mutex_unlock(&kvm->slots_lock);
1129 return r;
1130
1131 }
1132
1133 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1134 {
1135 long r;
1136
1137 switch (ioctl) {
1138 default:
1139 r = -ENOIOCTLCMD;
1140 }
1141
1142 return r;
1143 }
1144
1145 int kvm_arch_init(void *opaque)
1146 {
1147 if (kvm_mips_callbacks) {
1148 kvm_err("kvm: module already exists\n");
1149 return -EEXIST;
1150 }
1151
1152 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1153 }
1154
1155 void kvm_arch_exit(void)
1156 {
1157 kvm_mips_callbacks = NULL;
1158 }
1159
1160 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1161 struct kvm_sregs *sregs)
1162 {
1163 return -ENOIOCTLCMD;
1164 }
1165
1166 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1167 struct kvm_sregs *sregs)
1168 {
1169 return -ENOIOCTLCMD;
1170 }
1171
1172 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1173 {
1174 }
1175
1176 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1177 {
1178 return -ENOIOCTLCMD;
1179 }
1180
1181 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1182 {
1183 return -ENOIOCTLCMD;
1184 }
1185
1186 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1187 {
1188 return VM_FAULT_SIGBUS;
1189 }
1190
1191 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1192 {
1193 int r;
1194
1195 switch (ext) {
1196 case KVM_CAP_ONE_REG:
1197 case KVM_CAP_ENABLE_CAP:
1198 r = 1;
1199 break;
1200 case KVM_CAP_COALESCED_MMIO:
1201 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1202 break;
1203 case KVM_CAP_MIPS_FPU:
1204 /* We don't handle systems with inconsistent cpu_has_fpu */
1205 r = !!raw_cpu_has_fpu;
1206 break;
1207 case KVM_CAP_MIPS_MSA:
1208 /*
1209 * We don't support MSA vector partitioning yet:
1210 * 1) It would require explicit support which can't be tested
1211 * yet due to lack of support in current hardware.
1212 * 2) It extends the state that would need to be saved/restored
1213 * by e.g. QEMU for migration.
1214 *
1215 * When vector partitioning hardware becomes available, support
1216 * could be added by requiring a flag when enabling
1217 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1218 * to save/restore the appropriate extra state.
1219 */
1220 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1221 break;
1222 default:
1223 r = 0;
1224 break;
1225 }
1226 return r;
1227 }
1228
1229 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1230 {
1231 return kvm_mips_pending_timer(vcpu);
1232 }
1233
1234 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1235 {
1236 int i;
1237 struct mips_coproc *cop0;
1238
1239 if (!vcpu)
1240 return -1;
1241
1242 kvm_debug("VCPU Register Dump:\n");
1243 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1244 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1245
1246 for (i = 0; i < 32; i += 4) {
1247 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1248 vcpu->arch.gprs[i],
1249 vcpu->arch.gprs[i + 1],
1250 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1251 }
1252 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1253 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1254
1255 cop0 = vcpu->arch.cop0;
1256 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1257 kvm_read_c0_guest_status(cop0),
1258 kvm_read_c0_guest_cause(cop0));
1259
1260 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1261
1262 return 0;
1263 }
1264
1265 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1266 {
1267 int i;
1268
1269 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1270 vcpu->arch.gprs[i] = regs->gpr[i];
1271 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1272 vcpu->arch.hi = regs->hi;
1273 vcpu->arch.lo = regs->lo;
1274 vcpu->arch.pc = regs->pc;
1275
1276 return 0;
1277 }
1278
1279 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1280 {
1281 int i;
1282
1283 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1284 regs->gpr[i] = vcpu->arch.gprs[i];
1285
1286 regs->hi = vcpu->arch.hi;
1287 regs->lo = vcpu->arch.lo;
1288 regs->pc = vcpu->arch.pc;
1289
1290 return 0;
1291 }
1292
1293 static void kvm_mips_comparecount_func(unsigned long data)
1294 {
1295 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1296
1297 kvm_mips_callbacks->queue_timer_int(vcpu);
1298
1299 vcpu->arch.wait = 0;
1300 if (swait_active(&vcpu->wq))
1301 swake_up(&vcpu->wq);
1302 }
1303
1304 /* low level hrtimer wake routine */
1305 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1306 {
1307 struct kvm_vcpu *vcpu;
1308
1309 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1310 kvm_mips_comparecount_func((unsigned long) vcpu);
1311 return kvm_mips_count_timeout(vcpu);
1312 }
1313
1314 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1315 {
1316 kvm_mips_callbacks->vcpu_init(vcpu);
1317 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1318 HRTIMER_MODE_REL);
1319 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1320 return 0;
1321 }
1322
1323 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1324 struct kvm_translation *tr)
1325 {
1326 return 0;
1327 }
1328
1329 /* Initial guest state */
1330 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1331 {
1332 return kvm_mips_callbacks->vcpu_setup(vcpu);
1333 }
1334
1335 static void kvm_mips_set_c0_status(void)
1336 {
1337 u32 status = read_c0_status();
1338
1339 if (cpu_has_dsp)
1340 status |= (ST0_MX);
1341
1342 write_c0_status(status);
1343 ehb();
1344 }
1345
1346 /*
1347 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1348 */
1349 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1350 {
1351 u32 cause = vcpu->arch.host_cp0_cause;
1352 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1353 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1354 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1355 enum emulation_result er = EMULATE_DONE;
1356 int ret = RESUME_GUEST;
1357
1358 /* re-enable HTW before enabling interrupts */
1359 htw_start();
1360
1361 /* Set a default exit reason */
1362 run->exit_reason = KVM_EXIT_UNKNOWN;
1363 run->ready_for_interrupt_injection = 1;
1364
1365 /*
1366 * Set the appropriate status bits based on host CPU features,
1367 * before we hit the scheduler
1368 */
1369 kvm_mips_set_c0_status();
1370
1371 local_irq_enable();
1372
1373 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1374 cause, opc, run, vcpu);
1375 trace_kvm_exit(vcpu, exccode);
1376
1377 /*
1378 * Do a privilege check, if in UM most of these exit conditions end up
1379 * causing an exception to be delivered to the Guest Kernel
1380 */
1381 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1382 if (er == EMULATE_PRIV_FAIL) {
1383 goto skip_emul;
1384 } else if (er == EMULATE_FAIL) {
1385 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1386 ret = RESUME_HOST;
1387 goto skip_emul;
1388 }
1389
1390 switch (exccode) {
1391 case EXCCODE_INT:
1392 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1393
1394 ++vcpu->stat.int_exits;
1395
1396 if (need_resched())
1397 cond_resched();
1398
1399 ret = RESUME_GUEST;
1400 break;
1401
1402 case EXCCODE_CPU:
1403 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1404
1405 ++vcpu->stat.cop_unusable_exits;
1406 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1407 /* XXXKYMA: Might need to return to user space */
1408 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1409 ret = RESUME_HOST;
1410 break;
1411
1412 case EXCCODE_MOD:
1413 ++vcpu->stat.tlbmod_exits;
1414 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1415 break;
1416
1417 case EXCCODE_TLBS:
1418 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1419 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1420 badvaddr);
1421
1422 ++vcpu->stat.tlbmiss_st_exits;
1423 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1424 break;
1425
1426 case EXCCODE_TLBL:
1427 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1428 cause, opc, badvaddr);
1429
1430 ++vcpu->stat.tlbmiss_ld_exits;
1431 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1432 break;
1433
1434 case EXCCODE_ADES:
1435 ++vcpu->stat.addrerr_st_exits;
1436 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1437 break;
1438
1439 case EXCCODE_ADEL:
1440 ++vcpu->stat.addrerr_ld_exits;
1441 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1442 break;
1443
1444 case EXCCODE_SYS:
1445 ++vcpu->stat.syscall_exits;
1446 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1447 break;
1448
1449 case EXCCODE_RI:
1450 ++vcpu->stat.resvd_inst_exits;
1451 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1452 break;
1453
1454 case EXCCODE_BP:
1455 ++vcpu->stat.break_inst_exits;
1456 ret = kvm_mips_callbacks->handle_break(vcpu);
1457 break;
1458
1459 case EXCCODE_TR:
1460 ++vcpu->stat.trap_inst_exits;
1461 ret = kvm_mips_callbacks->handle_trap(vcpu);
1462 break;
1463
1464 case EXCCODE_MSAFPE:
1465 ++vcpu->stat.msa_fpe_exits;
1466 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1467 break;
1468
1469 case EXCCODE_FPE:
1470 ++vcpu->stat.fpe_exits;
1471 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1472 break;
1473
1474 case EXCCODE_MSADIS:
1475 ++vcpu->stat.msa_disabled_exits;
1476 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1477 break;
1478
1479 default:
1480 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1481 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1482 kvm_read_c0_guest_status(vcpu->arch.cop0));
1483 kvm_arch_vcpu_dump_regs(vcpu);
1484 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1485 ret = RESUME_HOST;
1486 break;
1487
1488 }
1489
1490 skip_emul:
1491 local_irq_disable();
1492
1493 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1494 kvm_mips_deliver_interrupts(vcpu, cause);
1495
1496 if (!(ret & RESUME_HOST)) {
1497 /* Only check for signals if not already exiting to userspace */
1498 if (signal_pending(current)) {
1499 run->exit_reason = KVM_EXIT_INTR;
1500 ret = (-EINTR << 2) | RESUME_HOST;
1501 ++vcpu->stat.signal_exits;
1502 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1503 }
1504 }
1505
1506 if (ret == RESUME_GUEST) {
1507 trace_kvm_reenter(vcpu);
1508
1509 /*
1510 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1511 * is live), restore FCR31 / MSACSR.
1512 *
1513 * This should be before returning to the guest exception
1514 * vector, as it may well cause an [MSA] FP exception if there
1515 * are pending exception bits unmasked. (see
1516 * kvm_mips_csr_die_notifier() for how that is handled).
1517 */
1518 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1519 read_c0_status() & ST0_CU1)
1520 __kvm_restore_fcsr(&vcpu->arch);
1521
1522 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1523 read_c0_config5() & MIPS_CONF5_MSAEN)
1524 __kvm_restore_msacsr(&vcpu->arch);
1525 }
1526
1527 /* Disable HTW before returning to guest or host */
1528 htw_stop();
1529
1530 return ret;
1531 }
1532
1533 /* Enable FPU for guest and restore context */
1534 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1535 {
1536 struct mips_coproc *cop0 = vcpu->arch.cop0;
1537 unsigned int sr, cfg5;
1538
1539 preempt_disable();
1540
1541 sr = kvm_read_c0_guest_status(cop0);
1542
1543 /*
1544 * If MSA state is already live, it is undefined how it interacts with
1545 * FR=0 FPU state, and we don't want to hit reserved instruction
1546 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1547 * play it safe and save it first.
1548 *
1549 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1550 * get called when guest CU1 is set, however we can't trust the guest
1551 * not to clobber the status register directly via the commpage.
1552 */
1553 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1554 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1555 kvm_lose_fpu(vcpu);
1556
1557 /*
1558 * Enable FPU for guest
1559 * We set FR and FRE according to guest context
1560 */
1561 change_c0_status(ST0_CU1 | ST0_FR, sr);
1562 if (cpu_has_fre) {
1563 cfg5 = kvm_read_c0_guest_config5(cop0);
1564 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1565 }
1566 enable_fpu_hazard();
1567
1568 /* If guest FPU state not active, restore it now */
1569 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1570 __kvm_restore_fpu(&vcpu->arch);
1571 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1572 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1573 } else {
1574 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1575 }
1576
1577 preempt_enable();
1578 }
1579
1580 #ifdef CONFIG_CPU_HAS_MSA
1581 /* Enable MSA for guest and restore context */
1582 void kvm_own_msa(struct kvm_vcpu *vcpu)
1583 {
1584 struct mips_coproc *cop0 = vcpu->arch.cop0;
1585 unsigned int sr, cfg5;
1586
1587 preempt_disable();
1588
1589 /*
1590 * Enable FPU if enabled in guest, since we're restoring FPU context
1591 * anyway. We set FR and FRE according to guest context.
1592 */
1593 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1594 sr = kvm_read_c0_guest_status(cop0);
1595
1596 /*
1597 * If FR=0 FPU state is already live, it is undefined how it
1598 * interacts with MSA state, so play it safe and save it first.
1599 */
1600 if (!(sr & ST0_FR) &&
1601 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1602 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1603 kvm_lose_fpu(vcpu);
1604
1605 change_c0_status(ST0_CU1 | ST0_FR, sr);
1606 if (sr & ST0_CU1 && cpu_has_fre) {
1607 cfg5 = kvm_read_c0_guest_config5(cop0);
1608 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1609 }
1610 }
1611
1612 /* Enable MSA for guest */
1613 set_c0_config5(MIPS_CONF5_MSAEN);
1614 enable_fpu_hazard();
1615
1616 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1617 case KVM_MIPS_AUX_FPU:
1618 /*
1619 * Guest FPU state already loaded, only restore upper MSA state
1620 */
1621 __kvm_restore_msa_upper(&vcpu->arch);
1622 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1623 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1624 break;
1625 case 0:
1626 /* Neither FPU or MSA already active, restore full MSA state */
1627 __kvm_restore_msa(&vcpu->arch);
1628 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1629 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1630 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1631 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1632 KVM_TRACE_AUX_FPU_MSA);
1633 break;
1634 default:
1635 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1636 break;
1637 }
1638
1639 preempt_enable();
1640 }
1641 #endif
1642
1643 /* Drop FPU & MSA without saving it */
1644 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1645 {
1646 preempt_disable();
1647 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1648 disable_msa();
1649 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1650 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1651 }
1652 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1653 clear_c0_status(ST0_CU1 | ST0_FR);
1654 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1655 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1656 }
1657 preempt_enable();
1658 }
1659
1660 /* Save and disable FPU & MSA */
1661 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1662 {
1663 /*
1664 * FPU & MSA get disabled in root context (hardware) when it is disabled
1665 * in guest context (software), but the register state in the hardware
1666 * may still be in use. This is why we explicitly re-enable the hardware
1667 * before saving.
1668 */
1669
1670 preempt_disable();
1671 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1672 set_c0_config5(MIPS_CONF5_MSAEN);
1673 enable_fpu_hazard();
1674
1675 __kvm_save_msa(&vcpu->arch);
1676 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1677
1678 /* Disable MSA & FPU */
1679 disable_msa();
1680 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1681 clear_c0_status(ST0_CU1 | ST0_FR);
1682 disable_fpu_hazard();
1683 }
1684 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1685 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1686 set_c0_status(ST0_CU1);
1687 enable_fpu_hazard();
1688
1689 __kvm_save_fpu(&vcpu->arch);
1690 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1691 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1692
1693 /* Disable FPU */
1694 clear_c0_status(ST0_CU1 | ST0_FR);
1695 disable_fpu_hazard();
1696 }
1697 preempt_enable();
1698 }
1699
1700 /*
1701 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1702 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1703 * exception if cause bits are set in the value being written.
1704 */
1705 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1706 unsigned long cmd, void *ptr)
1707 {
1708 struct die_args *args = (struct die_args *)ptr;
1709 struct pt_regs *regs = args->regs;
1710 unsigned long pc;
1711
1712 /* Only interested in FPE and MSAFPE */
1713 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1714 return NOTIFY_DONE;
1715
1716 /* Return immediately if guest context isn't active */
1717 if (!(current->flags & PF_VCPU))
1718 return NOTIFY_DONE;
1719
1720 /* Should never get here from user mode */
1721 BUG_ON(user_mode(regs));
1722
1723 pc = instruction_pointer(regs);
1724 switch (cmd) {
1725 case DIE_FP:
1726 /* match 2nd instruction in __kvm_restore_fcsr */
1727 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1728 return NOTIFY_DONE;
1729 break;
1730 case DIE_MSAFP:
1731 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1732 if (!cpu_has_msa ||
1733 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1734 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1735 return NOTIFY_DONE;
1736 break;
1737 }
1738
1739 /* Move PC forward a little and continue executing */
1740 instruction_pointer(regs) += 4;
1741
1742 return NOTIFY_STOP;
1743 }
1744
1745 static struct notifier_block kvm_mips_csr_die_notifier = {
1746 .notifier_call = kvm_mips_csr_die_notify,
1747 };
1748
1749 static int __init kvm_mips_init(void)
1750 {
1751 int ret;
1752
1753 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1754
1755 if (ret)
1756 return ret;
1757
1758 register_die_notifier(&kvm_mips_csr_die_notifier);
1759
1760 return 0;
1761 }
1762
1763 static void __exit kvm_mips_exit(void)
1764 {
1765 kvm_exit();
1766
1767 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1768 }
1769
1770 module_init(kvm_mips_init);
1771 module_exit(kvm_mips_exit);
1772
1773 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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