2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
13 #include <asm/bootinfo.h>
14 #include <asm/irq_cpu.h>
16 #include <lantiq_soc.h>
19 /* register definitions */
20 #define LTQ_ICU_IM0_ISR 0x0000
21 #define LTQ_ICU_IM0_IER 0x0008
22 #define LTQ_ICU_IM0_IOSR 0x0010
23 #define LTQ_ICU_IM0_IRSR 0x0018
24 #define LTQ_ICU_IM0_IMR 0x0020
25 #define LTQ_ICU_IM1_ISR 0x0028
26 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
28 #define LTQ_EIU_EXIN_C 0x0000
29 #define LTQ_EIU_EXIN_INIC 0x0004
30 #define LTQ_EIU_EXIN_INEN 0x000C
32 /* irq numbers used by the external interrupt unit (EIU) */
33 #define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
34 #define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
35 #define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
36 #define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
37 #define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
38 #define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
39 #define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
43 /* the performance counter */
44 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
46 /* irqs generated by device attached to the EBU need to be acked in
49 #define LTQ_ICU_EBU_IRQ 22
51 #define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
52 #define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
57 /* our 2 ipi interrupts for VSMP */
58 #define MIPS_CPU_IPI_RESCHED_IRQ 0
59 #define MIPS_CPU_IPI_CALL_IRQ 1
61 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
65 static unsigned short ltq_eiu_irq
[MAX_EIU
] = {
74 static struct resource ltq_icu_resource
= {
76 .start
= LTQ_ICU_BASE_ADDR
,
77 .end
= LTQ_ICU_BASE_ADDR
+ LTQ_ICU_SIZE
- 1,
78 .flags
= IORESOURCE_MEM
,
81 static struct resource ltq_eiu_resource
= {
83 .start
= LTQ_EIU_BASE_ADDR
,
84 .end
= LTQ_EIU_BASE_ADDR
+ LTQ_ICU_SIZE
- 1,
85 .flags
= IORESOURCE_MEM
,
88 static void __iomem
*ltq_icu_membase
;
89 static void __iomem
*ltq_eiu_membase
;
91 void ltq_disable_irq(struct irq_data
*d
)
93 u32 ier
= LTQ_ICU_IM0_IER
;
94 int irq_nr
= d
->irq
- INT_NUM_IRQ0
;
96 ier
+= LTQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
97 irq_nr
%= INT_NUM_IM_OFFSET
;
98 ltq_icu_w32(ltq_icu_r32(ier
) & ~(1 << irq_nr
), ier
);
101 void ltq_mask_and_ack_irq(struct irq_data
*d
)
103 u32 ier
= LTQ_ICU_IM0_IER
;
104 u32 isr
= LTQ_ICU_IM0_ISR
;
105 int irq_nr
= d
->irq
- INT_NUM_IRQ0
;
107 ier
+= LTQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
108 isr
+= LTQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
109 irq_nr
%= INT_NUM_IM_OFFSET
;
110 ltq_icu_w32(ltq_icu_r32(ier
) & ~(1 << irq_nr
), ier
);
111 ltq_icu_w32((1 << irq_nr
), isr
);
114 static void ltq_ack_irq(struct irq_data
*d
)
116 u32 isr
= LTQ_ICU_IM0_ISR
;
117 int irq_nr
= d
->irq
- INT_NUM_IRQ0
;
119 isr
+= LTQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
120 irq_nr
%= INT_NUM_IM_OFFSET
;
121 ltq_icu_w32((1 << irq_nr
), isr
);
124 void ltq_enable_irq(struct irq_data
*d
)
126 u32 ier
= LTQ_ICU_IM0_IER
;
127 int irq_nr
= d
->irq
- INT_NUM_IRQ0
;
129 ier
+= LTQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
130 irq_nr
%= INT_NUM_IM_OFFSET
;
131 ltq_icu_w32(ltq_icu_r32(ier
) | (1 << irq_nr
), ier
);
134 static unsigned int ltq_startup_eiu_irq(struct irq_data
*d
)
139 for (i
= 0; i
< MAX_EIU
; i
++) {
140 if (d
->irq
== ltq_eiu_irq
[i
]) {
141 /* low level - we should really handle set_type */
142 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C
) |
143 (0x6 << (i
* 4)), LTQ_EIU_EXIN_C
);
144 /* clear all pending */
145 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC
) & ~(1 << i
),
148 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) | (1 << i
),
157 static void ltq_shutdown_eiu_irq(struct irq_data
*d
)
162 for (i
= 0; i
< MAX_EIU
; i
++) {
163 if (d
->irq
== ltq_eiu_irq
[i
]) {
165 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) & ~(1 << i
),
172 static struct irq_chip ltq_irq_type
= {
174 .irq_enable
= ltq_enable_irq
,
175 .irq_disable
= ltq_disable_irq
,
176 .irq_unmask
= ltq_enable_irq
,
177 .irq_ack
= ltq_ack_irq
,
178 .irq_mask
= ltq_disable_irq
,
179 .irq_mask_ack
= ltq_mask_and_ack_irq
,
182 static struct irq_chip ltq_eiu_type
= {
184 .irq_startup
= ltq_startup_eiu_irq
,
185 .irq_shutdown
= ltq_shutdown_eiu_irq
,
186 .irq_enable
= ltq_enable_irq
,
187 .irq_disable
= ltq_disable_irq
,
188 .irq_unmask
= ltq_enable_irq
,
189 .irq_ack
= ltq_ack_irq
,
190 .irq_mask
= ltq_disable_irq
,
191 .irq_mask_ack
= ltq_mask_and_ack_irq
,
194 static void ltq_hw_irqdispatch(int module
)
198 irq
= ltq_icu_r32(LTQ_ICU_IM0_IOSR
+ (module
* LTQ_ICU_OFFSET
));
202 /* silicon bug causes only the msb set to 1 to be valid. all
203 * other bits might be bogus
206 do_IRQ((int)irq
+ INT_NUM_IM0_IRL0
+ (INT_NUM_IM_OFFSET
* module
));
208 /* if this is a EBU irq, we need to ack it or get a deadlock */
209 if ((irq
== LTQ_ICU_EBU_IRQ
) && (module
== 0))
210 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT
) | 0x10,
214 #define DEFINE_HWx_IRQDISPATCH(x) \
215 static void ltq_hw ## x ## _irqdispatch(void) \
217 ltq_hw_irqdispatch(x); \
219 DEFINE_HWx_IRQDISPATCH(0)
220 DEFINE_HWx_IRQDISPATCH(1)
221 DEFINE_HWx_IRQDISPATCH(2)
222 DEFINE_HWx_IRQDISPATCH(3)
223 DEFINE_HWx_IRQDISPATCH(4)
225 static void ltq_hw5_irqdispatch(void)
227 do_IRQ(MIPS_CPU_TIMER_IRQ
);
230 #ifdef CONFIG_MIPS_MT_SMP
231 void __init
arch_init_ipiirq(int irq
, struct irqaction
*action
)
233 setup_irq(irq
, action
);
234 irq_set_handler(irq
, handle_percpu_irq
);
237 static void ltq_sw0_irqdispatch(void)
239 do_IRQ(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_RESCHED_IRQ
);
242 static void ltq_sw1_irqdispatch(void)
244 do_IRQ(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_CALL_IRQ
);
246 static irqreturn_t
ipi_resched_interrupt(int irq
, void *dev_id
)
252 static irqreturn_t
ipi_call_interrupt(int irq
, void *dev_id
)
254 smp_call_function_interrupt();
258 static struct irqaction irq_resched
= {
259 .handler
= ipi_resched_interrupt
,
260 .flags
= IRQF_PERCPU
,
261 .name
= "IPI_resched"
264 static struct irqaction irq_call
= {
265 .handler
= ipi_call_interrupt
,
266 .flags
= IRQF_PERCPU
,
271 asmlinkage
void plat_irq_dispatch(void)
273 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
276 if (pending
& CAUSEF_IP7
) {
277 do_IRQ(MIPS_CPU_TIMER_IRQ
);
280 for (i
= 0; i
< 5; i
++) {
281 if (pending
& (CAUSEF_IP2
<< i
)) {
282 ltq_hw_irqdispatch(i
);
287 pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
293 static struct irqaction cascade
= {
294 .handler
= no_action
,
298 void __init
arch_init_irq(void)
302 if (insert_resource(&iomem_resource
, <q_icu_resource
) < 0)
303 panic("Failed to insert icu memory");
305 if (request_mem_region(ltq_icu_resource
.start
,
306 resource_size(<q_icu_resource
), "icu") < 0)
307 panic("Failed to request icu memory");
309 ltq_icu_membase
= ioremap_nocache(ltq_icu_resource
.start
,
310 resource_size(<q_icu_resource
));
311 if (!ltq_icu_membase
)
312 panic("Failed to remap icu memory");
314 if (insert_resource(&iomem_resource
, <q_eiu_resource
) < 0)
315 panic("Failed to insert eiu memory");
317 if (request_mem_region(ltq_eiu_resource
.start
,
318 resource_size(<q_eiu_resource
), "eiu") < 0)
319 panic("Failed to request eiu memory");
321 ltq_eiu_membase
= ioremap_nocache(ltq_eiu_resource
.start
,
322 resource_size(<q_eiu_resource
));
323 if (!ltq_eiu_membase
)
324 panic("Failed to remap eiu memory");
326 /* turn off all irqs by default */
327 for (i
= 0; i
< 5; i
++) {
328 /* make sure all irqs are turned off by default */
329 ltq_icu_w32(0, LTQ_ICU_IM0_IER
+ (i
* LTQ_ICU_OFFSET
));
330 /* clear all possibly pending interrupts */
331 ltq_icu_w32(~0, LTQ_ICU_IM0_ISR
+ (i
* LTQ_ICU_OFFSET
));
336 for (i
= 2; i
<= 6; i
++)
337 setup_irq(i
, &cascade
);
340 pr_info("Setting up vectored interrupts\n");
341 set_vi_handler(2, ltq_hw0_irqdispatch
);
342 set_vi_handler(3, ltq_hw1_irqdispatch
);
343 set_vi_handler(4, ltq_hw2_irqdispatch
);
344 set_vi_handler(5, ltq_hw3_irqdispatch
);
345 set_vi_handler(6, ltq_hw4_irqdispatch
);
346 set_vi_handler(7, ltq_hw5_irqdispatch
);
349 for (i
= INT_NUM_IRQ0
;
350 i
<= (INT_NUM_IRQ0
+ (5 * INT_NUM_IM_OFFSET
)); i
++)
351 if ((i
== LTQ_EIU_IR0
) || (i
== LTQ_EIU_IR1
) ||
353 irq_set_chip_and_handler(i
, <q_eiu_type
,
355 /* EIU3-5 only exist on ar9 and vr9 */
356 else if (((i
== LTQ_EIU_IR3
) || (i
== LTQ_EIU_IR4
) ||
357 (i
== LTQ_EIU_IR5
)) && (ltq_is_ar9() || ltq_is_vr9()))
358 irq_set_chip_and_handler(i
, <q_eiu_type
,
361 irq_set_chip_and_handler(i
, <q_irq_type
,
364 #if defined(CONFIG_MIPS_MT_SMP)
366 pr_info("Setting up IPI vectored interrupts\n");
367 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ
, ltq_sw0_irqdispatch
);
368 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ
, ltq_sw1_irqdispatch
);
370 arch_init_ipiirq(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_RESCHED_IRQ
,
372 arch_init_ipiirq(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_CALL_IRQ
, &irq_call
);
375 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
376 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
377 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
379 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
380 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
383 /* tell oprofile which irq to use */
384 cp0_perfcount_irq
= LTQ_PERF_IRQ
;
387 unsigned int __cpuinit
get_c0_compare_int(void)
389 return CP0_LEGACY_COMPARE_IRQ
;