arch/mips/lib/csum_partial.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Quick'n'dirty IP checksum ...
   7  *
   8  * Copyright (C) 1998, 1999 Ralf Baechle
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Copyright (C) 2007  Maciej W. Rozycki
  11  * Copyright (C) 2014 Imagination Technologies Ltd.
  12  */
  13 #include <linux/errno.h>
  14 #include <asm/asm.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/regdef.h>
  17
  18 #ifdef CONFIG_64BIT
  19 /*
  20  * As we are sharing code base with the mips32 tree (which use the o32 ABI
  21  * register definitions). We need to redefine the register definitions from
  22  * the n64 ABI register naming to the o32 ABI register naming.
  23  */
  24 #undef t0
  25 #undef t1
  26 #undef t2
  27 #undef t3
  28 #define t0      $8
  29 #define t1      $9
  30 #define t2      $10
  31 #define t3      $11
  32 #define t4      $12
  33 #define t5      $13
  34 #define t6      $14
  35 #define t7      $15
  36
  37 #define USE_DOUBLE
  38 #endif
  39
  40 #ifdef USE_DOUBLE
  41
  42 #define LOAD   ld
  43 #define LOAD32 lwu
  44 #define ADD    daddu
  45 #define NBYTES 8
  46
  47 #else
  48
  49 #define LOAD   lw
  50 #define LOAD32 lw
  51 #define ADD    addu
  52 #define NBYTES 4
  53
  54 #endif /* USE_DOUBLE */
  55
  56 #define UNIT(unit)  ((unit)*NBYTES)
  57
  58 #define ADDC(sum,reg)                                           \
  59         ADD     sum, reg;                                       \
  60         sltu    v1, sum, reg;                                   \
  61         ADD     sum, v1;                                        \
  62
  63 #define ADDC32(sum,reg)                                         \
  64         addu    sum, reg;                                       \
  65         sltu    v1, sum, reg;                                   \
  66         addu    sum, v1;                                        \
  67
  68 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)    \
  69         LOAD    _t0, (offset + UNIT(0))(src);                   \
  70         LOAD    _t1, (offset + UNIT(1))(src);                   \
  71         LOAD    _t2, (offset + UNIT(2))(src);                   \
  72         LOAD    _t3, (offset + UNIT(3))(src);                   \
  73         ADDC(sum, _t0);                                         \
  74         ADDC(sum, _t1);                                         \
  75         ADDC(sum, _t2);                                         \
  76         ADDC(sum, _t3)
  77
  78 #ifdef USE_DOUBLE
  79 #define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3)     \
  80         CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)
  81 #else
  82 #define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3)     \
  83         CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3);   \
  84         CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3)
  85 #endif
  86
  87 /*
  88  * a0: source address
  89  * a1: length of the area to checksum
  90  * a2: partial checksum
  91  */
  92
  93 #define src a0
  94 #define sum v0
  95
  96         .text
  97         .set    noreorder
  98         .align  5
  99 LEAF(csum_partial)
 100         move    sum, zero
 101         move    t7, zero
 102
 103         sltiu   t8, a1, 0x8
 104         bnez    t8, .Lsmall_csumcpy             /* < 8 bytes to copy */
 105          move   t2, a1
 106
 107         andi    t7, src, 0x1                    /* odd buffer? */
 108
 109 .Lhword_align:
 110         beqz    t7, .Lword_align
 111          andi   t8, src, 0x2
 112
 113         lbu     t0, (src)
 114         LONG_SUBU       a1, a1, 0x1
 115 #ifdef __MIPSEL__
 116         sll     t0, t0, 8
 117 #endif
 118         ADDC(sum, t0)
 119         PTR_ADDU        src, src, 0x1
 120         andi    t8, src, 0x2
 121
 122 .Lword_align:
 123         beqz    t8, .Ldword_align
 124          sltiu  t8, a1, 56
 125
 126         lhu     t0, (src)
 127         LONG_SUBU       a1, a1, 0x2
 128         ADDC(sum, t0)
 129         sltiu   t8, a1, 56
 130         PTR_ADDU        src, src, 0x2
 131
 132 .Ldword_align:
 133         bnez    t8, .Ldo_end_words
 134          move   t8, a1
 135
 136         andi    t8, src, 0x4
 137         beqz    t8, .Lqword_align
 138          andi   t8, src, 0x8
 139
 140         LOAD32  t0, 0x00(src)
 141         LONG_SUBU       a1, a1, 0x4
 142         ADDC(sum, t0)
 143         PTR_ADDU        src, src, 0x4
 144         andi    t8, src, 0x8
 145
 146 .Lqword_align:
 147         beqz    t8, .Loword_align
 148          andi   t8, src, 0x10
 149
 150 #ifdef USE_DOUBLE
 151         ld      t0, 0x00(src)
 152         LONG_SUBU       a1, a1, 0x8
 153         ADDC(sum, t0)
 154 #else
 155         lw      t0, 0x00(src)
 156         lw      t1, 0x04(src)
 157         LONG_SUBU       a1, a1, 0x8
 158         ADDC(sum, t0)
 159         ADDC(sum, t1)
 160 #endif
 161         PTR_ADDU        src, src, 0x8
 162         andi    t8, src, 0x10
 163
 164 .Loword_align:
 165         beqz    t8, .Lbegin_movement
 166          LONG_SRL       t8, a1, 0x7
 167
 168 #ifdef USE_DOUBLE
 169         ld      t0, 0x00(src)
 170         ld      t1, 0x08(src)
 171         ADDC(sum, t0)
 172         ADDC(sum, t1)
 173 #else
 174         CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
 175 #endif
 176         LONG_SUBU       a1, a1, 0x10
 177         PTR_ADDU        src, src, 0x10
 178         LONG_SRL        t8, a1, 0x7
 179
 180 .Lbegin_movement:
 181         beqz    t8, 1f
 182          andi   t2, a1, 0x40
 183
 184 .Lmove_128bytes:
 185         CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
 186         CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
 187         CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
 188         CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
 189         LONG_SUBU       t8, t8, 0x01
 190         .set    reorder                         /* DADDI_WAR */
 191         PTR_ADDU        src, src, 0x80
 192         bnez    t8, .Lmove_128bytes
 193         .set    noreorder
 194
 195 1:
 196         beqz    t2, 1f
 197          andi   t2, a1, 0x20
 198
 199 .Lmove_64bytes:
 200         CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
 201         CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
 202         PTR_ADDU        src, src, 0x40
 203
 204 1:
 205         beqz    t2, .Ldo_end_words
 206          andi   t8, a1, 0x1c
 207
 208 .Lmove_32bytes:
 209         CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
 210         andi    t8, a1, 0x1c
 211         PTR_ADDU        src, src, 0x20
 212
 213 .Ldo_end_words:
 214         beqz    t8, .Lsmall_csumcpy
 215          andi   t2, a1, 0x3
 216         LONG_SRL        t8, t8, 0x2
 217
 218 .Lend_words:
 219         LOAD32  t0, (src)
 220         LONG_SUBU       t8, t8, 0x1
 221         ADDC(sum, t0)
 222         .set    reorder                         /* DADDI_WAR */
 223         PTR_ADDU        src, src, 0x4
 224         bnez    t8, .Lend_words
 225         .set    noreorder
 226
 227 /* unknown src alignment and < 8 bytes to go  */
 228 .Lsmall_csumcpy:
 229         move    a1, t2
 230
 231         andi    t0, a1, 4
 232         beqz    t0, 1f
 233          andi   t0, a1, 2
 234
 235         /* Still a full word to go  */
 236         ulw     t1, (src)
 237         PTR_ADDIU       src, 4
 238 #ifdef USE_DOUBLE
 239         dsll    t1, t1, 32                      /* clear lower 32bit */
 240 #endif
 241         ADDC(sum, t1)
 242
 243 1:      move    t1, zero
 244         beqz    t0, 1f
 245          andi   t0, a1, 1
 246
 247         /* Still a halfword to go  */
 248         ulhu    t1, (src)
 249         PTR_ADDIU       src, 2
 250
 251 1:      beqz    t0, 1f
 252          sll    t1, t1, 16
 253
 254         lbu     t2, (src)
 255          nop
 256
 257 #ifdef __MIPSEB__
 258         sll     t2, t2, 8
 259 #endif
 260         or      t1, t2
 261
 262 1:      ADDC(sum, t1)
 263
 264         /* fold checksum */
 265 #ifdef USE_DOUBLE
 266         dsll32  v1, sum, 0
 267         daddu   sum, v1
 268         sltu    v1, sum, v1
 269         dsra32  sum, sum, 0
 270         addu    sum, v1
 271 #endif
 272
 273         /* odd buffer alignment? */
 274 #ifdef CONFIG_CPU_MIPSR2
 275         wsbh    v1, sum
 276         movn    sum, v1, t7
 277 #else
 278         beqz    t7, 1f                  /* odd buffer alignment? */
 279          lui    v1, 0x00ff
 280         addu    v1, 0x00ff
 281         and     t0, sum, v1
 282         sll     t0, t0, 8
 283         srl     sum, sum, 8
 284         and     sum, sum, v1
 285         or      sum, sum, t0
 286 1:
 287 #endif
 288         .set    reorder
 289         /* Add the passed partial csum.  */
 290         ADDC32(sum, a2)
 291         jr      ra
 292         .set    noreorder
 293         END(csum_partial)
 294
 295
 296 /*
 297  * checksum and copy routines based on memcpy.S
 298  *
 299  *      csum_partial_copy_nocheck(src, dst, len, sum)
 300  *      __csum_partial_copy_kernel(src, dst, len, sum, errp)
 301  *
 302  * See "Spec" in memcpy.S for details.  Unlike __copy_user, all
 303  * function in this file use the standard calling convention.
 304  */
 305
 306 #define src a0
 307 #define dst a1
 308 #define len a2
 309 #define psum a3
 310 #define sum v0
 311 #define odd t8
 312 #define errptr t9
 313
 314 /*
 315  * The exception handler for loads requires that:
 316  *  1- AT contain the address of the byte just past the end of the source
 317  *     of the copy,
 318  *  2- src_entry <= src < AT, and
 319  *  3- (dst - src) == (dst_entry - src_entry),
 320  * The _entry suffix denotes values when __copy_user was called.
 321  *
 322  * (1) is set up up by __csum_partial_copy_from_user and maintained by
 323  *      not writing AT in __csum_partial_copy
 324  * (2) is met by incrementing src by the number of bytes copied
 325  * (3) is met by not doing loads between a pair of increments of dst and src
 326  *
 327  * The exception handlers for stores stores -EFAULT to errptr and return.
 328  * These handlers do not need to overwrite any data.
 329  */
 330
 331 /* Instruction type */
 332 #define LD_INSN 1
 333 #define ST_INSN 2
 334 #define LEGACY_MODE 1
 335 #define EVA_MODE    2
 336 #define USEROP   1
 337 #define KERNELOP 2
 338
 339 /*
 340  * Wrapper to add an entry in the exception table
 341  * in case the insn causes a memory exception.
 342  * Arguments:
 343  * insn    : Load/store instruction
 344  * type    : Instruction type
 345  * reg     : Register
 346  * addr    : Address
 347  * handler : Exception handler
 348  */
 349 #define EXC(insn, type, reg, addr, handler)     \
 350         .if \mode == LEGACY_MODE;               \
 351 9:              insn reg, addr;                 \
 352                 .section __ex_table,"a";        \
 353                 PTR     9b, handler;            \
 354                 .previous;                      \
 355         .endif
 356
 357 #undef LOAD
 358
 359 #ifdef USE_DOUBLE
 360
 361 #define LOADK   ld /* No exception */
 362 #define LOAD(reg, addr, handler)        EXC(ld, LD_INSN, reg, addr, handler)
 363 #define LOADBU(reg, addr, handler)      EXC(lbu, LD_INSN, reg, addr, handler)
 364 #define LOADL(reg, addr, handler)       EXC(ldl, LD_INSN, reg, addr, handler)
 365 #define LOADR(reg, addr, handler)       EXC(ldr, LD_INSN, reg, addr, handler)
 366 #define STOREB(reg, addr, handler)      EXC(sb, ST_INSN, reg, addr, handler)
 367 #define STOREL(reg, addr, handler)      EXC(sdl, ST_INSN, reg, addr, handler)
 368 #define STORER(reg, addr, handler)      EXC(sdr, ST_INSN, reg, addr, handler)
 369 #define STORE(reg, addr, handler)       EXC(sd, ST_INSN, reg, addr, handler)
 370 #define ADD    daddu
 371 #define SUB    dsubu
 372 #define SRL    dsrl
 373 #define SLL    dsll
 374 #define SLLV   dsllv
 375 #define SRLV   dsrlv
 376 #define NBYTES 8
 377 #define LOG_NBYTES 3
 378
 379 #else
 380
 381 #define LOADK   lw /* No exception */
 382 #define LOAD(reg, addr, handler)        EXC(lw, LD_INSN, reg, addr, handler)
 383 #define LOADBU(reg, addr, handler)      EXC(lbu, LD_INSN, reg, addr, handler)
 384 #define LOADL(reg, addr, handler)       EXC(lwl, LD_INSN, reg, addr, handler)
 385 #define LOADR(reg, addr, handler)       EXC(lwr, LD_INSN, reg, addr, handler)
 386 #define STOREB(reg, addr, handler)      EXC(sb, ST_INSN, reg, addr, handler)
 387 #define STOREL(reg, addr, handler)      EXC(swl, ST_INSN, reg, addr, handler)
 388 #define STORER(reg, addr, handler)      EXC(swr, ST_INSN, reg, addr, handler)
 389 #define STORE(reg, addr, handler)       EXC(sw, ST_INSN, reg, addr, handler)
 390 #define ADD    addu
 391 #define SUB    subu
 392 #define SRL    srl
 393 #define SLL    sll
 394 #define SLLV   sllv
 395 #define SRLV   srlv
 396 #define NBYTES 4
 397 #define LOG_NBYTES 2
 398
 399 #endif /* USE_DOUBLE */
 400
 401 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 402 #define LDFIRST LOADR
 403 #define LDREST  LOADL
 404 #define STFIRST STORER
 405 #define STREST  STOREL
 406 #define SHIFT_DISCARD SLLV
 407 #define SHIFT_DISCARD_REVERT SRLV
 408 #else
 409 #define LDFIRST LOADL
 410 #define LDREST  LOADR
 411 #define STFIRST STOREL
 412 #define STREST  STORER
 413 #define SHIFT_DISCARD SRLV
 414 #define SHIFT_DISCARD_REVERT SLLV
 415 #endif
 416
 417 #define FIRST(unit) ((unit)*NBYTES)
 418 #define REST(unit)  (FIRST(unit)+NBYTES-1)
 419
 420 #define ADDRMASK (NBYTES-1)
 421
 422 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
 423         .set    noat
 424 #else
 425         .set    at=v1
 426 #endif
 427
 428         .macro __BUILD_CSUM_PARTIAL_COPY_USER mode, from, to, __nocheck
 429
 430         PTR_ADDU        AT, src, len    /* See (1) above. */
 431         /* initialize __nocheck if this the first time we execute this
 432          * macro
 433          */
 434 #ifdef CONFIG_64BIT
 435         move    errptr, a4
 436 #else
 437         lw      errptr, 16(sp)
 438 #endif
 439         .if \__nocheck == 1
 440         FEXPORT(csum_partial_copy_nocheck)
 441         .endif
 442         move    sum, zero
 443         move    odd, zero
 444         /*
 445          * Note: dst & src may be unaligned, len may be 0
 446          * Temps
 447          */
 448         /*
 449          * The "issue break"s below are very approximate.
 450          * Issue delays for dcache fills will perturb the schedule, as will
 451          * load queue full replay traps, etc.
 452          *
 453          * If len < NBYTES use byte operations.
 454          */
 455         sltu    t2, len, NBYTES
 456         and     t1, dst, ADDRMASK
 457         bnez    t2, .Lcopy_bytes_checklen\@
 458          and    t0, src, ADDRMASK
 459         andi    odd, dst, 0x1                   /* odd buffer? */
 460         bnez    t1, .Ldst_unaligned\@
 461          nop
 462         bnez    t0, .Lsrc_unaligned_dst_aligned\@
 463         /*
 464          * use delay slot for fall-through
 465          * src and dst are aligned; need to compute rem
 466          */
 467 .Lboth_aligned\@:
 468          SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
 469         beqz    t0, .Lcleanup_both_aligned\@ # len < 8*NBYTES
 470          nop
 471         SUB     len, 8*NBYTES           # subtract here for bgez loop
 472         .align  4
 473 1:
 474         LOAD(t0, UNIT(0)(src), .Ll_exc\@)
 475         LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
 476         LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
 477         LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
 478         LOAD(t4, UNIT(4)(src), .Ll_exc_copy\@)
 479         LOAD(t5, UNIT(5)(src), .Ll_exc_copy\@)
 480         LOAD(t6, UNIT(6)(src), .Ll_exc_copy\@)
 481         LOAD(t7, UNIT(7)(src), .Ll_exc_copy\@)
 482         SUB     len, len, 8*NBYTES
 483         ADD     src, src, 8*NBYTES
 484         STORE(t0, UNIT(0)(dst), .Ls_exc\@)
 485         ADDC(sum, t0)
 486         STORE(t1, UNIT(1)(dst), .Ls_exc\@)
 487         ADDC(sum, t1)
 488         STORE(t2, UNIT(2)(dst), .Ls_exc\@)
 489         ADDC(sum, t2)
 490         STORE(t3, UNIT(3)(dst), .Ls_exc\@)
 491         ADDC(sum, t3)
 492         STORE(t4, UNIT(4)(dst), .Ls_exc\@)
 493         ADDC(sum, t4)
 494         STORE(t5, UNIT(5)(dst), .Ls_exc\@)
 495         ADDC(sum, t5)
 496         STORE(t6, UNIT(6)(dst), .Ls_exc\@)
 497         ADDC(sum, t6)
 498         STORE(t7, UNIT(7)(dst), .Ls_exc\@)
 499         ADDC(sum, t7)
 500         .set    reorder                         /* DADDI_WAR */
 501         ADD     dst, dst, 8*NBYTES
 502         bgez    len, 1b
 503         .set    noreorder
 504         ADD     len, 8*NBYTES           # revert len (see above)
 505
 506         /*
 507          * len == the number of bytes left to copy < 8*NBYTES
 508          */
 509 .Lcleanup_both_aligned\@:
 510 #define rem t7
 511         beqz    len, .Ldone\@
 512          sltu   t0, len, 4*NBYTES
 513         bnez    t0, .Lless_than_4units\@
 514          and    rem, len, (NBYTES-1)    # rem = len % NBYTES
 515         /*
 516          * len >= 4*NBYTES
 517          */
 518         LOAD(t0, UNIT(0)(src), .Ll_exc\@)
 519         LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
 520         LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
 521         LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
 522         SUB     len, len, 4*NBYTES
 523         ADD     src, src, 4*NBYTES
 524         STORE(t0, UNIT(0)(dst), .Ls_exc\@)
 525         ADDC(sum, t0)
 526         STORE(t1, UNIT(1)(dst), .Ls_exc\@)
 527         ADDC(sum, t1)
 528         STORE(t2, UNIT(2)(dst), .Ls_exc\@)
 529         ADDC(sum, t2)
 530         STORE(t3, UNIT(3)(dst), .Ls_exc\@)
 531         ADDC(sum, t3)
 532         .set    reorder                         /* DADDI_WAR */
 533         ADD     dst, dst, 4*NBYTES
 534         beqz    len, .Ldone\@
 535         .set    noreorder
 536 .Lless_than_4units\@:
 537         /*
 538          * rem = len % NBYTES
 539          */
 540         beq     rem, len, .Lcopy_bytes\@
 541          nop
 542 1:
 543         LOAD(t0, 0(src), .Ll_exc\@)
 544         ADD     src, src, NBYTES
 545         SUB     len, len, NBYTES
 546         STORE(t0, 0(dst), .Ls_exc\@)
 547         ADDC(sum, t0)
 548         .set    reorder                         /* DADDI_WAR */
 549         ADD     dst, dst, NBYTES
 550         bne     rem, len, 1b
 551         .set    noreorder
 552
 553         /*
 554          * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
 555          * A loop would do only a byte at a time with possible branch
 556          * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
 557          * because can't assume read-access to dst.  Instead, use
 558          * STREST dst, which doesn't require read access to dst.
 559          *
 560          * This code should perform better than a simple loop on modern,
 561          * wide-issue mips processors because the code has fewer branches and
 562          * more instruction-level parallelism.
 563          */
 564 #define bits t2
 565         beqz    len, .Ldone\@
 566          ADD    t1, dst, len    # t1 is just past last byte of dst
 567         li      bits, 8*NBYTES
 568         SLL     rem, len, 3     # rem = number of bits to keep
 569         LOAD(t0, 0(src), .Ll_exc\@)
 570         SUB     bits, bits, rem # bits = number of bits to discard
 571         SHIFT_DISCARD t0, t0, bits
 572         STREST(t0, -1(t1), .Ls_exc\@)
 573         SHIFT_DISCARD_REVERT t0, t0, bits
 574         .set reorder
 575         ADDC(sum, t0)
 576         b       .Ldone\@
 577         .set noreorder
 578 .Ldst_unaligned\@:
 579         /*
 580          * dst is unaligned
 581          * t0 = src & ADDRMASK
 582          * t1 = dst & ADDRMASK; T1 > 0
 583          * len >= NBYTES
 584          *
 585          * Copy enough bytes to align dst
 586          * Set match = (src and dst have same alignment)
 587          */
 588 #define match rem
 589         LDFIRST(t3, FIRST(0)(src), .Ll_exc\@)
 590         ADD     t2, zero, NBYTES
 591         LDREST(t3, REST(0)(src), .Ll_exc_copy\@)
 592         SUB     t2, t2, t1      # t2 = number of bytes copied
 593         xor     match, t0, t1
 594         STFIRST(t3, FIRST(0)(dst), .Ls_exc\@)
 595         SLL     t4, t1, 3               # t4 = number of bits to discard
 596         SHIFT_DISCARD t3, t3, t4
 597         /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
 598         ADDC(sum, t3)
 599         beq     len, t2, .Ldone\@
 600          SUB    len, len, t2
 601         ADD     dst, dst, t2
 602         beqz    match, .Lboth_aligned\@
 603          ADD    src, src, t2
 604
 605 .Lsrc_unaligned_dst_aligned\@:
 606         SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
 607         beqz    t0, .Lcleanup_src_unaligned\@
 608          and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
 609 1:
 610 /*
 611  * Avoid consecutive LD*'s to the same register since some mips
 612  * implementations can't issue them in the same cycle.
 613  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
 614  * are to the same unit (unless src is aligned, but it's not).
 615  */
 616         LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
 617         LDFIRST(t1, FIRST(1)(src), .Ll_exc_copy\@)
 618         SUB     len, len, 4*NBYTES
 619         LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
 620         LDREST(t1, REST(1)(src), .Ll_exc_copy\@)
 621         LDFIRST(t2, FIRST(2)(src), .Ll_exc_copy\@)
 622         LDFIRST(t3, FIRST(3)(src), .Ll_exc_copy\@)
 623         LDREST(t2, REST(2)(src), .Ll_exc_copy\@)
 624         LDREST(t3, REST(3)(src), .Ll_exc_copy\@)
 625         ADD     src, src, 4*NBYTES
 626 #ifdef CONFIG_CPU_SB1
 627         nop                             # improves slotting
 628 #endif
 629         STORE(t0, UNIT(0)(dst), .Ls_exc\@)
 630         ADDC(sum, t0)
 631         STORE(t1, UNIT(1)(dst), .Ls_exc\@)
 632         ADDC(sum, t1)
 633         STORE(t2, UNIT(2)(dst), .Ls_exc\@)
 634         ADDC(sum, t2)
 635         STORE(t3, UNIT(3)(dst), .Ls_exc\@)
 636         ADDC(sum, t3)
 637         .set    reorder                         /* DADDI_WAR */
 638         ADD     dst, dst, 4*NBYTES
 639         bne     len, rem, 1b
 640         .set    noreorder
 641
 642 .Lcleanup_src_unaligned\@:
 643         beqz    len, .Ldone\@
 644          and    rem, len, NBYTES-1  # rem = len % NBYTES
 645         beq     rem, len, .Lcopy_bytes\@
 646          nop
 647 1:
 648         LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
 649         LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
 650         ADD     src, src, NBYTES
 651         SUB     len, len, NBYTES
 652         STORE(t0, 0(dst), .Ls_exc\@)
 653         ADDC(sum, t0)
 654         .set    reorder                         /* DADDI_WAR */
 655         ADD     dst, dst, NBYTES
 656         bne     len, rem, 1b
 657         .set    noreorder
 658
 659 .Lcopy_bytes_checklen\@:
 660         beqz    len, .Ldone\@
 661          nop
 662 .Lcopy_bytes\@:
 663         /* 0 < len < NBYTES  */
 664 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 665 #define SHIFT_START 0
 666 #define SHIFT_INC 8
 667 #else
 668 #define SHIFT_START 8*(NBYTES-1)
 669 #define SHIFT_INC -8
 670 #endif
 671         move    t2, zero        # partial word
 672         li      t3, SHIFT_START # shift
 673 /* use .Ll_exc_copy here to return correct sum on fault */
 674 #define COPY_BYTE(N)                    \
 675         LOADBU(t0, N(src), .Ll_exc_copy\@);     \
 676         SUB     len, len, 1;            \
 677         STOREB(t0, N(dst), .Ls_exc\@);  \
 678         SLLV    t0, t0, t3;             \
 679         addu    t3, SHIFT_INC;          \
 680         beqz    len, .Lcopy_bytes_done\@; \
 681          or     t2, t0
 682
 683         COPY_BYTE(0)
 684         COPY_BYTE(1)
 685 #ifdef USE_DOUBLE
 686         COPY_BYTE(2)
 687         COPY_BYTE(3)
 688         COPY_BYTE(4)
 689         COPY_BYTE(5)
 690 #endif
 691         LOADBU(t0, NBYTES-2(src), .Ll_exc_copy\@)
 692         SUB     len, len, 1
 693         STOREB(t0, NBYTES-2(dst), .Ls_exc\@)
 694         SLLV    t0, t0, t3
 695         or      t2, t0
 696 .Lcopy_bytes_done\@:
 697         ADDC(sum, t2)
 698 .Ldone\@:
 699         /* fold checksum */
 700 #ifdef USE_DOUBLE
 701         dsll32  v1, sum, 0
 702         daddu   sum, v1
 703         sltu    v1, sum, v1
 704         dsra32  sum, sum, 0
 705         addu    sum, v1
 706 #endif
 707
 708 #ifdef CONFIG_CPU_MIPSR2
 709         wsbh    v1, sum
 710         movn    sum, v1, odd
 711 #else
 712         beqz    odd, 1f                 /* odd buffer alignment? */
 713          lui    v1, 0x00ff
 714         addu    v1, 0x00ff
 715         and     t0, sum, v1
 716         sll     t0, t0, 8
 717         srl     sum, sum, 8
 718         and     sum, sum, v1
 719         or      sum, sum, t0
 720 1:
 721 #endif
 722         .set reorder
 723         ADDC32(sum, psum)
 724         jr      ra
 725         .set noreorder
 726
 727 .Ll_exc_copy\@:
 728         /*
 729          * Copy bytes from src until faulting load address (or until a
 730          * lb faults)
 731          *
 732          * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
 733          * may be more than a byte beyond the last address.
 734          * Hence, the lb below may get an exception.
 735          *
 736          * Assumes src < THREAD_BUADDR($28)
 737          */
 738         LOADK   t0, TI_TASK($28)
 739          li     t2, SHIFT_START
 740         LOADK   t0, THREAD_BUADDR(t0)
 741 1:
 742         LOADBU(t1, 0(src), .Ll_exc\@)
 743         ADD     src, src, 1
 744         sb      t1, 0(dst)      # can't fault -- we're copy_from_user
 745         SLLV    t1, t1, t2
 746         addu    t2, SHIFT_INC
 747         ADDC(sum, t1)
 748         .set    reorder                         /* DADDI_WAR */
 749         ADD     dst, dst, 1
 750         bne     src, t0, 1b
 751         .set    noreorder
 752 .Ll_exc\@:
 753         LOADK   t0, TI_TASK($28)
 754          nop
 755         LOADK   t0, THREAD_BUADDR(t0)   # t0 is just past last good address
 756          nop
 757         SUB     len, AT, t0             # len number of uncopied bytes
 758         /*
 759          * Here's where we rely on src and dst being incremented in tandem,
 760          *   See (3) above.
 761          * dst += (fault addr - src) to put dst at first byte to clear
 762          */
 763         ADD     dst, t0                 # compute start address in a1
 764         SUB     dst, src
 765         /*
 766          * Clear len bytes starting at dst.  Can't call __bzero because it
 767          * might modify len.  An inefficient loop for these rare times...
 768          */
 769         .set    reorder                         /* DADDI_WAR */
 770         SUB     src, len, 1
 771         beqz    len, .Ldone\@
 772         .set    noreorder
 773 1:      sb      zero, 0(dst)
 774         ADD     dst, dst, 1
 775         .set    push
 776         .set    noat
 777 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
 778         bnez    src, 1b
 779          SUB    src, src, 1
 780 #else
 781         li      v1, 1
 782         bnez    src, 1b
 783          SUB    src, src, v1
 784 #endif
 785         li      v1, -EFAULT
 786         b       .Ldone\@
 787          sw     v1, (errptr)
 788
 789 .Ls_exc\@:
 790         li      v0, -1 /* invalid checksum */
 791         li      v1, -EFAULT
 792         jr      ra
 793          sw     v1, (errptr)
 794         .set    pop
 795         .endm
 796
 797 LEAF(__csum_partial_copy_kernel)
 798 FEXPORT(__csum_partial_copy_to_user)
 799 FEXPORT(__csum_partial_copy_from_user)
 800 __BUILD_CSUM_PARTIAL_COPY_USER LEGACY_MODE USEROP USEROP 1
 801 END(__csum_partial_copy_kernel)