1 #include <linux/init.h>
3 #include <linux/percpu.h>
4 #include <linux/delay.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
11 #define SMBUS_CFG_BASE (loongson_sysconf.ht_control_base + 0x0300a000)
12 #define SMBUS_PCI_REG40 0x40
13 #define SMBUS_PCI_REG64 0x64
14 #define SMBUS_PCI_REGB4 0xb4
16 #define HPET_MIN_CYCLES 64
17 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
19 static DEFINE_SPINLOCK(hpet_lock
);
20 DEFINE_PER_CPU(struct clock_event_device
, hpet_clockevent_device
);
22 static unsigned int smbus_read(int offset
)
24 return *(volatile unsigned int *)(SMBUS_CFG_BASE
+ offset
);
27 static void smbus_write(int offset
, int data
)
29 *(volatile unsigned int *)(SMBUS_CFG_BASE
+ offset
) = data
;
32 static void smbus_enable(int offset
, int bit
)
34 unsigned int cfg
= smbus_read(offset
);
37 smbus_write(offset
, cfg
);
40 static int hpet_read(int offset
)
42 return *(volatile unsigned int *)(HPET_MMIO_ADDR
+ offset
);
45 static void hpet_write(int offset
, int data
)
47 *(volatile unsigned int *)(HPET_MMIO_ADDR
+ offset
) = data
;
50 static void hpet_start_counter(void)
52 unsigned int cfg
= hpet_read(HPET_CFG
);
54 cfg
|= HPET_CFG_ENABLE
;
55 hpet_write(HPET_CFG
, cfg
);
58 static void hpet_stop_counter(void)
60 unsigned int cfg
= hpet_read(HPET_CFG
);
62 cfg
&= ~HPET_CFG_ENABLE
;
63 hpet_write(HPET_CFG
, cfg
);
66 static void hpet_reset_counter(void)
68 hpet_write(HPET_COUNTER
, 0);
69 hpet_write(HPET_COUNTER
+ 4, 0);
72 static void hpet_restart_counter(void)
79 static void hpet_enable_legacy_int(void)
81 /* Do nothing on Loongson-3 */
84 static int hpet_set_state_periodic(struct clock_event_device
*evt
)
88 spin_lock(&hpet_lock
);
90 pr_info("set clock event to periodic mode!\n");
94 /* enables the timer0 to generate a periodic interrupt */
95 cfg
= hpet_read(HPET_T0_CFG
);
96 cfg
&= ~HPET_TN_LEVEL
;
97 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
| HPET_TN_SETVAL
|
99 hpet_write(HPET_T0_CFG
, cfg
);
101 /* set the comparator */
102 hpet_write(HPET_T0_CMP
, HPET_COMPARE_VAL
);
104 hpet_write(HPET_T0_CMP
, HPET_COMPARE_VAL
);
107 hpet_start_counter();
109 spin_unlock(&hpet_lock
);
113 static int hpet_set_state_shutdown(struct clock_event_device
*evt
)
117 spin_lock(&hpet_lock
);
119 cfg
= hpet_read(HPET_T0_CFG
);
120 cfg
&= ~HPET_TN_ENABLE
;
121 hpet_write(HPET_T0_CFG
, cfg
);
123 spin_unlock(&hpet_lock
);
127 static int hpet_set_state_oneshot(struct clock_event_device
*evt
)
131 spin_lock(&hpet_lock
);
133 pr_info("set clock event to one shot mode!\n");
134 cfg
= hpet_read(HPET_T0_CFG
);
137 * 1 : periodic interrupt
138 * 0 : non-periodic(oneshot) interrupt
140 cfg
&= ~HPET_TN_PERIODIC
;
141 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
142 hpet_write(HPET_T0_CFG
, cfg
);
144 spin_unlock(&hpet_lock
);
148 static int hpet_tick_resume(struct clock_event_device
*evt
)
150 spin_lock(&hpet_lock
);
151 hpet_enable_legacy_int();
152 spin_unlock(&hpet_lock
);
157 static int hpet_next_event(unsigned long delta
,
158 struct clock_event_device
*evt
)
163 cnt
= hpet_read(HPET_COUNTER
);
165 hpet_write(HPET_T0_CMP
, cnt
);
167 res
= (int)(cnt
- hpet_read(HPET_COUNTER
));
169 return res
< HPET_MIN_CYCLES
? -ETIME
: 0;
172 static irqreturn_t
hpet_irq_handler(int irq
, void *data
)
175 struct clock_event_device
*cd
;
176 unsigned int cpu
= smp_processor_id();
178 is_irq
= hpet_read(HPET_STATUS
);
179 if (is_irq
& HPET_T0_IRS
) {
180 /* clear the TIMER0 irq status register */
181 hpet_write(HPET_STATUS
, HPET_T0_IRS
);
182 cd
= &per_cpu(hpet_clockevent_device
, cpu
);
183 cd
->event_handler(cd
);
189 static struct irqaction hpet_irq
= {
190 .handler
= hpet_irq_handler
,
191 .flags
= IRQF_NOBALANCING
| IRQF_TIMER
,
196 * hpet address assignation and irq setting should be done in bios.
197 * but pmon don't do this, we just setup here directly.
198 * The operation under is normal. unfortunately, hpet_setup process
199 * is before pci initialize.
202 * struct pci_dev *pdev;
204 * pdev = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
205 * pci_write_config_word(pdev, SMBUS_PCI_REGB4, HPET_ADDR);
210 static void hpet_setup(void)
212 /* set hpet base address */
213 smbus_write(SMBUS_PCI_REGB4
, HPET_ADDR
);
215 /* enable decodeing of access to HPET MMIO*/
216 smbus_enable(SMBUS_PCI_REG40
, (1 << 28));
218 /* HPET irq enable */
219 smbus_enable(SMBUS_PCI_REG64
, (1 << 10));
221 hpet_enable_legacy_int();
224 void __init
setup_hpet_timer(void)
226 unsigned int cpu
= smp_processor_id();
227 struct clock_event_device
*cd
;
231 cd
= &per_cpu(hpet_clockevent_device
, cpu
);
234 cd
->features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
;
235 cd
->set_state_shutdown
= hpet_set_state_shutdown
;
236 cd
->set_state_periodic
= hpet_set_state_periodic
;
237 cd
->set_state_oneshot
= hpet_set_state_oneshot
;
238 cd
->tick_resume
= hpet_tick_resume
;
239 cd
->set_next_event
= hpet_next_event
;
240 cd
->irq
= HPET_T0_IRQ
;
241 cd
->cpumask
= cpumask_of(cpu
);
242 clockevent_set_clock(cd
, HPET_FREQ
);
243 cd
->max_delta_ns
= clockevent_delta2ns(0x7fffffff, cd
);
244 cd
->min_delta_ns
= clockevent_delta2ns(HPET_MIN_PROG_DELTA
, cd
);
246 clockevents_register_device(cd
);
247 setup_irq(HPET_T0_IRQ
, &hpet_irq
);
248 pr_info("hpet clock event device register\n");
251 static cycle_t
hpet_read_counter(struct clocksource
*cs
)
253 return (cycle_t
)hpet_read(HPET_COUNTER
);
256 static void hpet_suspend(struct clocksource
*cs
)
260 static void hpet_resume(struct clocksource
*cs
)
263 hpet_restart_counter();
266 static struct clocksource csrc_hpet
= {
268 /* mips clocksource rating is less than 300, so hpet is better. */
270 .read
= hpet_read_counter
,
271 .mask
= CLOCKSOURCE_MASK(32),
272 /* oneshot mode work normal with this flag */
273 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
274 .suspend
= hpet_suspend
,
275 .resume
= hpet_resume
,
280 int __init
init_hpet_clocksource(void)
282 csrc_hpet
.mult
= clocksource_hz2mult(HPET_FREQ
, csrc_hpet
.shift
);
283 return clocksource_register_hz(&csrc_hpet
, HPET_FREQ
);
286 arch_initcall(init_hpet_clocksource
);