2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
51 #include <asm/mips-r2-to-r6-emul.h>
55 /* Function which emulates a floating point instruction. */
57 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
60 static int fpux_emu(struct pt_regs
*,
61 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
63 /* Control registers */
65 #define FPCREG_RID 0 /* $0 = revision id */
66 #define FPCREG_CSR 31 /* $31 = csr */
68 /* Determine rounding mode from the RM bits of the FCSR */
69 #define modeindex(v) ((v) & FPU_CSR_RM)
71 /* convert condition code register number to csr bit */
72 const unsigned int fpucondbit
[8] = {
83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
84 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
85 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
86 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
87 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
90 * This functions translates a 32-bit microMIPS instruction
91 * into a 32-bit MIPS32 instruction. Returns 0 on success
92 * and SIGILL otherwise.
94 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
96 union mips_instruction insn
= *insn_ptr
;
97 union mips_instruction mips32_insn
= insn
;
100 switch (insn
.mm_i_format
.opcode
) {
102 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
103 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
104 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
107 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
108 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
109 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
112 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
113 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
114 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
117 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
118 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
119 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
122 /* NOTE: offset is << by 1 if in microMIPS mode. */
123 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
124 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
125 mips32_insn
.fb_format
.opcode
= cop1_op
;
126 mips32_insn
.fb_format
.bc
= bc_op
;
127 mips32_insn
.fb_format
.flag
=
128 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
133 switch (insn
.mm_fp0_format
.func
) {
142 op
= insn
.mm_fp0_format
.func
;
143 if (op
== mm_32f_01_op
)
145 else if (op
== mm_32f_11_op
)
147 else if (op
== mm_32f_02_op
)
149 else if (op
== mm_32f_12_op
)
151 else if (op
== mm_32f_41_op
)
153 else if (op
== mm_32f_51_op
)
155 else if (op
== mm_32f_42_op
)
159 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
160 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
161 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
162 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
163 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
164 mips32_insn
.fp6_format
.func
= func
;
167 func
= -1; /* Invalid */
168 op
= insn
.mm_fp5_format
.op
& 0x7;
169 if (op
== mm_ldxc1_op
)
171 else if (op
== mm_sdxc1_op
)
173 else if (op
== mm_lwxc1_op
)
175 else if (op
== mm_swxc1_op
)
179 mips32_insn
.r_format
.opcode
= cop1x_op
;
180 mips32_insn
.r_format
.rs
=
181 insn
.mm_fp5_format
.base
;
182 mips32_insn
.r_format
.rt
=
183 insn
.mm_fp5_format
.index
;
184 mips32_insn
.r_format
.rd
= 0;
185 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
186 mips32_insn
.r_format
.func
= func
;
191 op
= -1; /* Invalid */
192 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
194 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
197 mips32_insn
.fp0_format
.opcode
= cop1_op
;
198 mips32_insn
.fp0_format
.fmt
=
199 sdps_format
[insn
.mm_fp2_format
.fmt
];
200 mips32_insn
.fp0_format
.ft
=
201 (insn
.mm_fp2_format
.cc
<<2) + op
;
202 mips32_insn
.fp0_format
.fs
=
203 insn
.mm_fp2_format
.fs
;
204 mips32_insn
.fp0_format
.fd
=
205 insn
.mm_fp2_format
.fd
;
206 mips32_insn
.fp0_format
.func
= fmovc_op
;
211 func
= -1; /* Invalid */
212 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
214 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
216 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
218 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
221 mips32_insn
.fp0_format
.opcode
= cop1_op
;
222 mips32_insn
.fp0_format
.fmt
=
223 sdps_format
[insn
.mm_fp0_format
.fmt
];
224 mips32_insn
.fp0_format
.ft
=
225 insn
.mm_fp0_format
.ft
;
226 mips32_insn
.fp0_format
.fs
=
227 insn
.mm_fp0_format
.fs
;
228 mips32_insn
.fp0_format
.fd
=
229 insn
.mm_fp0_format
.fd
;
230 mips32_insn
.fp0_format
.func
= func
;
235 func
= -1; /* Invalid */
236 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
238 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
241 mips32_insn
.fp0_format
.opcode
= cop1_op
;
242 mips32_insn
.fp0_format
.fmt
=
243 sdps_format
[insn
.mm_fp0_format
.fmt
];
244 mips32_insn
.fp0_format
.ft
=
245 insn
.mm_fp0_format
.ft
;
246 mips32_insn
.fp0_format
.fs
=
247 insn
.mm_fp0_format
.fs
;
248 mips32_insn
.fp0_format
.fd
=
249 insn
.mm_fp0_format
.fd
;
250 mips32_insn
.fp0_format
.func
= func
;
254 case mm_32f_73_op
: /* POOL32FXF */
255 switch (insn
.mm_fp1_format
.op
) {
260 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
265 mips32_insn
.r_format
.opcode
= spec_op
;
266 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
267 mips32_insn
.r_format
.rt
=
268 (insn
.mm_fp4_format
.cc
<< 2) + op
;
269 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
270 mips32_insn
.r_format
.re
= 0;
271 mips32_insn
.r_format
.func
= movc_op
;
277 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
280 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
283 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
285 mips32_insn
.fp0_format
.opcode
= cop1_op
;
286 mips32_insn
.fp0_format
.fmt
= fmt
;
287 mips32_insn
.fp0_format
.ft
= 0;
288 mips32_insn
.fp0_format
.fs
=
289 insn
.mm_fp3_format
.fs
;
290 mips32_insn
.fp0_format
.fd
=
291 insn
.mm_fp3_format
.rt
;
292 mips32_insn
.fp0_format
.func
= func
;
300 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
303 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
308 mips32_insn
.fp0_format
.opcode
= cop1_op
;
309 mips32_insn
.fp0_format
.fmt
=
310 sdps_format
[insn
.mm_fp3_format
.fmt
];
311 mips32_insn
.fp0_format
.ft
= 0;
312 mips32_insn
.fp0_format
.fs
=
313 insn
.mm_fp3_format
.fs
;
314 mips32_insn
.fp0_format
.fd
=
315 insn
.mm_fp3_format
.rt
;
316 mips32_insn
.fp0_format
.func
= func
;
328 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
330 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
332 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
334 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
336 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
338 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
340 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
342 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
344 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
348 mips32_insn
.fp0_format
.opcode
= cop1_op
;
349 mips32_insn
.fp0_format
.fmt
=
350 sd_format
[insn
.mm_fp1_format
.fmt
];
351 mips32_insn
.fp0_format
.ft
= 0;
352 mips32_insn
.fp0_format
.fs
=
353 insn
.mm_fp1_format
.fs
;
354 mips32_insn
.fp0_format
.fd
=
355 insn
.mm_fp1_format
.rt
;
356 mips32_insn
.fp0_format
.func
= func
;
361 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
363 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
367 mips32_insn
.fp0_format
.opcode
= cop1_op
;
368 mips32_insn
.fp0_format
.fmt
=
369 sdps_format
[insn
.mm_fp1_format
.fmt
];
370 mips32_insn
.fp0_format
.ft
= 0;
371 mips32_insn
.fp0_format
.fs
=
372 insn
.mm_fp1_format
.fs
;
373 mips32_insn
.fp0_format
.fd
=
374 insn
.mm_fp1_format
.rt
;
375 mips32_insn
.fp0_format
.func
= func
;
383 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
385 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
387 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
389 else if (insn
.mm_fp1_format
.op
== mm_ctc1_op
)
391 else if (insn
.mm_fp1_format
.op
== mm_mfhc1_op
)
395 mips32_insn
.fp1_format
.opcode
= cop1_op
;
396 mips32_insn
.fp1_format
.op
= op
;
397 mips32_insn
.fp1_format
.rt
=
398 insn
.mm_fp1_format
.rt
;
399 mips32_insn
.fp1_format
.fs
=
400 insn
.mm_fp1_format
.fs
;
401 mips32_insn
.fp1_format
.fd
= 0;
402 mips32_insn
.fp1_format
.func
= 0;
408 case mm_32f_74_op
: /* c.cond.fmt */
409 mips32_insn
.fp0_format
.opcode
= cop1_op
;
410 mips32_insn
.fp0_format
.fmt
=
411 sdps_format
[insn
.mm_fp4_format
.fmt
];
412 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
413 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
414 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
415 mips32_insn
.fp0_format
.func
=
416 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
426 *insn_ptr
= mips32_insn
;
431 * Redundant with logic already in kernel/branch.c,
432 * embedded in compute_return_epc. At some point,
433 * a single subroutine should be used across both
436 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
437 unsigned long *contpc
)
439 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
441 unsigned int bit
= 0;
443 switch (insn
.i_format
.opcode
) {
445 switch (insn
.r_format
.func
) {
447 regs
->regs
[insn
.r_format
.rd
] =
448 regs
->cp0_epc
+ dec_insn
.pc_inc
+
449 dec_insn
.next_pc_inc
;
452 /* For R6, JR already emulated in jalr_op */
453 if (NO_R6EMU
&& insn
.r_format
.opcode
== jr_op
)
455 *contpc
= regs
->regs
[insn
.r_format
.rs
];
460 switch (insn
.i_format
.rt
) {
463 if (NO_R6EMU
&& (insn
.i_format
.rs
||
464 insn
.i_format
.rt
== bltzall_op
))
467 regs
->regs
[31] = regs
->cp0_epc
+
469 dec_insn
.next_pc_inc
;
475 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
476 *contpc
= regs
->cp0_epc
+
478 (insn
.i_format
.simmediate
<< 2);
480 *contpc
= regs
->cp0_epc
+
482 dec_insn
.next_pc_inc
;
486 if (NO_R6EMU
&& (insn
.i_format
.rs
||
487 insn
.i_format
.rt
== bgezall_op
))
490 regs
->regs
[31] = regs
->cp0_epc
+
492 dec_insn
.next_pc_inc
;
498 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
499 *contpc
= regs
->cp0_epc
+
501 (insn
.i_format
.simmediate
<< 2);
503 *contpc
= regs
->cp0_epc
+
505 dec_insn
.next_pc_inc
;
512 regs
->regs
[31] = regs
->cp0_epc
+
514 dec_insn
.next_pc_inc
;
517 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
520 *contpc
|= (insn
.j_format
.target
<< 2);
521 /* Set microMIPS mode bit: XOR for jalx. */
528 if (regs
->regs
[insn
.i_format
.rs
] ==
529 regs
->regs
[insn
.i_format
.rt
])
530 *contpc
= regs
->cp0_epc
+
532 (insn
.i_format
.simmediate
<< 2);
534 *contpc
= regs
->cp0_epc
+
536 dec_insn
.next_pc_inc
;
542 if (regs
->regs
[insn
.i_format
.rs
] !=
543 regs
->regs
[insn
.i_format
.rt
])
544 *contpc
= regs
->cp0_epc
+
546 (insn
.i_format
.simmediate
<< 2);
548 *contpc
= regs
->cp0_epc
+
550 dec_insn
.next_pc_inc
;
558 * Compact branches for R6 for the
559 * blez and blezl opcodes.
560 * BLEZ | rs = 0 | rt != 0 == BLEZALC
561 * BLEZ | rs = rt != 0 == BGEZALC
562 * BLEZ | rs != 0 | rt != 0 == BGEUC
563 * BLEZL | rs = 0 | rt != 0 == BLEZC
564 * BLEZL | rs = rt != 0 == BGEZC
565 * BLEZL | rs != 0 | rt != 0 == BGEC
567 * For real BLEZ{,L}, rt is always 0.
569 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
570 if ((insn
.i_format
.opcode
== blez_op
) &&
571 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
572 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
573 regs
->regs
[31] = regs
->cp0_epc
+
575 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
576 dec_insn
.next_pc_inc
;
580 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
581 *contpc
= regs
->cp0_epc
+
583 (insn
.i_format
.simmediate
<< 2);
585 *contpc
= regs
->cp0_epc
+
587 dec_insn
.next_pc_inc
;
594 * Compact branches for R6 for the
595 * bgtz and bgtzl opcodes.
596 * BGTZ | rs = 0 | rt != 0 == BGTZALC
597 * BGTZ | rs = rt != 0 == BLTZALC
598 * BGTZ | rs != 0 | rt != 0 == BLTUC
599 * BGTZL | rs = 0 | rt != 0 == BGTZC
600 * BGTZL | rs = rt != 0 == BLTZC
601 * BGTZL | rs != 0 | rt != 0 == BLTC
603 * *ZALC varint for BGTZ &&& rt != 0
604 * For real GTZ{,L}, rt is always 0.
606 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
607 if ((insn
.i_format
.opcode
== blez_op
) &&
608 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
609 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
610 regs
->regs
[31] = regs
->cp0_epc
+
612 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
613 dec_insn
.next_pc_inc
;
618 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
619 *contpc
= regs
->cp0_epc
+
621 (insn
.i_format
.simmediate
<< 2);
623 *contpc
= regs
->cp0_epc
+
625 dec_insn
.next_pc_inc
;
629 if (!cpu_has_mips_r6
)
631 if (insn
.i_format
.rt
&& !insn
.i_format
.rs
)
632 regs
->regs
[31] = regs
->cp0_epc
+ 4;
633 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
634 dec_insn
.next_pc_inc
;
637 #ifdef CONFIG_CPU_CAVIUM_OCTEON
638 case lwc2_op
: /* This is bbit0 on Octeon */
639 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
640 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
642 *contpc
= regs
->cp0_epc
+ 8;
644 case ldc2_op
: /* This is bbit032 on Octeon */
645 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
646 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
648 *contpc
= regs
->cp0_epc
+ 8;
650 case swc2_op
: /* This is bbit1 on Octeon */
651 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
652 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
654 *contpc
= regs
->cp0_epc
+ 8;
656 case sdc2_op
: /* This is bbit132 on Octeon */
657 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
658 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
660 *contpc
= regs
->cp0_epc
+ 8;
665 * Only valid for MIPS R6 but we can still end up
666 * here from a broken userland so just tell emulator
667 * this is not a branch and let it break later on.
669 if (!cpu_has_mips_r6
)
671 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
672 dec_insn
.next_pc_inc
;
676 if (!cpu_has_mips_r6
)
678 regs
->regs
[31] = regs
->cp0_epc
+ 4;
679 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
680 dec_insn
.next_pc_inc
;
684 if (!cpu_has_mips_r6
)
686 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
687 dec_insn
.next_pc_inc
;
691 if (!cpu_has_mips_r6
)
693 if (!insn
.i_format
.rs
)
694 regs
->regs
[31] = regs
->cp0_epc
+ 4;
695 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
696 dec_insn
.next_pc_inc
;
702 /* Need to check for R6 bc1nez and bc1eqz branches */
703 if (cpu_has_mips_r6
&&
704 ((insn
.i_format
.rs
== bc1eqz_op
) ||
705 (insn
.i_format
.rs
== bc1nez_op
))) {
707 switch (insn
.i_format
.rs
) {
709 if (get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1)
713 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1))
718 *contpc
= regs
->cp0_epc
+
720 (insn
.i_format
.simmediate
<< 2);
722 *contpc
= regs
->cp0_epc
+
724 dec_insn
.next_pc_inc
;
728 /* R2/R6 compatible cop1 instruction. Fall through */
731 if (insn
.i_format
.rs
== bc_op
) {
734 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
736 fcr31
= current
->thread
.fpu
.fcr31
;
739 bit
= (insn
.i_format
.rt
>> 2);
742 switch (insn
.i_format
.rt
& 3) {
745 if (~fcr31
& (1 << bit
))
746 *contpc
= regs
->cp0_epc
+
748 (insn
.i_format
.simmediate
<< 2);
750 *contpc
= regs
->cp0_epc
+
752 dec_insn
.next_pc_inc
;
756 if (fcr31
& (1 << bit
))
757 *contpc
= regs
->cp0_epc
+
759 (insn
.i_format
.simmediate
<< 2);
761 *contpc
= regs
->cp0_epc
+
763 dec_insn
.next_pc_inc
;
773 * In the Linux kernel, we support selection of FPR format on the
774 * basis of the Status.FR bit. If an FPU is not present, the FR bit
775 * is hardwired to zero, which would imply a 32-bit FPU even for
776 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
777 * FPU emu is slow and bulky and optimizing this function offers fairly
778 * sizeable benefits so we try to be clever and make this function return
779 * a constant whenever possible, that is on 64-bit kernels without O32
780 * compatibility enabled and on 32-bit without 64-bit FPU support.
782 static inline int cop1_64bit(struct pt_regs
*xcp
)
784 if (config_enabled(CONFIG_64BIT
) && !config_enabled(CONFIG_MIPS32_O32
))
786 else if (config_enabled(CONFIG_32BIT
) &&
787 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT
))
790 return !test_thread_flag(TIF_32BIT_FPREGS
);
793 static inline bool hybrid_fprs(void)
795 return test_thread_flag(TIF_HYBRID_FPREGS
);
798 #define SIFROMREG(si, x) \
800 if (cop1_64bit(xcp) && !hybrid_fprs()) \
801 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
803 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
806 #define SITOREG(si, x) \
808 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
810 set_fpr32(&ctx->fpr[x], 0, si); \
811 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
812 set_fpr32(&ctx->fpr[x], i, 0); \
814 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
818 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
820 #define SITOHREG(si, x) \
823 set_fpr32(&ctx->fpr[x], 1, si); \
824 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
825 set_fpr32(&ctx->fpr[x], i, 0); \
828 #define DIFROMREG(di, x) \
829 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
831 #define DITOREG(di, x) \
834 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
835 set_fpr64(&ctx->fpr[fpr], 0, di); \
836 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
837 set_fpr64(&ctx->fpr[fpr], i, 0); \
840 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
841 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
842 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
843 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
846 * Emulate the single floating point instruction pointed at by EPC.
847 * Two instructions if the instruction is in a branch delay slot.
850 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
851 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
853 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
854 unsigned int cond
, cbit
;
865 * These are giving gcc a gentle hint about what to expect in
866 * dec_inst in order to do better optimization.
868 if (!cpu_has_mmips
&& dec_insn
.micro_mips_mode
)
871 /* XXX NEC Vr54xx bug workaround */
872 if (delay_slot(xcp
)) {
873 if (dec_insn
.micro_mips_mode
) {
874 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
875 clear_delay_slot(xcp
);
877 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
878 clear_delay_slot(xcp
);
882 if (delay_slot(xcp
)) {
884 * The instruction to be emulated is in a branch delay slot
885 * which means that we have to emulate the branch instruction
886 * BEFORE we do the cop1 instruction.
888 * This branch could be a COP1 branch, but in that case we
889 * would have had a trap for that instruction, and would not
890 * come through this route.
892 * Linux MIPS branch emulator operates on context, updating the
895 ir
= dec_insn
.next_insn
; /* process delay slot instr */
896 pc_inc
= dec_insn
.next_pc_inc
;
898 ir
= dec_insn
.insn
; /* process current instr */
899 pc_inc
= dec_insn
.pc_inc
;
903 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
904 * instructions, we want to convert microMIPS FPU instructions
905 * into MIPS32 instructions so that we could reuse all of the
906 * FPU emulation code.
908 * NOTE: We cannot do this for branch instructions since they
909 * are not a subset. Example: Cannot emulate a 16-bit
910 * aligned target address with a MIPS32 instruction.
912 if (dec_insn
.micro_mips_mode
) {
914 * If next instruction is a 16-bit instruction, then it
915 * it cannot be a FPU instruction. This could happen
916 * since we can be called for non-FPU instructions.
919 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
925 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
926 MIPS_FPU_EMU_INC_STATS(emulated
);
927 switch (MIPSInst_OPCODE(ir
)) {
929 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
931 MIPS_FPU_EMU_INC_STATS(loads
);
933 if (!access_ok(VERIFY_READ
, dva
, sizeof(u64
))) {
934 MIPS_FPU_EMU_INC_STATS(errors
);
938 if (__get_user(dval
, dva
)) {
939 MIPS_FPU_EMU_INC_STATS(errors
);
943 DITOREG(dval
, MIPSInst_RT(ir
));
947 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
949 MIPS_FPU_EMU_INC_STATS(stores
);
950 DIFROMREG(dval
, MIPSInst_RT(ir
));
951 if (!access_ok(VERIFY_WRITE
, dva
, sizeof(u64
))) {
952 MIPS_FPU_EMU_INC_STATS(errors
);
956 if (__put_user(dval
, dva
)) {
957 MIPS_FPU_EMU_INC_STATS(errors
);
964 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
966 MIPS_FPU_EMU_INC_STATS(loads
);
967 if (!access_ok(VERIFY_READ
, wva
, sizeof(u32
))) {
968 MIPS_FPU_EMU_INC_STATS(errors
);
972 if (__get_user(wval
, wva
)) {
973 MIPS_FPU_EMU_INC_STATS(errors
);
977 SITOREG(wval
, MIPSInst_RT(ir
));
981 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
983 MIPS_FPU_EMU_INC_STATS(stores
);
984 SIFROMREG(wval
, MIPSInst_RT(ir
));
985 if (!access_ok(VERIFY_WRITE
, wva
, sizeof(u32
))) {
986 MIPS_FPU_EMU_INC_STATS(errors
);
990 if (__put_user(wval
, wva
)) {
991 MIPS_FPU_EMU_INC_STATS(errors
);
998 switch (MIPSInst_RS(ir
)) {
1000 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1003 /* copregister fs -> gpr[rt] */
1004 if (MIPSInst_RT(ir
) != 0) {
1005 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1011 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1014 /* copregister fs <- rt */
1015 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1019 if (!cpu_has_mips_r2
)
1022 /* copregister rd -> gpr[rt] */
1023 if (MIPSInst_RT(ir
) != 0) {
1024 SIFROMHREG(xcp
->regs
[MIPSInst_RT(ir
)],
1030 if (!cpu_has_mips_r2
)
1033 /* copregister rd <- gpr[rt] */
1034 SITOHREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1038 /* copregister rd -> gpr[rt] */
1039 if (MIPSInst_RT(ir
) != 0) {
1040 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1046 /* copregister rd <- rt */
1047 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1051 /* cop control register rd -> gpr[rt] */
1052 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1054 value
= (value
& ~FPU_CSR_RM
) | modeindex(value
);
1055 pr_debug("%p gpr[%d]<-csr=%08x\n",
1056 (void *) (xcp
->cp0_epc
),
1057 MIPSInst_RT(ir
), value
);
1059 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1063 if (MIPSInst_RT(ir
))
1064 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1068 /* copregister rd <- rt */
1069 if (MIPSInst_RT(ir
) == 0)
1072 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1074 /* we only have one writable control reg
1076 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1077 pr_debug("%p gpr[%d]->csr=%08x\n",
1078 (void *) (xcp
->cp0_epc
),
1079 MIPSInst_RT(ir
), value
);
1082 * Don't write reserved bits,
1083 * and convert to ieee library modes
1085 ctx
->fcr31
= (value
& ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1088 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1094 if (delay_slot(xcp
))
1097 if (cpu_has_mips_4_5_r
)
1098 cbit
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1100 cbit
= FPU_CSR_COND
;
1101 cond
= ctx
->fcr31
& cbit
;
1104 switch (MIPSInst_RT(ir
) & 3) {
1115 /* thats an illegal instruction */
1119 set_delay_slot(xcp
);
1122 * Branch taken: emulate dslot instruction
1124 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1126 contpc
= MIPSInst_SIMM(ir
);
1127 ir
= dec_insn
.next_insn
;
1128 if (dec_insn
.micro_mips_mode
) {
1129 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1131 /* If 16-bit instruction, not FPU. */
1132 if ((dec_insn
.next_pc_inc
== 2) ||
1133 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1136 * Since this instruction will
1137 * be put on the stack with
1138 * 32-bit words, get around
1139 * this problem by putting a
1140 * NOP16 as the second one.
1142 if (dec_insn
.next_pc_inc
== 2)
1143 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1146 * Single step the non-CP1
1147 * instruction in the dslot.
1149 return mips_dsemul(xcp
, ir
, contpc
);
1152 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1154 switch (MIPSInst_OPCODE(ir
)) {
1163 if (cpu_has_mips_2_3_4_5
||
1174 if (cpu_has_mips_4_5
|| cpu_has_mips64
|| cpu_has_mips32r2
)
1175 /* its one of ours */
1181 if (!cpu_has_mips_4_5_r
)
1184 if (MIPSInst_FUNC(ir
) == movc_op
)
1190 * Single step the non-cp1
1191 * instruction in the dslot
1193 return mips_dsemul(xcp
, ir
, contpc
);
1194 } else if (likely
) { /* branch not taken */
1196 * branch likely nullifies
1197 * dslot if not taken
1199 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1200 contpc
+= dec_insn
.pc_inc
;
1202 * else continue & execute
1203 * dslot as normal insn
1209 if (!(MIPSInst_RS(ir
) & 0x10))
1212 /* a real fpu computation instruction */
1213 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1219 if (!cpu_has_mips_4_5
&& !cpu_has_mips64
&& !cpu_has_mips32r2
)
1222 sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1228 if (!cpu_has_mips_4_5_r
)
1231 if (MIPSInst_FUNC(ir
) != movc_op
)
1233 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1234 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1235 xcp
->regs
[MIPSInst_RD(ir
)] =
1236 xcp
->regs
[MIPSInst_RS(ir
)];
1244 xcp
->cp0_epc
= contpc
;
1245 clear_delay_slot(xcp
);
1251 * Conversion table from MIPS compare ops 48-63
1252 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1254 static const unsigned char cmptab
[8] = {
1255 0, /* cmp_0 (sig) cmp_sf */
1256 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1257 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1258 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1259 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1260 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1261 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1262 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1267 * Additional MIPS4 instructions
1270 #define DEF3OP(name, p, f1, f2, f3) \
1271 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1272 union ieee754##p s, union ieee754##p t) \
1274 struct _ieee754_csr ieee754_csr_save; \
1276 ieee754_csr_save = ieee754_csr; \
1278 ieee754_csr_save.cx |= ieee754_csr.cx; \
1279 ieee754_csr_save.sx |= ieee754_csr.sx; \
1281 ieee754_csr.cx |= ieee754_csr_save.cx; \
1282 ieee754_csr.sx |= ieee754_csr_save.sx; \
1286 static union ieee754dp
fpemu_dp_recip(union ieee754dp d
)
1288 return ieee754dp_div(ieee754dp_one(0), d
);
1291 static union ieee754dp
fpemu_dp_rsqrt(union ieee754dp d
)
1293 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1296 static union ieee754sp
fpemu_sp_recip(union ieee754sp s
)
1298 return ieee754sp_div(ieee754sp_one(0), s
);
1301 static union ieee754sp
fpemu_sp_rsqrt(union ieee754sp s
)
1303 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1306 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1307 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1308 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1309 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1310 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1311 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1312 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1313 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1315 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1316 mips_instruction ir
, void *__user
*fault_addr
)
1318 unsigned rcsr
= 0; /* resulting csr */
1320 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1322 switch (MIPSInst_FMA_FFMT(ir
)) {
1323 case s_fmt
:{ /* 0 */
1325 union ieee754sp(*handler
) (union ieee754sp
, union ieee754sp
, union ieee754sp
);
1326 union ieee754sp fd
, fr
, fs
, ft
;
1330 switch (MIPSInst_FUNC(ir
)) {
1332 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1333 xcp
->regs
[MIPSInst_FT(ir
)]);
1335 MIPS_FPU_EMU_INC_STATS(loads
);
1336 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1337 MIPS_FPU_EMU_INC_STATS(errors
);
1341 if (__get_user(val
, va
)) {
1342 MIPS_FPU_EMU_INC_STATS(errors
);
1346 SITOREG(val
, MIPSInst_FD(ir
));
1350 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1351 xcp
->regs
[MIPSInst_FT(ir
)]);
1353 MIPS_FPU_EMU_INC_STATS(stores
);
1355 SIFROMREG(val
, MIPSInst_FS(ir
));
1356 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1357 MIPS_FPU_EMU_INC_STATS(errors
);
1361 if (put_user(val
, va
)) {
1362 MIPS_FPU_EMU_INC_STATS(errors
);
1369 handler
= fpemu_sp_madd
;
1372 handler
= fpemu_sp_msub
;
1375 handler
= fpemu_sp_nmadd
;
1378 handler
= fpemu_sp_nmsub
;
1382 SPFROMREG(fr
, MIPSInst_FR(ir
));
1383 SPFROMREG(fs
, MIPSInst_FS(ir
));
1384 SPFROMREG(ft
, MIPSInst_FT(ir
));
1385 fd
= (*handler
) (fr
, fs
, ft
);
1386 SPTOREG(fd
, MIPSInst_FD(ir
));
1389 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1390 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1391 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1393 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1394 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1395 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1397 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1398 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1399 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1401 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1402 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1403 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1406 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1407 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1408 /*printk ("SIGFPE: FPU csr = %08x\n",
1421 case d_fmt
:{ /* 1 */
1422 union ieee754dp(*handler
) (union ieee754dp
, union ieee754dp
, union ieee754dp
);
1423 union ieee754dp fd
, fr
, fs
, ft
;
1427 switch (MIPSInst_FUNC(ir
)) {
1429 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1430 xcp
->regs
[MIPSInst_FT(ir
)]);
1432 MIPS_FPU_EMU_INC_STATS(loads
);
1433 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1434 MIPS_FPU_EMU_INC_STATS(errors
);
1438 if (__get_user(val
, va
)) {
1439 MIPS_FPU_EMU_INC_STATS(errors
);
1443 DITOREG(val
, MIPSInst_FD(ir
));
1447 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1448 xcp
->regs
[MIPSInst_FT(ir
)]);
1450 MIPS_FPU_EMU_INC_STATS(stores
);
1451 DIFROMREG(val
, MIPSInst_FS(ir
));
1452 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1453 MIPS_FPU_EMU_INC_STATS(errors
);
1457 if (__put_user(val
, va
)) {
1458 MIPS_FPU_EMU_INC_STATS(errors
);
1465 handler
= fpemu_dp_madd
;
1468 handler
= fpemu_dp_msub
;
1471 handler
= fpemu_dp_nmadd
;
1474 handler
= fpemu_dp_nmsub
;
1478 DPFROMREG(fr
, MIPSInst_FR(ir
));
1479 DPFROMREG(fs
, MIPSInst_FS(ir
));
1480 DPFROMREG(ft
, MIPSInst_FT(ir
));
1481 fd
= (*handler
) (fr
, fs
, ft
);
1482 DPTOREG(fd
, MIPSInst_FD(ir
));
1492 if (MIPSInst_FUNC(ir
) != pfetch_op
)
1495 /* ignore prefx operation */
1508 * Emulate a single COP1 arithmetic instruction.
1510 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1511 mips_instruction ir
)
1513 int rfmt
; /* resulting format */
1514 unsigned rcsr
= 0; /* resulting csr */
1523 } rv
; /* resulting value */
1526 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1527 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1528 case s_fmt
: { /* 0 */
1530 union ieee754sp(*b
) (union ieee754sp
, union ieee754sp
);
1531 union ieee754sp(*u
) (union ieee754sp
);
1533 union ieee754sp fs
, ft
;
1535 switch (MIPSInst_FUNC(ir
)) {
1538 handler
.b
= ieee754sp_add
;
1541 handler
.b
= ieee754sp_sub
;
1544 handler
.b
= ieee754sp_mul
;
1547 handler
.b
= ieee754sp_div
;
1552 if (!cpu_has_mips_4_5_r
)
1555 handler
.u
= ieee754sp_sqrt
;
1559 * Note that on some MIPS IV implementations such as the
1560 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1561 * achieve full IEEE-754 accuracy - however this emulator does.
1564 if (!cpu_has_mips_4_5_r2_r6
)
1567 handler
.u
= fpemu_sp_rsqrt
;
1571 if (!cpu_has_mips_4_5_r2_r6
)
1574 handler
.u
= fpemu_sp_recip
;
1578 if (!cpu_has_mips_4_5_r
)
1581 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1582 if (((ctx
->fcr31
& cond
) != 0) !=
1583 ((MIPSInst_FT(ir
) & 1) != 0))
1585 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1589 if (!cpu_has_mips_4_5_r
)
1592 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1594 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1598 if (!cpu_has_mips_4_5_r
)
1601 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1603 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1607 handler
.u
= ieee754sp_abs
;
1611 handler
.u
= ieee754sp_neg
;
1616 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1619 /* binary op on handler */
1621 SPFROMREG(fs
, MIPSInst_FS(ir
));
1622 SPFROMREG(ft
, MIPSInst_FT(ir
));
1624 rv
.s
= (*handler
.b
) (fs
, ft
);
1627 SPFROMREG(fs
, MIPSInst_FS(ir
));
1628 rv
.s
= (*handler
.u
) (fs
);
1631 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1632 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1633 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1635 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1636 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1637 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1639 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1640 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1641 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1643 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
)) {
1644 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv
);
1645 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1647 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1648 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1649 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1653 /* unary conv ops */
1655 return SIGILL
; /* not defined */
1658 SPFROMREG(fs
, MIPSInst_FS(ir
));
1659 rv
.d
= ieee754dp_fsp(fs
);
1664 SPFROMREG(fs
, MIPSInst_FS(ir
));
1665 rv
.w
= ieee754sp_tint(fs
);
1673 if (!cpu_has_mips_2_3_4_5
&& !cpu_has_mips64
)
1676 oldrm
= ieee754_csr
.rm
;
1677 SPFROMREG(fs
, MIPSInst_FS(ir
));
1678 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1679 rv
.w
= ieee754sp_tint(fs
);
1680 ieee754_csr
.rm
= oldrm
;
1685 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1688 SPFROMREG(fs
, MIPSInst_FS(ir
));
1689 rv
.l
= ieee754sp_tlong(fs
);
1697 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1700 oldrm
= ieee754_csr
.rm
;
1701 SPFROMREG(fs
, MIPSInst_FS(ir
));
1702 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1703 rv
.l
= ieee754sp_tlong(fs
);
1704 ieee754_csr
.rm
= oldrm
;
1709 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1710 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1711 union ieee754sp fs
, ft
;
1713 SPFROMREG(fs
, MIPSInst_FS(ir
));
1714 SPFROMREG(ft
, MIPSInst_FT(ir
));
1715 rv
.w
= ieee754sp_cmp(fs
, ft
,
1716 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1718 if ((cmpop
& 0x8) && ieee754_cxtest
1719 (IEEE754_INVALID_OPERATION
))
1720 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1732 union ieee754dp fs
, ft
;
1734 union ieee754dp(*b
) (union ieee754dp
, union ieee754dp
);
1735 union ieee754dp(*u
) (union ieee754dp
);
1738 switch (MIPSInst_FUNC(ir
)) {
1741 handler
.b
= ieee754dp_add
;
1744 handler
.b
= ieee754dp_sub
;
1747 handler
.b
= ieee754dp_mul
;
1750 handler
.b
= ieee754dp_div
;
1755 if (!cpu_has_mips_2_3_4_5_r
)
1758 handler
.u
= ieee754dp_sqrt
;
1761 * Note that on some MIPS IV implementations such as the
1762 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1763 * achieve full IEEE-754 accuracy - however this emulator does.
1766 if (!cpu_has_mips_4_5_r2_r6
)
1769 handler
.u
= fpemu_dp_rsqrt
;
1772 if (!cpu_has_mips_4_5_r2_r6
)
1775 handler
.u
= fpemu_dp_recip
;
1778 if (!cpu_has_mips_4_5_r
)
1781 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1782 if (((ctx
->fcr31
& cond
) != 0) !=
1783 ((MIPSInst_FT(ir
) & 1) != 0))
1785 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1788 if (!cpu_has_mips_4_5_r
)
1791 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1793 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1796 if (!cpu_has_mips_4_5_r
)
1799 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1801 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1804 handler
.u
= ieee754dp_abs
;
1808 handler
.u
= ieee754dp_neg
;
1813 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1816 /* binary op on handler */
1818 DPFROMREG(fs
, MIPSInst_FS(ir
));
1819 DPFROMREG(ft
, MIPSInst_FT(ir
));
1821 rv
.d
= (*handler
.b
) (fs
, ft
);
1824 DPFROMREG(fs
, MIPSInst_FS(ir
));
1825 rv
.d
= (*handler
.u
) (fs
);
1832 DPFROMREG(fs
, MIPSInst_FS(ir
));
1833 rv
.s
= ieee754sp_fdp(fs
);
1838 return SIGILL
; /* not defined */
1841 DPFROMREG(fs
, MIPSInst_FS(ir
));
1842 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1850 if (!cpu_has_mips_2_3_4_5_r
)
1853 oldrm
= ieee754_csr
.rm
;
1854 DPFROMREG(fs
, MIPSInst_FS(ir
));
1855 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1856 rv
.w
= ieee754dp_tint(fs
);
1857 ieee754_csr
.rm
= oldrm
;
1862 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1865 DPFROMREG(fs
, MIPSInst_FS(ir
));
1866 rv
.l
= ieee754dp_tlong(fs
);
1874 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1877 oldrm
= ieee754_csr
.rm
;
1878 DPFROMREG(fs
, MIPSInst_FS(ir
));
1879 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1880 rv
.l
= ieee754dp_tlong(fs
);
1881 ieee754_csr
.rm
= oldrm
;
1886 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1887 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1888 union ieee754dp fs
, ft
;
1890 DPFROMREG(fs
, MIPSInst_FS(ir
));
1891 DPFROMREG(ft
, MIPSInst_FT(ir
));
1892 rv
.w
= ieee754dp_cmp(fs
, ft
,
1893 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1898 (IEEE754_INVALID_OPERATION
))
1899 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1912 switch (MIPSInst_FUNC(ir
)) {
1914 /* convert word to single precision real */
1915 SPFROMREG(fs
, MIPSInst_FS(ir
));
1916 rv
.s
= ieee754sp_fint(fs
.bits
);
1920 /* convert word to double precision real */
1921 SPFROMREG(fs
, MIPSInst_FS(ir
));
1922 rv
.d
= ieee754dp_fint(fs
.bits
);
1933 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1936 DIFROMREG(bits
, MIPSInst_FS(ir
));
1938 switch (MIPSInst_FUNC(ir
)) {
1940 /* convert long to single precision real */
1941 rv
.s
= ieee754sp_flong(bits
);
1945 /* convert long to double precision real */
1946 rv
.d
= ieee754dp_flong(bits
);
1959 * Update the fpu CSR register for this operation.
1960 * If an exception is required, generate a tidy SIGFPE exception,
1961 * without updating the result register.
1962 * Note: cause exception bits do not accumulate, they are rewritten
1963 * for each op; only the flag/sticky bits accumulate.
1965 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1966 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1967 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1972 * Now we can safely write the result back to the register file.
1977 if (cpu_has_mips_4_5_r
)
1978 cbit
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
1980 cbit
= FPU_CSR_COND
;
1984 ctx
->fcr31
&= ~cbit
;
1988 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
1991 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
1994 SITOREG(rv
.w
, MIPSInst_FD(ir
));
1997 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
2000 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2009 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2010 int has_fpu
, void *__user
*fault_addr
)
2012 unsigned long oldepc
, prevepc
;
2013 struct mm_decoded_insn dec_insn
;
2018 oldepc
= xcp
->cp0_epc
;
2020 prevepc
= xcp
->cp0_epc
;
2022 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2024 * Get next 2 microMIPS instructions and convert them
2025 * into 32-bit instructions.
2027 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2028 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2029 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2030 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2031 MIPS_FPU_EMU_INC_STATS(errors
);
2036 /* Get first instruction. */
2037 if (mm_insn_16bit(*instr_ptr
)) {
2038 /* Duplicate the half-word. */
2039 dec_insn
.insn
= (*instr_ptr
<< 16) |
2041 /* 16-bit instruction. */
2042 dec_insn
.pc_inc
= 2;
2045 dec_insn
.insn
= (*instr_ptr
<< 16) |
2047 /* 32-bit instruction. */
2048 dec_insn
.pc_inc
= 4;
2051 /* Get second instruction. */
2052 if (mm_insn_16bit(*instr_ptr
)) {
2053 /* Duplicate the half-word. */
2054 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2056 /* 16-bit instruction. */
2057 dec_insn
.next_pc_inc
= 2;
2059 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2061 /* 32-bit instruction. */
2062 dec_insn
.next_pc_inc
= 4;
2064 dec_insn
.micro_mips_mode
= 1;
2066 if ((get_user(dec_insn
.insn
,
2067 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2068 (get_user(dec_insn
.next_insn
,
2069 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2070 MIPS_FPU_EMU_INC_STATS(errors
);
2073 dec_insn
.pc_inc
= 4;
2074 dec_insn
.next_pc_inc
= 4;
2075 dec_insn
.micro_mips_mode
= 0;
2078 if ((dec_insn
.insn
== 0) ||
2079 ((dec_insn
.pc_inc
== 2) &&
2080 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2081 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2084 * The 'ieee754_csr' is an alias of
2085 * ctx->fcr31. No need to copy ctx->fcr31 to
2086 * ieee754_csr. But ieee754_csr.rm is ieee
2087 * library modes. (not mips rounding mode)
2089 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2098 } while (xcp
->cp0_epc
> prevepc
);
2100 /* SIGILL indicates a non-fpu instruction */
2101 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2102 /* but if EPC has advanced, then ignore it */