2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
59 static int fpux_emu(struct pt_regs
*,
60 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* microMIPS bitfields */
71 #define MM_POOL32A_MINOR_MASK 0x3f
72 #define MM_POOL32A_MINOR_SHIFT 0x6
73 #define MM_MIPS32_COND_FC 0x30
75 /* Convert MIPS rounding mode (0..3) to IEEE library modes. */
76 static const unsigned char ieee_rm
[4] = {
77 [FPU_CSR_RN
] = IEEE754_RN
,
78 [FPU_CSR_RZ
] = IEEE754_RZ
,
79 [FPU_CSR_RU
] = IEEE754_RU
,
80 [FPU_CSR_RD
] = IEEE754_RD
,
82 /* Convert IEEE library modes to MIPS rounding mode (0..3). */
83 static const unsigned char mips_rm
[4] = {
84 [IEEE754_RN
] = FPU_CSR_RN
,
85 [IEEE754_RZ
] = FPU_CSR_RZ
,
86 [IEEE754_RD
] = FPU_CSR_RD
,
87 [IEEE754_RU
] = FPU_CSR_RU
,
90 /* convert condition code register number to csr bit */
91 static const unsigned int fpucondbit
[8] = {
102 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
103 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
105 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
106 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
107 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
108 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
109 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
112 * This functions translates a 32-bit microMIPS instruction
113 * into a 32-bit MIPS32 instruction. Returns 0 on success
114 * and SIGILL otherwise.
116 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
118 union mips_instruction insn
= *insn_ptr
;
119 union mips_instruction mips32_insn
= insn
;
122 switch (insn
.mm_i_format
.opcode
) {
124 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
125 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
126 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
129 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
130 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
131 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
134 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
135 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
136 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
139 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
140 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
141 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
144 /* NOTE: offset is << by 1 if in microMIPS mode. */
145 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
146 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
147 mips32_insn
.fb_format
.opcode
= cop1_op
;
148 mips32_insn
.fb_format
.bc
= bc_op
;
149 mips32_insn
.fb_format
.flag
=
150 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
155 switch (insn
.mm_fp0_format
.func
) {
164 op
= insn
.mm_fp0_format
.func
;
165 if (op
== mm_32f_01_op
)
167 else if (op
== mm_32f_11_op
)
169 else if (op
== mm_32f_02_op
)
171 else if (op
== mm_32f_12_op
)
173 else if (op
== mm_32f_41_op
)
175 else if (op
== mm_32f_51_op
)
177 else if (op
== mm_32f_42_op
)
181 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
182 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
183 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
184 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
185 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
186 mips32_insn
.fp6_format
.func
= func
;
189 func
= -1; /* Invalid */
190 op
= insn
.mm_fp5_format
.op
& 0x7;
191 if (op
== mm_ldxc1_op
)
193 else if (op
== mm_sdxc1_op
)
195 else if (op
== mm_lwxc1_op
)
197 else if (op
== mm_swxc1_op
)
201 mips32_insn
.r_format
.opcode
= cop1x_op
;
202 mips32_insn
.r_format
.rs
=
203 insn
.mm_fp5_format
.base
;
204 mips32_insn
.r_format
.rt
=
205 insn
.mm_fp5_format
.index
;
206 mips32_insn
.r_format
.rd
= 0;
207 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
208 mips32_insn
.r_format
.func
= func
;
213 op
= -1; /* Invalid */
214 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
216 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
219 mips32_insn
.fp0_format
.opcode
= cop1_op
;
220 mips32_insn
.fp0_format
.fmt
=
221 sdps_format
[insn
.mm_fp2_format
.fmt
];
222 mips32_insn
.fp0_format
.ft
=
223 (insn
.mm_fp2_format
.cc
<<2) + op
;
224 mips32_insn
.fp0_format
.fs
=
225 insn
.mm_fp2_format
.fs
;
226 mips32_insn
.fp0_format
.fd
=
227 insn
.mm_fp2_format
.fd
;
228 mips32_insn
.fp0_format
.func
= fmovc_op
;
233 func
= -1; /* Invalid */
234 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
236 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
238 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
240 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
243 mips32_insn
.fp0_format
.opcode
= cop1_op
;
244 mips32_insn
.fp0_format
.fmt
=
245 sdps_format
[insn
.mm_fp0_format
.fmt
];
246 mips32_insn
.fp0_format
.ft
=
247 insn
.mm_fp0_format
.ft
;
248 mips32_insn
.fp0_format
.fs
=
249 insn
.mm_fp0_format
.fs
;
250 mips32_insn
.fp0_format
.fd
=
251 insn
.mm_fp0_format
.fd
;
252 mips32_insn
.fp0_format
.func
= func
;
257 func
= -1; /* Invalid */
258 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
260 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
263 mips32_insn
.fp0_format
.opcode
= cop1_op
;
264 mips32_insn
.fp0_format
.fmt
=
265 sdps_format
[insn
.mm_fp0_format
.fmt
];
266 mips32_insn
.fp0_format
.ft
=
267 insn
.mm_fp0_format
.ft
;
268 mips32_insn
.fp0_format
.fs
=
269 insn
.mm_fp0_format
.fs
;
270 mips32_insn
.fp0_format
.fd
=
271 insn
.mm_fp0_format
.fd
;
272 mips32_insn
.fp0_format
.func
= func
;
276 case mm_32f_73_op
: /* POOL32FXF */
277 switch (insn
.mm_fp1_format
.op
) {
282 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
287 mips32_insn
.r_format
.opcode
= spec_op
;
288 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
289 mips32_insn
.r_format
.rt
=
290 (insn
.mm_fp4_format
.cc
<< 2) + op
;
291 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
292 mips32_insn
.r_format
.re
= 0;
293 mips32_insn
.r_format
.func
= movc_op
;
299 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
302 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
305 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
307 mips32_insn
.fp0_format
.opcode
= cop1_op
;
308 mips32_insn
.fp0_format
.fmt
= fmt
;
309 mips32_insn
.fp0_format
.ft
= 0;
310 mips32_insn
.fp0_format
.fs
=
311 insn
.mm_fp3_format
.fs
;
312 mips32_insn
.fp0_format
.fd
=
313 insn
.mm_fp3_format
.rt
;
314 mips32_insn
.fp0_format
.func
= func
;
322 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
325 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
330 mips32_insn
.fp0_format
.opcode
= cop1_op
;
331 mips32_insn
.fp0_format
.fmt
=
332 sdps_format
[insn
.mm_fp3_format
.fmt
];
333 mips32_insn
.fp0_format
.ft
= 0;
334 mips32_insn
.fp0_format
.fs
=
335 insn
.mm_fp3_format
.fs
;
336 mips32_insn
.fp0_format
.fd
=
337 insn
.mm_fp3_format
.rt
;
338 mips32_insn
.fp0_format
.func
= func
;
350 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
352 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
354 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
356 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
358 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
360 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
362 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
364 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
366 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
370 mips32_insn
.fp0_format
.opcode
= cop1_op
;
371 mips32_insn
.fp0_format
.fmt
=
372 sd_format
[insn
.mm_fp1_format
.fmt
];
373 mips32_insn
.fp0_format
.ft
= 0;
374 mips32_insn
.fp0_format
.fs
=
375 insn
.mm_fp1_format
.fs
;
376 mips32_insn
.fp0_format
.fd
=
377 insn
.mm_fp1_format
.rt
;
378 mips32_insn
.fp0_format
.func
= func
;
383 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
385 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
389 mips32_insn
.fp0_format
.opcode
= cop1_op
;
390 mips32_insn
.fp0_format
.fmt
=
391 sdps_format
[insn
.mm_fp1_format
.fmt
];
392 mips32_insn
.fp0_format
.ft
= 0;
393 mips32_insn
.fp0_format
.fs
=
394 insn
.mm_fp1_format
.fs
;
395 mips32_insn
.fp0_format
.fd
=
396 insn
.mm_fp1_format
.rt
;
397 mips32_insn
.fp0_format
.func
= func
;
405 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
407 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
409 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
411 else if (insn
.mm_fp1_format
.op
== mm_ctc1_op
)
413 else if (insn
.mm_fp1_format
.op
== mm_mfhc1_op
)
417 mips32_insn
.fp1_format
.opcode
= cop1_op
;
418 mips32_insn
.fp1_format
.op
= op
;
419 mips32_insn
.fp1_format
.rt
=
420 insn
.mm_fp1_format
.rt
;
421 mips32_insn
.fp1_format
.fs
=
422 insn
.mm_fp1_format
.fs
;
423 mips32_insn
.fp1_format
.fd
= 0;
424 mips32_insn
.fp1_format
.func
= 0;
430 case mm_32f_74_op
: /* c.cond.fmt */
431 mips32_insn
.fp0_format
.opcode
= cop1_op
;
432 mips32_insn
.fp0_format
.fmt
=
433 sdps_format
[insn
.mm_fp4_format
.fmt
];
434 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
435 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
436 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
437 mips32_insn
.fp0_format
.func
=
438 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
448 *insn_ptr
= mips32_insn
;
452 int mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
453 unsigned long *contpc
)
455 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
463 switch (insn
.mm_i_format
.opcode
) {
465 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
467 switch (insn
.mm_i_format
.simmediate
>>
468 MM_POOL32A_MINOR_SHIFT
) {
473 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
474 regs
->regs
[insn
.mm_i_format
.rt
] =
477 dec_insn
.next_pc_inc
;
478 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
484 switch (insn
.mm_i_format
.rt
) {
487 regs
->regs
[31] = regs
->cp0_epc
+
489 dec_insn
.next_pc_inc
;
492 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
493 *contpc
= regs
->cp0_epc
+
495 (insn
.mm_i_format
.simmediate
<< 1);
497 *contpc
= regs
->cp0_epc
+
499 dec_insn
.next_pc_inc
;
503 regs
->regs
[31] = regs
->cp0_epc
+
505 dec_insn
.next_pc_inc
;
508 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
509 *contpc
= regs
->cp0_epc
+
511 (insn
.mm_i_format
.simmediate
<< 1);
513 *contpc
= regs
->cp0_epc
+
515 dec_insn
.next_pc_inc
;
518 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
519 *contpc
= regs
->cp0_epc
+
521 (insn
.mm_i_format
.simmediate
<< 1);
523 *contpc
= regs
->cp0_epc
+
525 dec_insn
.next_pc_inc
;
528 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
529 *contpc
= regs
->cp0_epc
+
531 (insn
.mm_i_format
.simmediate
<< 1);
533 *contpc
= regs
->cp0_epc
+
535 dec_insn
.next_pc_inc
;
545 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
547 fcr31
= current
->thread
.fpu
.fcr31
;
553 bit
= (insn
.mm_i_format
.rs
>> 2);
556 if (fcr31
& (1 << bit
))
557 *contpc
= regs
->cp0_epc
+
559 (insn
.mm_i_format
.simmediate
<< 1);
561 *contpc
= regs
->cp0_epc
+
562 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
567 switch (insn
.mm_i_format
.rt
) {
570 regs
->regs
[31] = regs
->cp0_epc
+
571 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
574 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
579 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
580 *contpc
= regs
->cp0_epc
+
582 (insn
.mm_b1_format
.simmediate
<< 1);
584 *contpc
= regs
->cp0_epc
+
585 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
588 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
589 *contpc
= regs
->cp0_epc
+
591 (insn
.mm_b1_format
.simmediate
<< 1);
593 *contpc
= regs
->cp0_epc
+
594 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
597 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
598 (insn
.mm_b0_format
.simmediate
<< 1);
601 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
602 regs
->regs
[insn
.mm_i_format
.rt
])
603 *contpc
= regs
->cp0_epc
+
605 (insn
.mm_i_format
.simmediate
<< 1);
607 *contpc
= regs
->cp0_epc
+
609 dec_insn
.next_pc_inc
;
612 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
613 regs
->regs
[insn
.mm_i_format
.rt
])
614 *contpc
= regs
->cp0_epc
+
616 (insn
.mm_i_format
.simmediate
<< 1);
618 *contpc
= regs
->cp0_epc
+
619 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
622 regs
->regs
[31] = regs
->cp0_epc
+
623 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
624 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
627 *contpc
|= (insn
.j_format
.target
<< 2);
631 regs
->regs
[31] = regs
->cp0_epc
+
632 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
635 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
638 *contpc
|= (insn
.j_format
.target
<< 1);
639 set_isa16_mode(*contpc
);
646 * Redundant with logic already in kernel/branch.c,
647 * embedded in compute_return_epc. At some point,
648 * a single subroutine should be used across both
651 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
652 unsigned long *contpc
)
654 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
656 unsigned int bit
= 0;
658 switch (insn
.i_format
.opcode
) {
660 switch (insn
.r_format
.func
) {
662 regs
->regs
[insn
.r_format
.rd
] =
663 regs
->cp0_epc
+ dec_insn
.pc_inc
+
664 dec_insn
.next_pc_inc
;
667 *contpc
= regs
->regs
[insn
.r_format
.rs
];
672 switch (insn
.i_format
.rt
) {
675 regs
->regs
[31] = regs
->cp0_epc
+
677 dec_insn
.next_pc_inc
;
681 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
682 *contpc
= regs
->cp0_epc
+
684 (insn
.i_format
.simmediate
<< 2);
686 *contpc
= regs
->cp0_epc
+
688 dec_insn
.next_pc_inc
;
692 regs
->regs
[31] = regs
->cp0_epc
+
694 dec_insn
.next_pc_inc
;
698 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
699 *contpc
= regs
->cp0_epc
+
701 (insn
.i_format
.simmediate
<< 2);
703 *contpc
= regs
->cp0_epc
+
705 dec_insn
.next_pc_inc
;
712 regs
->regs
[31] = regs
->cp0_epc
+
714 dec_insn
.next_pc_inc
;
717 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
720 *contpc
|= (insn
.j_format
.target
<< 2);
721 /* Set microMIPS mode bit: XOR for jalx. */
726 if (regs
->regs
[insn
.i_format
.rs
] ==
727 regs
->regs
[insn
.i_format
.rt
])
728 *contpc
= regs
->cp0_epc
+
730 (insn
.i_format
.simmediate
<< 2);
732 *contpc
= regs
->cp0_epc
+
734 dec_insn
.next_pc_inc
;
738 if (regs
->regs
[insn
.i_format
.rs
] !=
739 regs
->regs
[insn
.i_format
.rt
])
740 *contpc
= regs
->cp0_epc
+
742 (insn
.i_format
.simmediate
<< 2);
744 *contpc
= regs
->cp0_epc
+
746 dec_insn
.next_pc_inc
;
750 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
751 *contpc
= regs
->cp0_epc
+
753 (insn
.i_format
.simmediate
<< 2);
755 *contpc
= regs
->cp0_epc
+
757 dec_insn
.next_pc_inc
;
761 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
762 *contpc
= regs
->cp0_epc
+
764 (insn
.i_format
.simmediate
<< 2);
766 *contpc
= regs
->cp0_epc
+
768 dec_insn
.next_pc_inc
;
770 #ifdef CONFIG_CPU_CAVIUM_OCTEON
771 case lwc2_op
: /* This is bbit0 on Octeon */
772 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
773 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
775 *contpc
= regs
->cp0_epc
+ 8;
777 case ldc2_op
: /* This is bbit032 on Octeon */
778 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
779 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
781 *contpc
= regs
->cp0_epc
+ 8;
783 case swc2_op
: /* This is bbit1 on Octeon */
784 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
785 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
787 *contpc
= regs
->cp0_epc
+ 8;
789 case sdc2_op
: /* This is bbit132 on Octeon */
790 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
791 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
793 *contpc
= regs
->cp0_epc
+ 8;
800 if (insn
.i_format
.rs
== bc_op
) {
803 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
805 fcr31
= current
->thread
.fpu
.fcr31
;
808 bit
= (insn
.i_format
.rt
>> 2);
811 switch (insn
.i_format
.rt
& 3) {
814 if (~fcr31
& (1 << bit
))
815 *contpc
= regs
->cp0_epc
+
817 (insn
.i_format
.simmediate
<< 2);
819 *contpc
= regs
->cp0_epc
+
821 dec_insn
.next_pc_inc
;
825 if (fcr31
& (1 << bit
))
826 *contpc
= regs
->cp0_epc
+
828 (insn
.i_format
.simmediate
<< 2);
830 *contpc
= regs
->cp0_epc
+
832 dec_insn
.next_pc_inc
;
842 * In the Linux kernel, we support selection of FPR format on the
843 * basis of the Status.FR bit. If an FPU is not present, the FR bit
844 * is hardwired to zero, which would imply a 32-bit FPU even for
845 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
846 * FPU emu is slow and bulky and optimizing this function offers fairly
847 * sizeable benefits so we try to be clever and make this function return
848 * a constant whenever possible, that is on 64-bit kernels without O32
849 * compatibility enabled and on 32-bit without 64-bit FPU support.
851 static inline int cop1_64bit(struct pt_regs
*xcp
)
853 if (config_enabled(CONFIG_64BIT
) && !config_enabled(CONFIG_MIPS32_O32
))
855 else if (config_enabled(CONFIG_32BIT
) &&
856 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT
))
859 return !test_thread_flag(TIF_32BIT_FPREGS
);
862 #define SIFROMREG(si, x) \
864 if (cop1_64bit(xcp)) \
865 (si) = get_fpr32(&ctx->fpr[x], 0); \
867 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
870 #define SITOREG(si, x) \
872 if (cop1_64bit(xcp)) { \
874 set_fpr32(&ctx->fpr[x], 0, si); \
875 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
876 set_fpr32(&ctx->fpr[x], i, 0); \
878 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
882 #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
884 #define SITOHREG(si, x) \
887 set_fpr32(&ctx->fpr[x], 1, si); \
888 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
889 set_fpr32(&ctx->fpr[x], i, 0); \
892 #define DIFROMREG(di, x) \
893 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
895 #define DITOREG(di, x) \
898 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
899 set_fpr64(&ctx->fpr[fpr], 0, di); \
900 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
901 set_fpr64(&ctx->fpr[fpr], i, 0); \
904 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
905 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
906 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
907 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
910 * Emulate the single floating point instruction pointed at by EPC.
911 * Two instructions if the instruction is in a branch delay slot.
914 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
915 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
917 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
918 unsigned int cond
, cbit
;
928 /* XXX NEC Vr54xx bug workaround */
929 if (delay_slot(xcp
)) {
930 if (dec_insn
.micro_mips_mode
) {
931 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
932 clear_delay_slot(xcp
);
934 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
935 clear_delay_slot(xcp
);
939 if (delay_slot(xcp
)) {
941 * The instruction to be emulated is in a branch delay slot
942 * which means that we have to emulate the branch instruction
943 * BEFORE we do the cop1 instruction.
945 * This branch could be a COP1 branch, but in that case we
946 * would have had a trap for that instruction, and would not
947 * come through this route.
949 * Linux MIPS branch emulator operates on context, updating the
952 ir
= dec_insn
.next_insn
; /* process delay slot instr */
953 pc_inc
= dec_insn
.next_pc_inc
;
955 ir
= dec_insn
.insn
; /* process current instr */
956 pc_inc
= dec_insn
.pc_inc
;
960 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
961 * instructions, we want to convert microMIPS FPU instructions
962 * into MIPS32 instructions so that we could reuse all of the
963 * FPU emulation code.
965 * NOTE: We cannot do this for branch instructions since they
966 * are not a subset. Example: Cannot emulate a 16-bit
967 * aligned target address with a MIPS32 instruction.
969 if (dec_insn
.micro_mips_mode
) {
971 * If next instruction is a 16-bit instruction, then it
972 * it cannot be a FPU instruction. This could happen
973 * since we can be called for non-FPU instructions.
976 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
982 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
983 MIPS_FPU_EMU_INC_STATS(emulated
);
984 switch (MIPSInst_OPCODE(ir
)) {
986 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
988 MIPS_FPU_EMU_INC_STATS(loads
);
990 if (!access_ok(VERIFY_READ
, dva
, sizeof(u64
))) {
991 MIPS_FPU_EMU_INC_STATS(errors
);
995 if (__get_user(dval
, dva
)) {
996 MIPS_FPU_EMU_INC_STATS(errors
);
1000 DITOREG(dval
, MIPSInst_RT(ir
));
1004 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1006 MIPS_FPU_EMU_INC_STATS(stores
);
1007 DIFROMREG(dval
, MIPSInst_RT(ir
));
1008 if (!access_ok(VERIFY_WRITE
, dva
, sizeof(u64
))) {
1009 MIPS_FPU_EMU_INC_STATS(errors
);
1013 if (__put_user(dval
, dva
)) {
1014 MIPS_FPU_EMU_INC_STATS(errors
);
1021 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1023 MIPS_FPU_EMU_INC_STATS(loads
);
1024 if (!access_ok(VERIFY_READ
, wva
, sizeof(u32
))) {
1025 MIPS_FPU_EMU_INC_STATS(errors
);
1029 if (__get_user(wval
, wva
)) {
1030 MIPS_FPU_EMU_INC_STATS(errors
);
1034 SITOREG(wval
, MIPSInst_RT(ir
));
1038 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1040 MIPS_FPU_EMU_INC_STATS(stores
);
1041 SIFROMREG(wval
, MIPSInst_RT(ir
));
1042 if (!access_ok(VERIFY_WRITE
, wva
, sizeof(u32
))) {
1043 MIPS_FPU_EMU_INC_STATS(errors
);
1047 if (__put_user(wval
, wva
)) {
1048 MIPS_FPU_EMU_INC_STATS(errors
);
1055 switch (MIPSInst_RS(ir
)) {
1057 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1060 /* copregister fs -> gpr[rt] */
1061 if (MIPSInst_RT(ir
) != 0) {
1062 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1068 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1071 /* copregister fs <- rt */
1072 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1076 if (!cpu_has_mips_r2
)
1079 /* copregister rd -> gpr[rt] */
1080 if (MIPSInst_RT(ir
) != 0) {
1081 SIFROMHREG(xcp
->regs
[MIPSInst_RT(ir
)],
1087 if (!cpu_has_mips_r2
)
1090 /* copregister rd <- gpr[rt] */
1091 SITOHREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1095 /* copregister rd -> gpr[rt] */
1096 if (MIPSInst_RT(ir
) != 0) {
1097 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1103 /* copregister rd <- rt */
1104 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1108 /* cop control register rd -> gpr[rt] */
1109 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1111 value
= (value
& ~FPU_CSR_RM
) |
1112 mips_rm
[modeindex(value
)];
1113 pr_debug("%p gpr[%d]<-csr=%08x\n",
1114 (void *) (xcp
->cp0_epc
),
1115 MIPSInst_RT(ir
), value
);
1117 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1121 if (MIPSInst_RT(ir
))
1122 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1126 /* copregister rd <- rt */
1127 if (MIPSInst_RT(ir
) == 0)
1130 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1132 /* we only have one writable control reg
1134 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1135 pr_debug("%p gpr[%d]->csr=%08x\n",
1136 (void *) (xcp
->cp0_epc
),
1137 MIPSInst_RT(ir
), value
);
1140 * Don't write reserved bits,
1141 * and convert to ieee library modes
1143 ctx
->fcr31
= (value
&
1144 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1145 ieee_rm
[modeindex(value
)];
1147 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1153 if (delay_slot(xcp
))
1156 if (cpu_has_mips_4_5_r
)
1157 cbit
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1159 cbit
= FPU_CSR_COND
;
1160 cond
= ctx
->fcr31
& cbit
;
1163 switch (MIPSInst_RT(ir
) & 3) {
1174 /* thats an illegal instruction */
1178 set_delay_slot(xcp
);
1181 * Branch taken: emulate dslot instruction
1183 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1185 contpc
= MIPSInst_SIMM(ir
);
1186 ir
= dec_insn
.next_insn
;
1187 if (dec_insn
.micro_mips_mode
) {
1188 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1190 /* If 16-bit instruction, not FPU. */
1191 if ((dec_insn
.next_pc_inc
== 2) ||
1192 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1195 * Since this instruction will
1196 * be put on the stack with
1197 * 32-bit words, get around
1198 * this problem by putting a
1199 * NOP16 as the second one.
1201 if (dec_insn
.next_pc_inc
== 2)
1202 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1205 * Single step the non-CP1
1206 * instruction in the dslot.
1208 return mips_dsemul(xcp
, ir
, contpc
);
1211 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1213 switch (MIPSInst_OPCODE(ir
)) {
1222 if (cpu_has_mips_2_3_4_5
||
1233 if (cpu_has_mips_4_5
|| cpu_has_mips64
)
1234 /* its one of ours */
1240 if (!cpu_has_mips_4_5_r
)
1243 if (MIPSInst_FUNC(ir
) == movc_op
)
1249 * Single step the non-cp1
1250 * instruction in the dslot
1252 return mips_dsemul(xcp
, ir
, contpc
);
1253 } else if (likely
) { /* branch not taken */
1255 * branch likely nullifies
1256 * dslot if not taken
1258 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1259 contpc
+= dec_insn
.pc_inc
;
1261 * else continue & execute
1262 * dslot as normal insn
1268 if (!(MIPSInst_RS(ir
) & 0x10))
1271 /* a real fpu computation instruction */
1272 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1278 if (!cpu_has_mips_4_5
&& !cpu_has_mips64
)
1281 sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1287 if (!cpu_has_mips_4_5_r
)
1290 if (MIPSInst_FUNC(ir
) != movc_op
)
1292 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1293 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1294 xcp
->regs
[MIPSInst_RD(ir
)] =
1295 xcp
->regs
[MIPSInst_RS(ir
)];
1303 xcp
->cp0_epc
= contpc
;
1304 clear_delay_slot(xcp
);
1310 * Conversion table from MIPS compare ops 48-63
1311 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1313 static const unsigned char cmptab
[8] = {
1314 0, /* cmp_0 (sig) cmp_sf */
1315 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1316 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1317 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1318 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1319 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1320 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1321 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1326 * Additional MIPS4 instructions
1329 #define DEF3OP(name, p, f1, f2, f3) \
1330 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1331 union ieee754##p s, union ieee754##p t) \
1333 struct _ieee754_csr ieee754_csr_save; \
1335 ieee754_csr_save = ieee754_csr; \
1337 ieee754_csr_save.cx |= ieee754_csr.cx; \
1338 ieee754_csr_save.sx |= ieee754_csr.sx; \
1340 ieee754_csr.cx |= ieee754_csr_save.cx; \
1341 ieee754_csr.sx |= ieee754_csr_save.sx; \
1345 static union ieee754dp
fpemu_dp_recip(union ieee754dp d
)
1347 return ieee754dp_div(ieee754dp_one(0), d
);
1350 static union ieee754dp
fpemu_dp_rsqrt(union ieee754dp d
)
1352 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1355 static union ieee754sp
fpemu_sp_recip(union ieee754sp s
)
1357 return ieee754sp_div(ieee754sp_one(0), s
);
1360 static union ieee754sp
fpemu_sp_rsqrt(union ieee754sp s
)
1362 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1365 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1366 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1367 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1368 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1369 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1370 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1371 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1372 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1374 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1375 mips_instruction ir
, void *__user
*fault_addr
)
1377 unsigned rcsr
= 0; /* resulting csr */
1379 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1381 switch (MIPSInst_FMA_FFMT(ir
)) {
1382 case s_fmt
:{ /* 0 */
1384 union ieee754sp(*handler
) (union ieee754sp
, union ieee754sp
, union ieee754sp
);
1385 union ieee754sp fd
, fr
, fs
, ft
;
1389 switch (MIPSInst_FUNC(ir
)) {
1391 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1392 xcp
->regs
[MIPSInst_FT(ir
)]);
1394 MIPS_FPU_EMU_INC_STATS(loads
);
1395 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1396 MIPS_FPU_EMU_INC_STATS(errors
);
1400 if (__get_user(val
, va
)) {
1401 MIPS_FPU_EMU_INC_STATS(errors
);
1405 SITOREG(val
, MIPSInst_FD(ir
));
1409 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1410 xcp
->regs
[MIPSInst_FT(ir
)]);
1412 MIPS_FPU_EMU_INC_STATS(stores
);
1414 SIFROMREG(val
, MIPSInst_FS(ir
));
1415 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1416 MIPS_FPU_EMU_INC_STATS(errors
);
1420 if (put_user(val
, va
)) {
1421 MIPS_FPU_EMU_INC_STATS(errors
);
1428 handler
= fpemu_sp_madd
;
1431 handler
= fpemu_sp_msub
;
1434 handler
= fpemu_sp_nmadd
;
1437 handler
= fpemu_sp_nmsub
;
1441 SPFROMREG(fr
, MIPSInst_FR(ir
));
1442 SPFROMREG(fs
, MIPSInst_FS(ir
));
1443 SPFROMREG(ft
, MIPSInst_FT(ir
));
1444 fd
= (*handler
) (fr
, fs
, ft
);
1445 SPTOREG(fd
, MIPSInst_FD(ir
));
1448 if (ieee754_cxtest(IEEE754_INEXACT
))
1449 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1450 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1451 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1452 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1453 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1454 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1455 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1457 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1458 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1459 /*printk ("SIGFPE: FPU csr = %08x\n",
1472 case d_fmt
:{ /* 1 */
1473 union ieee754dp(*handler
) (union ieee754dp
, union ieee754dp
, union ieee754dp
);
1474 union ieee754dp fd
, fr
, fs
, ft
;
1478 switch (MIPSInst_FUNC(ir
)) {
1480 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1481 xcp
->regs
[MIPSInst_FT(ir
)]);
1483 MIPS_FPU_EMU_INC_STATS(loads
);
1484 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1485 MIPS_FPU_EMU_INC_STATS(errors
);
1489 if (__get_user(val
, va
)) {
1490 MIPS_FPU_EMU_INC_STATS(errors
);
1494 DITOREG(val
, MIPSInst_FD(ir
));
1498 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1499 xcp
->regs
[MIPSInst_FT(ir
)]);
1501 MIPS_FPU_EMU_INC_STATS(stores
);
1502 DIFROMREG(val
, MIPSInst_FS(ir
));
1503 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1504 MIPS_FPU_EMU_INC_STATS(errors
);
1508 if (__put_user(val
, va
)) {
1509 MIPS_FPU_EMU_INC_STATS(errors
);
1516 handler
= fpemu_dp_madd
;
1519 handler
= fpemu_dp_msub
;
1522 handler
= fpemu_dp_nmadd
;
1525 handler
= fpemu_dp_nmsub
;
1529 DPFROMREG(fr
, MIPSInst_FR(ir
));
1530 DPFROMREG(fs
, MIPSInst_FS(ir
));
1531 DPFROMREG(ft
, MIPSInst_FT(ir
));
1532 fd
= (*handler
) (fr
, fs
, ft
);
1533 DPTOREG(fd
, MIPSInst_FD(ir
));
1543 if (MIPSInst_FUNC(ir
) != pfetch_op
)
1546 /* ignore prefx operation */
1559 * Emulate a single COP1 arithmetic instruction.
1561 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1562 mips_instruction ir
)
1564 int rfmt
; /* resulting format */
1565 unsigned rcsr
= 0; /* resulting csr */
1574 } rv
; /* resulting value */
1577 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1578 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1579 case s_fmt
: { /* 0 */
1581 union ieee754sp(*b
) (union ieee754sp
, union ieee754sp
);
1582 union ieee754sp(*u
) (union ieee754sp
);
1584 union ieee754sp fs
, ft
;
1586 switch (MIPSInst_FUNC(ir
)) {
1589 handler
.b
= ieee754sp_add
;
1592 handler
.b
= ieee754sp_sub
;
1595 handler
.b
= ieee754sp_mul
;
1598 handler
.b
= ieee754sp_div
;
1603 if (!cpu_has_mips_4_5_r
)
1606 handler
.u
= ieee754sp_sqrt
;
1610 * Note that on some MIPS IV implementations such as the
1611 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1612 * achieve full IEEE-754 accuracy - however this emulator does.
1615 if (!cpu_has_mips_4_5_r2
)
1618 handler
.u
= fpemu_sp_rsqrt
;
1622 if (!cpu_has_mips_4_5_r2
)
1625 handler
.u
= fpemu_sp_recip
;
1629 if (!cpu_has_mips_4_5_r
)
1632 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1633 if (((ctx
->fcr31
& cond
) != 0) !=
1634 ((MIPSInst_FT(ir
) & 1) != 0))
1636 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1640 if (!cpu_has_mips_4_5_r
)
1643 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1645 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1649 if (!cpu_has_mips_4_5_r
)
1652 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1654 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1658 handler
.u
= ieee754sp_abs
;
1662 handler
.u
= ieee754sp_neg
;
1667 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1670 /* binary op on handler */
1672 SPFROMREG(fs
, MIPSInst_FS(ir
));
1673 SPFROMREG(ft
, MIPSInst_FT(ir
));
1675 rv
.s
= (*handler
.b
) (fs
, ft
);
1678 SPFROMREG(fs
, MIPSInst_FS(ir
));
1679 rv
.s
= (*handler
.u
) (fs
);
1682 if (ieee754_cxtest(IEEE754_INEXACT
))
1683 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1684 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1685 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1686 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1687 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1688 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
1689 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1690 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1691 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1694 /* unary conv ops */
1696 return SIGILL
; /* not defined */
1699 SPFROMREG(fs
, MIPSInst_FS(ir
));
1700 rv
.d
= ieee754dp_fsp(fs
);
1705 SPFROMREG(fs
, MIPSInst_FS(ir
));
1706 rv
.w
= ieee754sp_tint(fs
);
1714 if (!cpu_has_mips_2_3_4_5
&& !cpu_has_mips64
)
1717 oldrm
= ieee754_csr
.rm
;
1718 SPFROMREG(fs
, MIPSInst_FS(ir
));
1719 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1720 rv
.w
= ieee754sp_tint(fs
);
1721 ieee754_csr
.rm
= oldrm
;
1726 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1729 SPFROMREG(fs
, MIPSInst_FS(ir
));
1730 rv
.l
= ieee754sp_tlong(fs
);
1738 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1741 oldrm
= ieee754_csr
.rm
;
1742 SPFROMREG(fs
, MIPSInst_FS(ir
));
1743 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1744 rv
.l
= ieee754sp_tlong(fs
);
1745 ieee754_csr
.rm
= oldrm
;
1750 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1751 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1752 union ieee754sp fs
, ft
;
1754 SPFROMREG(fs
, MIPSInst_FS(ir
));
1755 SPFROMREG(ft
, MIPSInst_FT(ir
));
1756 rv
.w
= ieee754sp_cmp(fs
, ft
,
1757 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1759 if ((cmpop
& 0x8) && ieee754_cxtest
1760 (IEEE754_INVALID_OPERATION
))
1761 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1773 union ieee754dp fs
, ft
;
1775 union ieee754dp(*b
) (union ieee754dp
, union ieee754dp
);
1776 union ieee754dp(*u
) (union ieee754dp
);
1779 switch (MIPSInst_FUNC(ir
)) {
1782 handler
.b
= ieee754dp_add
;
1785 handler
.b
= ieee754dp_sub
;
1788 handler
.b
= ieee754dp_mul
;
1791 handler
.b
= ieee754dp_div
;
1796 if (!cpu_has_mips_2_3_4_5_r
)
1799 handler
.u
= ieee754dp_sqrt
;
1802 * Note that on some MIPS IV implementations such as the
1803 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1804 * achieve full IEEE-754 accuracy - however this emulator does.
1807 if (!cpu_has_mips_4_5_r2
)
1810 handler
.u
= fpemu_dp_rsqrt
;
1813 if (!cpu_has_mips_4_5_r2
)
1816 handler
.u
= fpemu_dp_recip
;
1819 if (!cpu_has_mips_4_5_r
)
1822 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1823 if (((ctx
->fcr31
& cond
) != 0) !=
1824 ((MIPSInst_FT(ir
) & 1) != 0))
1826 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1829 if (!cpu_has_mips_4_5_r
)
1832 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1834 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1837 if (!cpu_has_mips_4_5_r
)
1840 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1842 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1845 handler
.u
= ieee754dp_abs
;
1849 handler
.u
= ieee754dp_neg
;
1854 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1857 /* binary op on handler */
1859 DPFROMREG(fs
, MIPSInst_FS(ir
));
1860 DPFROMREG(ft
, MIPSInst_FT(ir
));
1862 rv
.d
= (*handler
.b
) (fs
, ft
);
1865 DPFROMREG(fs
, MIPSInst_FS(ir
));
1866 rv
.d
= (*handler
.u
) (fs
);
1873 DPFROMREG(fs
, MIPSInst_FS(ir
));
1874 rv
.s
= ieee754sp_fdp(fs
);
1879 return SIGILL
; /* not defined */
1882 DPFROMREG(fs
, MIPSInst_FS(ir
));
1883 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1891 if (!cpu_has_mips_2_3_4_5_r
)
1894 oldrm
= ieee754_csr
.rm
;
1895 DPFROMREG(fs
, MIPSInst_FS(ir
));
1896 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1897 rv
.w
= ieee754dp_tint(fs
);
1898 ieee754_csr
.rm
= oldrm
;
1903 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1906 DPFROMREG(fs
, MIPSInst_FS(ir
));
1907 rv
.l
= ieee754dp_tlong(fs
);
1915 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1918 oldrm
= ieee754_csr
.rm
;
1919 DPFROMREG(fs
, MIPSInst_FS(ir
));
1920 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1921 rv
.l
= ieee754dp_tlong(fs
);
1922 ieee754_csr
.rm
= oldrm
;
1927 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1928 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1929 union ieee754dp fs
, ft
;
1931 DPFROMREG(fs
, MIPSInst_FS(ir
));
1932 DPFROMREG(ft
, MIPSInst_FT(ir
));
1933 rv
.w
= ieee754dp_cmp(fs
, ft
,
1934 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1939 (IEEE754_INVALID_OPERATION
))
1940 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1953 switch (MIPSInst_FUNC(ir
)) {
1955 /* convert word to single precision real */
1956 SPFROMREG(fs
, MIPSInst_FS(ir
));
1957 rv
.s
= ieee754sp_fint(fs
.bits
);
1961 /* convert word to double precision real */
1962 SPFROMREG(fs
, MIPSInst_FS(ir
));
1963 rv
.d
= ieee754dp_fint(fs
.bits
);
1974 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1977 DIFROMREG(bits
, MIPSInst_FS(ir
));
1979 switch (MIPSInst_FUNC(ir
)) {
1981 /* convert long to single precision real */
1982 rv
.s
= ieee754sp_flong(bits
);
1986 /* convert long to double precision real */
1987 rv
.d
= ieee754dp_flong(bits
);
2000 * Update the fpu CSR register for this operation.
2001 * If an exception is required, generate a tidy SIGFPE exception,
2002 * without updating the result register.
2003 * Note: cause exception bits do not accumulate, they are rewritten
2004 * for each op; only the flag/sticky bits accumulate.
2006 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
2007 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
2008 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2013 * Now we can safely write the result back to the register file.
2018 if (cpu_has_mips_4_5_r
)
2019 cbit
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
2021 cbit
= FPU_CSR_COND
;
2025 ctx
->fcr31
&= ~cbit
;
2029 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
2032 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
2035 SITOREG(rv
.w
, MIPSInst_FD(ir
));
2038 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
2041 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2050 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2051 int has_fpu
, void *__user
*fault_addr
)
2053 unsigned long oldepc
, prevepc
;
2054 struct mm_decoded_insn dec_insn
;
2059 oldepc
= xcp
->cp0_epc
;
2061 prevepc
= xcp
->cp0_epc
;
2063 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2065 * Get next 2 microMIPS instructions and convert them
2066 * into 32-bit instructions.
2068 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2069 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2070 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2071 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2072 MIPS_FPU_EMU_INC_STATS(errors
);
2077 /* Get first instruction. */
2078 if (mm_insn_16bit(*instr_ptr
)) {
2079 /* Duplicate the half-word. */
2080 dec_insn
.insn
= (*instr_ptr
<< 16) |
2082 /* 16-bit instruction. */
2083 dec_insn
.pc_inc
= 2;
2086 dec_insn
.insn
= (*instr_ptr
<< 16) |
2088 /* 32-bit instruction. */
2089 dec_insn
.pc_inc
= 4;
2092 /* Get second instruction. */
2093 if (mm_insn_16bit(*instr_ptr
)) {
2094 /* Duplicate the half-word. */
2095 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2097 /* 16-bit instruction. */
2098 dec_insn
.next_pc_inc
= 2;
2100 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2102 /* 32-bit instruction. */
2103 dec_insn
.next_pc_inc
= 4;
2105 dec_insn
.micro_mips_mode
= 1;
2107 if ((get_user(dec_insn
.insn
,
2108 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2109 (get_user(dec_insn
.next_insn
,
2110 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2111 MIPS_FPU_EMU_INC_STATS(errors
);
2114 dec_insn
.pc_inc
= 4;
2115 dec_insn
.next_pc_inc
= 4;
2116 dec_insn
.micro_mips_mode
= 0;
2119 if ((dec_insn
.insn
== 0) ||
2120 ((dec_insn
.pc_inc
== 2) &&
2121 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2122 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2125 * The 'ieee754_csr' is an alias of
2126 * ctx->fcr31. No need to copy ctx->fcr31 to
2127 * ieee754_csr. But ieee754_csr.rm is ieee
2128 * library modes. (not mips rounding mode)
2130 /* convert to ieee library modes */
2131 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
2132 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2133 /* revert to mips rounding mode */
2134 ieee754_csr
.rm
= mips_rm
[ieee754_csr
.rm
];
2143 } while (xcp
->cp0_epc
> prevepc
);
2145 /* SIGILL indicates a non-fpu instruction */
2146 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2147 /* but if EPC has advanced, then ignore it */