2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-r2-to-r6-emul.h>
56 /* Function which emulates a floating point instruction. */
58 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
61 static int fpux_emu(struct pt_regs
*,
62 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
64 /* Control registers */
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit
[8] = {
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
95 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
97 union mips_instruction insn
= *insn_ptr
;
98 union mips_instruction mips32_insn
= insn
;
101 switch (insn
.mm_i_format
.opcode
) {
103 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
104 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
105 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
108 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
109 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
110 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
113 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
114 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
115 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
118 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
119 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
120 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
125 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
126 mips32_insn
.fb_format
.opcode
= cop1_op
;
127 mips32_insn
.fb_format
.bc
= bc_op
;
128 mips32_insn
.fb_format
.flag
=
129 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
134 switch (insn
.mm_fp0_format
.func
) {
143 op
= insn
.mm_fp0_format
.func
;
144 if (op
== mm_32f_01_op
)
146 else if (op
== mm_32f_11_op
)
148 else if (op
== mm_32f_02_op
)
150 else if (op
== mm_32f_12_op
)
152 else if (op
== mm_32f_41_op
)
154 else if (op
== mm_32f_51_op
)
156 else if (op
== mm_32f_42_op
)
160 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
161 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
162 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
163 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
164 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
165 mips32_insn
.fp6_format
.func
= func
;
168 func
= -1; /* Invalid */
169 op
= insn
.mm_fp5_format
.op
& 0x7;
170 if (op
== mm_ldxc1_op
)
172 else if (op
== mm_sdxc1_op
)
174 else if (op
== mm_lwxc1_op
)
176 else if (op
== mm_swxc1_op
)
180 mips32_insn
.r_format
.opcode
= cop1x_op
;
181 mips32_insn
.r_format
.rs
=
182 insn
.mm_fp5_format
.base
;
183 mips32_insn
.r_format
.rt
=
184 insn
.mm_fp5_format
.index
;
185 mips32_insn
.r_format
.rd
= 0;
186 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
187 mips32_insn
.r_format
.func
= func
;
192 op
= -1; /* Invalid */
193 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
195 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
198 mips32_insn
.fp0_format
.opcode
= cop1_op
;
199 mips32_insn
.fp0_format
.fmt
=
200 sdps_format
[insn
.mm_fp2_format
.fmt
];
201 mips32_insn
.fp0_format
.ft
=
202 (insn
.mm_fp2_format
.cc
<<2) + op
;
203 mips32_insn
.fp0_format
.fs
=
204 insn
.mm_fp2_format
.fs
;
205 mips32_insn
.fp0_format
.fd
=
206 insn
.mm_fp2_format
.fd
;
207 mips32_insn
.fp0_format
.func
= fmovc_op
;
212 func
= -1; /* Invalid */
213 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
215 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
217 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
219 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
222 mips32_insn
.fp0_format
.opcode
= cop1_op
;
223 mips32_insn
.fp0_format
.fmt
=
224 sdps_format
[insn
.mm_fp0_format
.fmt
];
225 mips32_insn
.fp0_format
.ft
=
226 insn
.mm_fp0_format
.ft
;
227 mips32_insn
.fp0_format
.fs
=
228 insn
.mm_fp0_format
.fs
;
229 mips32_insn
.fp0_format
.fd
=
230 insn
.mm_fp0_format
.fd
;
231 mips32_insn
.fp0_format
.func
= func
;
236 func
= -1; /* Invalid */
237 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
239 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
242 mips32_insn
.fp0_format
.opcode
= cop1_op
;
243 mips32_insn
.fp0_format
.fmt
=
244 sdps_format
[insn
.mm_fp0_format
.fmt
];
245 mips32_insn
.fp0_format
.ft
=
246 insn
.mm_fp0_format
.ft
;
247 mips32_insn
.fp0_format
.fs
=
248 insn
.mm_fp0_format
.fs
;
249 mips32_insn
.fp0_format
.fd
=
250 insn
.mm_fp0_format
.fd
;
251 mips32_insn
.fp0_format
.func
= func
;
255 case mm_32f_73_op
: /* POOL32FXF */
256 switch (insn
.mm_fp1_format
.op
) {
261 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
266 mips32_insn
.r_format
.opcode
= spec_op
;
267 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
268 mips32_insn
.r_format
.rt
=
269 (insn
.mm_fp4_format
.cc
<< 2) + op
;
270 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
271 mips32_insn
.r_format
.re
= 0;
272 mips32_insn
.r_format
.func
= movc_op
;
278 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
281 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
284 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
286 mips32_insn
.fp0_format
.opcode
= cop1_op
;
287 mips32_insn
.fp0_format
.fmt
= fmt
;
288 mips32_insn
.fp0_format
.ft
= 0;
289 mips32_insn
.fp0_format
.fs
=
290 insn
.mm_fp3_format
.fs
;
291 mips32_insn
.fp0_format
.fd
=
292 insn
.mm_fp3_format
.rt
;
293 mips32_insn
.fp0_format
.func
= func
;
301 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
304 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
309 mips32_insn
.fp0_format
.opcode
= cop1_op
;
310 mips32_insn
.fp0_format
.fmt
=
311 sdps_format
[insn
.mm_fp3_format
.fmt
];
312 mips32_insn
.fp0_format
.ft
= 0;
313 mips32_insn
.fp0_format
.fs
=
314 insn
.mm_fp3_format
.fs
;
315 mips32_insn
.fp0_format
.fd
=
316 insn
.mm_fp3_format
.rt
;
317 mips32_insn
.fp0_format
.func
= func
;
329 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
331 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
333 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
335 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
337 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
339 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
341 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
343 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
345 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
349 mips32_insn
.fp0_format
.opcode
= cop1_op
;
350 mips32_insn
.fp0_format
.fmt
=
351 sd_format
[insn
.mm_fp1_format
.fmt
];
352 mips32_insn
.fp0_format
.ft
= 0;
353 mips32_insn
.fp0_format
.fs
=
354 insn
.mm_fp1_format
.fs
;
355 mips32_insn
.fp0_format
.fd
=
356 insn
.mm_fp1_format
.rt
;
357 mips32_insn
.fp0_format
.func
= func
;
362 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
364 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
368 mips32_insn
.fp0_format
.opcode
= cop1_op
;
369 mips32_insn
.fp0_format
.fmt
=
370 sdps_format
[insn
.mm_fp1_format
.fmt
];
371 mips32_insn
.fp0_format
.ft
= 0;
372 mips32_insn
.fp0_format
.fs
=
373 insn
.mm_fp1_format
.fs
;
374 mips32_insn
.fp0_format
.fd
=
375 insn
.mm_fp1_format
.rt
;
376 mips32_insn
.fp0_format
.func
= func
;
384 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
386 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
388 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
390 else if (insn
.mm_fp1_format
.op
== mm_ctc1_op
)
392 else if (insn
.mm_fp1_format
.op
== mm_mfhc1_op
)
396 mips32_insn
.fp1_format
.opcode
= cop1_op
;
397 mips32_insn
.fp1_format
.op
= op
;
398 mips32_insn
.fp1_format
.rt
=
399 insn
.mm_fp1_format
.rt
;
400 mips32_insn
.fp1_format
.fs
=
401 insn
.mm_fp1_format
.fs
;
402 mips32_insn
.fp1_format
.fd
= 0;
403 mips32_insn
.fp1_format
.func
= 0;
409 case mm_32f_74_op
: /* c.cond.fmt */
410 mips32_insn
.fp0_format
.opcode
= cop1_op
;
411 mips32_insn
.fp0_format
.fmt
=
412 sdps_format
[insn
.mm_fp4_format
.fmt
];
413 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
414 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
415 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
416 mips32_insn
.fp0_format
.func
=
417 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
427 *insn_ptr
= mips32_insn
;
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
437 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
438 unsigned long *contpc
)
440 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
442 unsigned int bit
= 0;
444 switch (insn
.i_format
.opcode
) {
446 switch (insn
.r_format
.func
) {
448 regs
->regs
[insn
.r_format
.rd
] =
449 regs
->cp0_epc
+ dec_insn
.pc_inc
+
450 dec_insn
.next_pc_inc
;
453 /* For R6, JR already emulated in jalr_op */
454 if (NO_R6EMU
&& insn
.r_format
.func
== jr_op
)
456 *contpc
= regs
->regs
[insn
.r_format
.rs
];
461 switch (insn
.i_format
.rt
) {
464 if (NO_R6EMU
&& (insn
.i_format
.rs
||
465 insn
.i_format
.rt
== bltzall_op
))
468 regs
->regs
[31] = regs
->cp0_epc
+
470 dec_insn
.next_pc_inc
;
476 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
477 *contpc
= regs
->cp0_epc
+
479 (insn
.i_format
.simmediate
<< 2);
481 *contpc
= regs
->cp0_epc
+
483 dec_insn
.next_pc_inc
;
487 if (NO_R6EMU
&& (insn
.i_format
.rs
||
488 insn
.i_format
.rt
== bgezall_op
))
491 regs
->regs
[31] = regs
->cp0_epc
+
493 dec_insn
.next_pc_inc
;
499 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
500 *contpc
= regs
->cp0_epc
+
502 (insn
.i_format
.simmediate
<< 2);
504 *contpc
= regs
->cp0_epc
+
506 dec_insn
.next_pc_inc
;
513 regs
->regs
[31] = regs
->cp0_epc
+
515 dec_insn
.next_pc_inc
;
518 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
521 *contpc
|= (insn
.j_format
.target
<< 2);
522 /* Set microMIPS mode bit: XOR for jalx. */
529 if (regs
->regs
[insn
.i_format
.rs
] ==
530 regs
->regs
[insn
.i_format
.rt
])
531 *contpc
= regs
->cp0_epc
+
533 (insn
.i_format
.simmediate
<< 2);
535 *contpc
= regs
->cp0_epc
+
537 dec_insn
.next_pc_inc
;
543 if (regs
->regs
[insn
.i_format
.rs
] !=
544 regs
->regs
[insn
.i_format
.rt
])
545 *contpc
= regs
->cp0_epc
+
547 (insn
.i_format
.simmediate
<< 2);
549 *contpc
= regs
->cp0_epc
+
551 dec_insn
.next_pc_inc
;
554 if (!insn
.i_format
.rt
&& NO_R6EMU
)
559 * Compact branches for R6 for the
560 * blez and blezl opcodes.
561 * BLEZ | rs = 0 | rt != 0 == BLEZALC
562 * BLEZ | rs = rt != 0 == BGEZALC
563 * BLEZ | rs != 0 | rt != 0 == BGEUC
564 * BLEZL | rs = 0 | rt != 0 == BLEZC
565 * BLEZL | rs = rt != 0 == BGEZC
566 * BLEZL | rs != 0 | rt != 0 == BGEC
568 * For real BLEZ{,L}, rt is always 0.
570 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
571 if ((insn
.i_format
.opcode
== blez_op
) &&
572 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
573 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
574 regs
->regs
[31] = regs
->cp0_epc
+
576 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
577 dec_insn
.next_pc_inc
;
581 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
582 *contpc
= regs
->cp0_epc
+
584 (insn
.i_format
.simmediate
<< 2);
586 *contpc
= regs
->cp0_epc
+
588 dec_insn
.next_pc_inc
;
591 if (!insn
.i_format
.rt
&& NO_R6EMU
)
595 * Compact branches for R6 for the
596 * bgtz and bgtzl opcodes.
597 * BGTZ | rs = 0 | rt != 0 == BGTZALC
598 * BGTZ | rs = rt != 0 == BLTZALC
599 * BGTZ | rs != 0 | rt != 0 == BLTUC
600 * BGTZL | rs = 0 | rt != 0 == BGTZC
601 * BGTZL | rs = rt != 0 == BLTZC
602 * BGTZL | rs != 0 | rt != 0 == BLTC
604 * *ZALC varint for BGTZ &&& rt != 0
605 * For real GTZ{,L}, rt is always 0.
607 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
608 if ((insn
.i_format
.opcode
== blez_op
) &&
609 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
610 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
611 regs
->regs
[31] = regs
->cp0_epc
+
613 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
614 dec_insn
.next_pc_inc
;
619 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
620 *contpc
= regs
->cp0_epc
+
622 (insn
.i_format
.simmediate
<< 2);
624 *contpc
= regs
->cp0_epc
+
626 dec_insn
.next_pc_inc
;
630 if (!cpu_has_mips_r6
)
632 if (insn
.i_format
.rt
&& !insn
.i_format
.rs
)
633 regs
->regs
[31] = regs
->cp0_epc
+ 4;
634 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
635 dec_insn
.next_pc_inc
;
638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
639 case lwc2_op
: /* This is bbit0 on Octeon */
640 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
641 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
643 *contpc
= regs
->cp0_epc
+ 8;
645 case ldc2_op
: /* This is bbit032 on Octeon */
646 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
647 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
649 *contpc
= regs
->cp0_epc
+ 8;
651 case swc2_op
: /* This is bbit1 on Octeon */
652 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
653 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
655 *contpc
= regs
->cp0_epc
+ 8;
657 case sdc2_op
: /* This is bbit132 on Octeon */
658 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
659 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
661 *contpc
= regs
->cp0_epc
+ 8;
666 * Only valid for MIPS R6 but we can still end up
667 * here from a broken userland so just tell emulator
668 * this is not a branch and let it break later on.
670 if (!cpu_has_mips_r6
)
672 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
673 dec_insn
.next_pc_inc
;
677 if (!cpu_has_mips_r6
)
679 regs
->regs
[31] = regs
->cp0_epc
+ 4;
680 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
681 dec_insn
.next_pc_inc
;
685 if (!cpu_has_mips_r6
)
687 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
688 dec_insn
.next_pc_inc
;
692 if (!cpu_has_mips_r6
)
694 if (!insn
.i_format
.rs
)
695 regs
->regs
[31] = regs
->cp0_epc
+ 4;
696 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
697 dec_insn
.next_pc_inc
;
703 /* Need to check for R6 bc1nez and bc1eqz branches */
704 if (cpu_has_mips_r6
&&
705 ((insn
.i_format
.rs
== bc1eqz_op
) ||
706 (insn
.i_format
.rs
== bc1nez_op
))) {
708 switch (insn
.i_format
.rs
) {
710 if (get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1)
714 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1))
719 *contpc
= regs
->cp0_epc
+
721 (insn
.i_format
.simmediate
<< 2);
723 *contpc
= regs
->cp0_epc
+
725 dec_insn
.next_pc_inc
;
729 /* R2/R6 compatible cop1 instruction. Fall through */
732 if (insn
.i_format
.rs
== bc_op
) {
735 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
737 fcr31
= current
->thread
.fpu
.fcr31
;
740 bit
= (insn
.i_format
.rt
>> 2);
743 switch (insn
.i_format
.rt
& 3) {
746 if (~fcr31
& (1 << bit
))
747 *contpc
= regs
->cp0_epc
+
749 (insn
.i_format
.simmediate
<< 2);
751 *contpc
= regs
->cp0_epc
+
753 dec_insn
.next_pc_inc
;
757 if (fcr31
& (1 << bit
))
758 *contpc
= regs
->cp0_epc
+
760 (insn
.i_format
.simmediate
<< 2);
762 *contpc
= regs
->cp0_epc
+
764 dec_insn
.next_pc_inc
;
774 * In the Linux kernel, we support selection of FPR format on the
775 * basis of the Status.FR bit. If an FPU is not present, the FR bit
776 * is hardwired to zero, which would imply a 32-bit FPU even for
777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
778 * FPU emu is slow and bulky and optimizing this function offers fairly
779 * sizeable benefits so we try to be clever and make this function return
780 * a constant whenever possible, that is on 64-bit kernels without O32
781 * compatibility enabled and on 32-bit without 64-bit FPU support.
783 static inline int cop1_64bit(struct pt_regs
*xcp
)
785 if (config_enabled(CONFIG_64BIT
) && !config_enabled(CONFIG_MIPS32_O32
))
787 else if (config_enabled(CONFIG_32BIT
) &&
788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT
))
791 return !test_thread_flag(TIF_32BIT_FPREGS
);
794 static inline bool hybrid_fprs(void)
796 return test_thread_flag(TIF_HYBRID_FPREGS
);
799 #define SIFROMREG(si, x) \
801 if (cop1_64bit(xcp) && !hybrid_fprs()) \
802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
807 #define SITOREG(si, x) \
809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
811 set_fpr32(&ctx->fpr[x], 0, si); \
812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
813 set_fpr32(&ctx->fpr[x], i, 0); \
815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
819 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
821 #define SITOHREG(si, x) \
824 set_fpr32(&ctx->fpr[x], 1, si); \
825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
826 set_fpr32(&ctx->fpr[x], i, 0); \
829 #define DIFROMREG(di, x) \
830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
832 #define DITOREG(di, x) \
835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
836 set_fpr64(&ctx->fpr[fpr], 0, di); \
837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
838 set_fpr64(&ctx->fpr[fpr], i, 0); \
841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
843 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
844 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
847 * Emulate a CFC1 instruction.
849 static inline void cop1_cfc(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
852 u32 fcr31
= ctx
->fcr31
;
855 switch (MIPSInst_RD(ir
)) {
858 pr_debug("%p gpr[%d]<-csr=%08x\n",
859 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
865 value
= (fcr31
>> (FPU_CSR_FS_S
- MIPS_FENR_FS_S
)) &
867 value
|= fcr31
& (FPU_CSR_ALL_E
| FPU_CSR_RM
);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
875 value
= fcr31
& (FPU_CSR_ALL_X
| FPU_CSR_ALL_S
);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
883 value
= (fcr31
>> (FPU_CSR_COND_S
- MIPS_FCCR_COND0_S
)) &
885 value
|= (fcr31
>> (FPU_CSR_COND1_S
- MIPS_FCCR_COND1_S
)) &
886 (MIPS_FCCR_CONDX
& ~MIPS_FCCR_COND0
);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
892 value
= boot_cpu_data
.fpu_id
;
900 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
904 * Emulate a CTC1 instruction.
906 static inline void cop1_ctc(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
909 u32 fcr31
= ctx
->fcr31
;
913 if (MIPSInst_RT(ir
) == 0)
916 value
= xcp
->regs
[MIPSInst_RT(ir
)];
918 switch (MIPSInst_RD(ir
)) {
920 pr_debug("%p gpr[%d]->csr=%08x\n",
921 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
923 /* Preserve read-only bits. */
924 mask
= boot_cpu_data
.fpu_msk31
;
925 fcr31
= (value
& ~mask
) | (fcr31
& mask
);
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
933 fcr31
&= ~(FPU_CSR_FS
| FPU_CSR_ALL_E
| FPU_CSR_RM
);
934 fcr31
|= (value
<< (FPU_CSR_FS_S
- MIPS_FENR_FS_S
)) &
936 fcr31
|= value
& (FPU_CSR_ALL_E
| FPU_CSR_RM
);
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
944 fcr31
&= ~(FPU_CSR_ALL_X
| FPU_CSR_ALL_S
);
945 fcr31
|= value
& (FPU_CSR_ALL_X
| FPU_CSR_ALL_S
);
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp
->cp0_epc
, MIPSInst_RT(ir
), value
);
953 fcr31
&= ~(FPU_CSR_CONDX
| FPU_CSR_COND
);
954 fcr31
|= (value
<< (FPU_CSR_COND_S
- MIPS_FCCR_COND0_S
)) &
956 fcr31
|= (value
<< (FPU_CSR_COND1_S
- MIPS_FCCR_COND1_S
)) &
968 * Emulate the single floating point instruction pointed at by EPC.
969 * Two instructions if the instruction is in a branch delay slot.
972 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
973 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
975 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
976 unsigned int cond
, cbit
;
986 * These are giving gcc a gentle hint about what to expect in
987 * dec_inst in order to do better optimization.
989 if (!cpu_has_mmips
&& dec_insn
.micro_mips_mode
)
992 /* XXX NEC Vr54xx bug workaround */
993 if (delay_slot(xcp
)) {
994 if (dec_insn
.micro_mips_mode
) {
995 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
996 clear_delay_slot(xcp
);
998 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
999 clear_delay_slot(xcp
);
1003 if (delay_slot(xcp
)) {
1005 * The instruction to be emulated is in a branch delay slot
1006 * which means that we have to emulate the branch instruction
1007 * BEFORE we do the cop1 instruction.
1009 * This branch could be a COP1 branch, but in that case we
1010 * would have had a trap for that instruction, and would not
1011 * come through this route.
1013 * Linux MIPS branch emulator operates on context, updating the
1016 ir
= dec_insn
.next_insn
; /* process delay slot instr */
1017 pc_inc
= dec_insn
.next_pc_inc
;
1019 ir
= dec_insn
.insn
; /* process current instr */
1020 pc_inc
= dec_insn
.pc_inc
;
1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025 * instructions, we want to convert microMIPS FPU instructions
1026 * into MIPS32 instructions so that we could reuse all of the
1027 * FPU emulation code.
1029 * NOTE: We cannot do this for branch instructions since they
1030 * are not a subset. Example: Cannot emulate a 16-bit
1031 * aligned target address with a MIPS32 instruction.
1033 if (dec_insn
.micro_mips_mode
) {
1035 * If next instruction is a 16-bit instruction, then it
1036 * it cannot be a FPU instruction. This could happen
1037 * since we can be called for non-FPU instructions.
1039 if ((pc_inc
== 2) ||
1040 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
1047 MIPS_FPU_EMU_INC_STATS(emulated
);
1048 switch (MIPSInst_OPCODE(ir
)) {
1050 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1052 MIPS_FPU_EMU_INC_STATS(loads
);
1054 if (!access_ok(VERIFY_READ
, dva
, sizeof(u64
))) {
1055 MIPS_FPU_EMU_INC_STATS(errors
);
1059 if (__get_user(dval
, dva
)) {
1060 MIPS_FPU_EMU_INC_STATS(errors
);
1064 DITOREG(dval
, MIPSInst_RT(ir
));
1068 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1070 MIPS_FPU_EMU_INC_STATS(stores
);
1071 DIFROMREG(dval
, MIPSInst_RT(ir
));
1072 if (!access_ok(VERIFY_WRITE
, dva
, sizeof(u64
))) {
1073 MIPS_FPU_EMU_INC_STATS(errors
);
1077 if (__put_user(dval
, dva
)) {
1078 MIPS_FPU_EMU_INC_STATS(errors
);
1085 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1087 MIPS_FPU_EMU_INC_STATS(loads
);
1088 if (!access_ok(VERIFY_READ
, wva
, sizeof(u32
))) {
1089 MIPS_FPU_EMU_INC_STATS(errors
);
1093 if (__get_user(wval
, wva
)) {
1094 MIPS_FPU_EMU_INC_STATS(errors
);
1098 SITOREG(wval
, MIPSInst_RT(ir
));
1102 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1104 MIPS_FPU_EMU_INC_STATS(stores
);
1105 SIFROMREG(wval
, MIPSInst_RT(ir
));
1106 if (!access_ok(VERIFY_WRITE
, wva
, sizeof(u32
))) {
1107 MIPS_FPU_EMU_INC_STATS(errors
);
1111 if (__put_user(wval
, wva
)) {
1112 MIPS_FPU_EMU_INC_STATS(errors
);
1119 switch (MIPSInst_RS(ir
)) {
1121 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1124 /* copregister fs -> gpr[rt] */
1125 if (MIPSInst_RT(ir
) != 0) {
1126 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1132 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1135 /* copregister fs <- rt */
1136 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1140 if (!cpu_has_mips_r2_r6
)
1143 /* copregister rd -> gpr[rt] */
1144 if (MIPSInst_RT(ir
) != 0) {
1145 SIFROMHREG(xcp
->regs
[MIPSInst_RT(ir
)],
1151 if (!cpu_has_mips_r2_r6
)
1154 /* copregister rd <- gpr[rt] */
1155 SITOHREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1159 /* copregister rd -> gpr[rt] */
1160 if (MIPSInst_RT(ir
) != 0) {
1161 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1167 /* copregister rd <- rt */
1168 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1172 /* cop control register rd -> gpr[rt] */
1173 cop1_cfc(xcp
, ctx
, ir
);
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp
, ctx
, ir
);
1179 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1186 if (!cpu_has_mips_r6
|| delay_slot(xcp
))
1190 switch (MIPSInst_RS(ir
)) {
1192 if (get_fpr32(¤t
->thread
.fpu
.fpr
[MIPSInst_RT(ir
)], 0) & 0x1)
1196 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[MIPSInst_RT(ir
)], 0) & 0x1))
1203 if (delay_slot(xcp
))
1206 if (cpu_has_mips_4_5_r
)
1207 cbit
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1209 cbit
= FPU_CSR_COND
;
1210 cond
= ctx
->fcr31
& cbit
;
1213 switch (MIPSInst_RT(ir
) & 3) {
1215 if (cpu_has_mips_2_3_4_5_r
)
1222 if (cpu_has_mips_2_3_4_5_r
)
1229 set_delay_slot(xcp
);
1232 * Branch taken: emulate dslot instruction
1237 * Remember EPC at the branch to point back
1238 * at so that any delay-slot instruction
1239 * signal is not silently ignored.
1241 bcpc
= xcp
->cp0_epc
;
1242 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1244 contpc
= MIPSInst_SIMM(ir
);
1245 ir
= dec_insn
.next_insn
;
1246 if (dec_insn
.micro_mips_mode
) {
1247 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1249 /* If 16-bit instruction, not FPU. */
1250 if ((dec_insn
.next_pc_inc
== 2) ||
1251 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1254 * Since this instruction will
1255 * be put on the stack with
1256 * 32-bit words, get around
1257 * this problem by putting a
1258 * NOP16 as the second one.
1260 if (dec_insn
.next_pc_inc
== 2)
1261 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1264 * Single step the non-CP1
1265 * instruction in the dslot.
1267 sig
= mips_dsemul(xcp
, ir
,
1270 xcp
->cp0_epc
= bcpc
;
1272 * SIGILL forces out of
1273 * the emulation loop.
1275 return sig
? sig
: SIGILL
;
1278 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1280 switch (MIPSInst_OPCODE(ir
)) {
1287 if (cpu_has_mips_2_3_4_5_r
)
1296 if (cpu_has_mips_4_5_64_r2_r6
)
1297 /* its one of ours */
1303 switch (MIPSInst_FUNC(ir
)) {
1305 if (cpu_has_mips_4_5_r
)
1313 xcp
->cp0_epc
= bcpc
;
1318 * Single step the non-cp1
1319 * instruction in the dslot
1321 sig
= mips_dsemul(xcp
, ir
, contpc
);
1323 xcp
->cp0_epc
= bcpc
;
1324 /* SIGILL forces out of the emulation loop. */
1325 return sig
? sig
: SIGILL
;
1326 } else if (likely
) { /* branch not taken */
1328 * branch likely nullifies
1329 * dslot if not taken
1331 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1332 contpc
+= dec_insn
.pc_inc
;
1334 * else continue & execute
1335 * dslot as normal insn
1341 if (!(MIPSInst_RS(ir
) & 0x10))
1344 /* a real fpu computation instruction */
1345 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1351 if (!cpu_has_mips_4_5_64_r2_r6
)
1354 sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1360 if (!cpu_has_mips_4_5_r
)
1363 if (MIPSInst_FUNC(ir
) != movc_op
)
1365 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1366 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1367 xcp
->regs
[MIPSInst_RD(ir
)] =
1368 xcp
->regs
[MIPSInst_RS(ir
)];
1376 xcp
->cp0_epc
= contpc
;
1377 clear_delay_slot(xcp
);
1383 * Conversion table from MIPS compare ops 48-63
1384 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1386 static const unsigned char cmptab
[8] = {
1387 0, /* cmp_0 (sig) cmp_sf */
1388 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1389 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1390 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1391 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1392 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1393 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1394 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1399 * Additional MIPS4 instructions
1402 #define DEF3OP(name, p, f1, f2, f3) \
1403 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1404 union ieee754##p s, union ieee754##p t) \
1406 struct _ieee754_csr ieee754_csr_save; \
1408 ieee754_csr_save = ieee754_csr; \
1410 ieee754_csr_save.cx |= ieee754_csr.cx; \
1411 ieee754_csr_save.sx |= ieee754_csr.sx; \
1413 ieee754_csr.cx |= ieee754_csr_save.cx; \
1414 ieee754_csr.sx |= ieee754_csr_save.sx; \
1418 static union ieee754dp
fpemu_dp_recip(union ieee754dp d
)
1420 return ieee754dp_div(ieee754dp_one(0), d
);
1423 static union ieee754dp
fpemu_dp_rsqrt(union ieee754dp d
)
1425 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1428 static union ieee754sp
fpemu_sp_recip(union ieee754sp s
)
1430 return ieee754sp_div(ieee754sp_one(0), s
);
1433 static union ieee754sp
fpemu_sp_rsqrt(union ieee754sp s
)
1435 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1438 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1439 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1440 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1441 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1442 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1443 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1444 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1445 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1447 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1448 mips_instruction ir
, void *__user
*fault_addr
)
1450 unsigned rcsr
= 0; /* resulting csr */
1452 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1454 switch (MIPSInst_FMA_FFMT(ir
)) {
1455 case s_fmt
:{ /* 0 */
1457 union ieee754sp(*handler
) (union ieee754sp
, union ieee754sp
, union ieee754sp
);
1458 union ieee754sp fd
, fr
, fs
, ft
;
1462 switch (MIPSInst_FUNC(ir
)) {
1464 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1465 xcp
->regs
[MIPSInst_FT(ir
)]);
1467 MIPS_FPU_EMU_INC_STATS(loads
);
1468 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1469 MIPS_FPU_EMU_INC_STATS(errors
);
1473 if (__get_user(val
, va
)) {
1474 MIPS_FPU_EMU_INC_STATS(errors
);
1478 SITOREG(val
, MIPSInst_FD(ir
));
1482 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1483 xcp
->regs
[MIPSInst_FT(ir
)]);
1485 MIPS_FPU_EMU_INC_STATS(stores
);
1487 SIFROMREG(val
, MIPSInst_FS(ir
));
1488 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1489 MIPS_FPU_EMU_INC_STATS(errors
);
1493 if (put_user(val
, va
)) {
1494 MIPS_FPU_EMU_INC_STATS(errors
);
1501 handler
= fpemu_sp_madd
;
1504 handler
= fpemu_sp_msub
;
1507 handler
= fpemu_sp_nmadd
;
1510 handler
= fpemu_sp_nmsub
;
1514 SPFROMREG(fr
, MIPSInst_FR(ir
));
1515 SPFROMREG(fs
, MIPSInst_FS(ir
));
1516 SPFROMREG(ft
, MIPSInst_FT(ir
));
1517 fd
= (*handler
) (fr
, fs
, ft
);
1518 SPTOREG(fd
, MIPSInst_FD(ir
));
1521 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1522 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1523 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1525 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1526 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1527 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1529 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1530 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1531 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1533 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1534 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1535 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1538 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1539 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1540 /*printk ("SIGFPE: FPU csr = %08x\n",
1553 case d_fmt
:{ /* 1 */
1554 union ieee754dp(*handler
) (union ieee754dp
, union ieee754dp
, union ieee754dp
);
1555 union ieee754dp fd
, fr
, fs
, ft
;
1559 switch (MIPSInst_FUNC(ir
)) {
1561 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1562 xcp
->regs
[MIPSInst_FT(ir
)]);
1564 MIPS_FPU_EMU_INC_STATS(loads
);
1565 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1566 MIPS_FPU_EMU_INC_STATS(errors
);
1570 if (__get_user(val
, va
)) {
1571 MIPS_FPU_EMU_INC_STATS(errors
);
1575 DITOREG(val
, MIPSInst_FD(ir
));
1579 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1580 xcp
->regs
[MIPSInst_FT(ir
)]);
1582 MIPS_FPU_EMU_INC_STATS(stores
);
1583 DIFROMREG(val
, MIPSInst_FS(ir
));
1584 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1585 MIPS_FPU_EMU_INC_STATS(errors
);
1589 if (__put_user(val
, va
)) {
1590 MIPS_FPU_EMU_INC_STATS(errors
);
1597 handler
= fpemu_dp_madd
;
1600 handler
= fpemu_dp_msub
;
1603 handler
= fpemu_dp_nmadd
;
1606 handler
= fpemu_dp_nmsub
;
1610 DPFROMREG(fr
, MIPSInst_FR(ir
));
1611 DPFROMREG(fs
, MIPSInst_FS(ir
));
1612 DPFROMREG(ft
, MIPSInst_FT(ir
));
1613 fd
= (*handler
) (fr
, fs
, ft
);
1614 DPTOREG(fd
, MIPSInst_FD(ir
));
1624 if (MIPSInst_FUNC(ir
) != pfetch_op
)
1627 /* ignore prefx operation */
1640 * Emulate a single COP1 arithmetic instruction.
1642 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1643 mips_instruction ir
)
1645 int rfmt
; /* resulting format */
1646 unsigned rcsr
= 0; /* resulting csr */
1655 } rv
; /* resulting value */
1658 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1659 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1660 case s_fmt
: { /* 0 */
1662 union ieee754sp(*b
) (union ieee754sp
, union ieee754sp
);
1663 union ieee754sp(*u
) (union ieee754sp
);
1665 union ieee754sp fs
, ft
;
1667 switch (MIPSInst_FUNC(ir
)) {
1670 handler
.b
= ieee754sp_add
;
1673 handler
.b
= ieee754sp_sub
;
1676 handler
.b
= ieee754sp_mul
;
1679 handler
.b
= ieee754sp_div
;
1684 if (!cpu_has_mips_2_3_4_5_r
)
1687 handler
.u
= ieee754sp_sqrt
;
1691 * Note that on some MIPS IV implementations such as the
1692 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1693 * achieve full IEEE-754 accuracy - however this emulator does.
1696 if (!cpu_has_mips_4_5_64_r2_r6
)
1699 handler
.u
= fpemu_sp_rsqrt
;
1703 if (!cpu_has_mips_4_5_64_r2_r6
)
1706 handler
.u
= fpemu_sp_recip
;
1710 if (!cpu_has_mips_4_5_r
)
1713 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1714 if (((ctx
->fcr31
& cond
) != 0) !=
1715 ((MIPSInst_FT(ir
) & 1) != 0))
1717 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1721 if (!cpu_has_mips_4_5_r
)
1724 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1726 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1730 if (!cpu_has_mips_4_5_r
)
1733 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1735 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1739 handler
.u
= ieee754sp_abs
;
1743 handler
.u
= ieee754sp_neg
;
1748 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1751 /* binary op on handler */
1753 SPFROMREG(fs
, MIPSInst_FS(ir
));
1754 SPFROMREG(ft
, MIPSInst_FT(ir
));
1756 rv
.s
= (*handler
.b
) (fs
, ft
);
1759 SPFROMREG(fs
, MIPSInst_FS(ir
));
1760 rv
.s
= (*handler
.u
) (fs
);
1763 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1764 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1765 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1767 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1768 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1769 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1771 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1772 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1773 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1775 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
)) {
1776 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv
);
1777 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1779 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1780 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1781 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1785 /* unary conv ops */
1787 return SIGILL
; /* not defined */
1790 SPFROMREG(fs
, MIPSInst_FS(ir
));
1791 rv
.d
= ieee754dp_fsp(fs
);
1796 SPFROMREG(fs
, MIPSInst_FS(ir
));
1797 rv
.w
= ieee754sp_tint(fs
);
1805 if (!cpu_has_mips_2_3_4_5_r
)
1808 oldrm
= ieee754_csr
.rm
;
1809 SPFROMREG(fs
, MIPSInst_FS(ir
));
1810 ieee754_csr
.rm
= MIPSInst_FUNC(ir
);
1811 rv
.w
= ieee754sp_tint(fs
);
1812 ieee754_csr
.rm
= oldrm
;
1817 if (!cpu_has_mips_3_4_5_64_r2_r6
)
1820 SPFROMREG(fs
, MIPSInst_FS(ir
));
1821 rv
.l
= ieee754sp_tlong(fs
);
1829 if (!cpu_has_mips_3_4_5_64_r2_r6
)
1832 oldrm
= ieee754_csr
.rm
;
1833 SPFROMREG(fs
, MIPSInst_FS(ir
));
1834 ieee754_csr
.rm
= MIPSInst_FUNC(ir
);
1835 rv
.l
= ieee754sp_tlong(fs
);
1836 ieee754_csr
.rm
= oldrm
;
1841 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1842 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1843 union ieee754sp fs
, ft
;
1845 SPFROMREG(fs
, MIPSInst_FS(ir
));
1846 SPFROMREG(ft
, MIPSInst_FT(ir
));
1847 rv
.w
= ieee754sp_cmp(fs
, ft
,
1848 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1850 if ((cmpop
& 0x8) && ieee754_cxtest
1851 (IEEE754_INVALID_OPERATION
))
1852 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1864 union ieee754dp fs
, ft
;
1866 union ieee754dp(*b
) (union ieee754dp
, union ieee754dp
);
1867 union ieee754dp(*u
) (union ieee754dp
);
1870 switch (MIPSInst_FUNC(ir
)) {
1873 handler
.b
= ieee754dp_add
;
1876 handler
.b
= ieee754dp_sub
;
1879 handler
.b
= ieee754dp_mul
;
1882 handler
.b
= ieee754dp_div
;
1887 if (!cpu_has_mips_2_3_4_5_r
)
1890 handler
.u
= ieee754dp_sqrt
;
1893 * Note that on some MIPS IV implementations such as the
1894 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1895 * achieve full IEEE-754 accuracy - however this emulator does.
1898 if (!cpu_has_mips_4_5_64_r2_r6
)
1901 handler
.u
= fpemu_dp_rsqrt
;
1904 if (!cpu_has_mips_4_5_64_r2_r6
)
1907 handler
.u
= fpemu_dp_recip
;
1910 if (!cpu_has_mips_4_5_r
)
1913 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1914 if (((ctx
->fcr31
& cond
) != 0) !=
1915 ((MIPSInst_FT(ir
) & 1) != 0))
1917 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1920 if (!cpu_has_mips_4_5_r
)
1923 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1925 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1928 if (!cpu_has_mips_4_5_r
)
1931 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1933 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1936 handler
.u
= ieee754dp_abs
;
1940 handler
.u
= ieee754dp_neg
;
1945 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1948 /* binary op on handler */
1950 DPFROMREG(fs
, MIPSInst_FS(ir
));
1951 DPFROMREG(ft
, MIPSInst_FT(ir
));
1953 rv
.d
= (*handler
.b
) (fs
, ft
);
1956 DPFROMREG(fs
, MIPSInst_FS(ir
));
1957 rv
.d
= (*handler
.u
) (fs
);
1964 DPFROMREG(fs
, MIPSInst_FS(ir
));
1965 rv
.s
= ieee754sp_fdp(fs
);
1970 return SIGILL
; /* not defined */
1973 DPFROMREG(fs
, MIPSInst_FS(ir
));
1974 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1982 if (!cpu_has_mips_2_3_4_5_r
)
1985 oldrm
= ieee754_csr
.rm
;
1986 DPFROMREG(fs
, MIPSInst_FS(ir
));
1987 ieee754_csr
.rm
= MIPSInst_FUNC(ir
);
1988 rv
.w
= ieee754dp_tint(fs
);
1989 ieee754_csr
.rm
= oldrm
;
1994 if (!cpu_has_mips_3_4_5_64_r2_r6
)
1997 DPFROMREG(fs
, MIPSInst_FS(ir
));
1998 rv
.l
= ieee754dp_tlong(fs
);
2006 if (!cpu_has_mips_3_4_5_64_r2_r6
)
2009 oldrm
= ieee754_csr
.rm
;
2010 DPFROMREG(fs
, MIPSInst_FS(ir
));
2011 ieee754_csr
.rm
= MIPSInst_FUNC(ir
);
2012 rv
.l
= ieee754dp_tlong(fs
);
2013 ieee754_csr
.rm
= oldrm
;
2018 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
2019 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
2020 union ieee754dp fs
, ft
;
2022 DPFROMREG(fs
, MIPSInst_FS(ir
));
2023 DPFROMREG(ft
, MIPSInst_FT(ir
));
2024 rv
.w
= ieee754dp_cmp(fs
, ft
,
2025 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
2030 (IEEE754_INVALID_OPERATION
))
2031 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
2047 switch (MIPSInst_FUNC(ir
)) {
2049 /* convert word to single precision real */
2050 SPFROMREG(fs
, MIPSInst_FS(ir
));
2051 rv
.s
= ieee754sp_fint(fs
.bits
);
2055 /* convert word to double precision real */
2056 SPFROMREG(fs
, MIPSInst_FS(ir
));
2057 rv
.d
= ieee754dp_fint(fs
.bits
);
2068 if (!cpu_has_mips_3_4_5_64_r2_r6
)
2071 DIFROMREG(bits
, MIPSInst_FS(ir
));
2073 switch (MIPSInst_FUNC(ir
)) {
2075 /* convert long to single precision real */
2076 rv
.s
= ieee754sp_flong(bits
);
2080 /* convert long to double precision real */
2081 rv
.d
= ieee754dp_flong(bits
);
2094 * Update the fpu CSR register for this operation.
2095 * If an exception is required, generate a tidy SIGFPE exception,
2096 * without updating the result register.
2097 * Note: cause exception bits do not accumulate, they are rewritten
2098 * for each op; only the flag/sticky bits accumulate.
2100 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
2101 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
2102 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2107 * Now we can safely write the result back to the register file.
2112 if (cpu_has_mips_4_5_r
)
2113 cbit
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
2115 cbit
= FPU_CSR_COND
;
2119 ctx
->fcr31
&= ~cbit
;
2123 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
2126 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
2129 SITOREG(rv
.w
, MIPSInst_FD(ir
));
2132 if (!cpu_has_mips_3_4_5_64_r2_r6
)
2135 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2144 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2145 int has_fpu
, void *__user
*fault_addr
)
2147 unsigned long oldepc
, prevepc
;
2148 struct mm_decoded_insn dec_insn
;
2153 oldepc
= xcp
->cp0_epc
;
2155 prevepc
= xcp
->cp0_epc
;
2157 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2159 * Get next 2 microMIPS instructions and convert them
2160 * into 32-bit instructions.
2162 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2163 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2164 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2165 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2166 MIPS_FPU_EMU_INC_STATS(errors
);
2171 /* Get first instruction. */
2172 if (mm_insn_16bit(*instr_ptr
)) {
2173 /* Duplicate the half-word. */
2174 dec_insn
.insn
= (*instr_ptr
<< 16) |
2176 /* 16-bit instruction. */
2177 dec_insn
.pc_inc
= 2;
2180 dec_insn
.insn
= (*instr_ptr
<< 16) |
2182 /* 32-bit instruction. */
2183 dec_insn
.pc_inc
= 4;
2186 /* Get second instruction. */
2187 if (mm_insn_16bit(*instr_ptr
)) {
2188 /* Duplicate the half-word. */
2189 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2191 /* 16-bit instruction. */
2192 dec_insn
.next_pc_inc
= 2;
2194 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2196 /* 32-bit instruction. */
2197 dec_insn
.next_pc_inc
= 4;
2199 dec_insn
.micro_mips_mode
= 1;
2201 if ((get_user(dec_insn
.insn
,
2202 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2203 (get_user(dec_insn
.next_insn
,
2204 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2205 MIPS_FPU_EMU_INC_STATS(errors
);
2208 dec_insn
.pc_inc
= 4;
2209 dec_insn
.next_pc_inc
= 4;
2210 dec_insn
.micro_mips_mode
= 0;
2213 if ((dec_insn
.insn
== 0) ||
2214 ((dec_insn
.pc_inc
== 2) &&
2215 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2216 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2219 * The 'ieee754_csr' is an alias of ctx->fcr31.
2220 * No need to copy ctx->fcr31 to ieee754_csr.
2222 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2231 } while (xcp
->cp0_epc
> prevepc
);
2233 /* SIGILL indicates a non-fpu instruction */
2234 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2235 /* but if EPC has advanced, then ignore it */