2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/percpu-defs.h>
39 #include <linux/perf_event.h>
41 #include <asm/branch.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/uaccess.h>
47 #include <asm/processor.h>
48 #include <asm/fpu_emulator.h>
53 /* Strap kernel emulator for full MIPS IV emulation */
60 /* Function which emulates a floating point instruction. */
62 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
65 #if __mips >= 4 && __mips != 32
66 static int fpux_emu(struct pt_regs
*,
67 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
70 /* Control registers */
72 #define FPCREG_RID 0 /* $0 = revision id */
73 #define FPCREG_CSR 31 /* $31 = csr */
75 /* Determine rounding mode from the RM bits of the FCSR */
76 #define modeindex(v) ((v) & FPU_CSR_RM)
78 /* microMIPS bitfields */
79 #define MM_POOL32A_MINOR_MASK 0x3f
80 #define MM_POOL32A_MINOR_SHIFT 0x6
81 #define MM_MIPS32_COND_FC 0x30
83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
84 static const unsigned char ieee_rm
[4] = {
85 [FPU_CSR_RN
] = IEEE754_RN
,
86 [FPU_CSR_RZ
] = IEEE754_RZ
,
87 [FPU_CSR_RU
] = IEEE754_RU
,
88 [FPU_CSR_RD
] = IEEE754_RD
,
90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
91 static const unsigned char mips_rm
[4] = {
92 [IEEE754_RN
] = FPU_CSR_RN
,
93 [IEEE754_RZ
] = FPU_CSR_RZ
,
94 [IEEE754_RD
] = FPU_CSR_RD
,
95 [IEEE754_RU
] = FPU_CSR_RU
,
99 /* convert condition code register number to csr bit */
100 static const unsigned int fpucondbit
[8] = {
112 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
113 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
115 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
116 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
117 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
118 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
119 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
122 * This functions translates a 32-bit microMIPS instruction
123 * into a 32-bit MIPS32 instruction. Returns 0 on success
124 * and SIGILL otherwise.
126 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
128 union mips_instruction insn
= *insn_ptr
;
129 union mips_instruction mips32_insn
= insn
;
132 switch (insn
.mm_i_format
.opcode
) {
134 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
135 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
136 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
139 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
140 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
141 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
144 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
145 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
146 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
149 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
150 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
151 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
154 /* NOTE: offset is << by 1 if in microMIPS mode. */
155 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
156 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
157 mips32_insn
.fb_format
.opcode
= cop1_op
;
158 mips32_insn
.fb_format
.bc
= bc_op
;
159 mips32_insn
.fb_format
.flag
=
160 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
165 switch (insn
.mm_fp0_format
.func
) {
174 op
= insn
.mm_fp0_format
.func
;
175 if (op
== mm_32f_01_op
)
177 else if (op
== mm_32f_11_op
)
179 else if (op
== mm_32f_02_op
)
181 else if (op
== mm_32f_12_op
)
183 else if (op
== mm_32f_41_op
)
185 else if (op
== mm_32f_51_op
)
187 else if (op
== mm_32f_42_op
)
191 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
192 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
193 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
194 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
195 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
196 mips32_insn
.fp6_format
.func
= func
;
199 func
= -1; /* Invalid */
200 op
= insn
.mm_fp5_format
.op
& 0x7;
201 if (op
== mm_ldxc1_op
)
203 else if (op
== mm_sdxc1_op
)
205 else if (op
== mm_lwxc1_op
)
207 else if (op
== mm_swxc1_op
)
211 mips32_insn
.r_format
.opcode
= cop1x_op
;
212 mips32_insn
.r_format
.rs
=
213 insn
.mm_fp5_format
.base
;
214 mips32_insn
.r_format
.rt
=
215 insn
.mm_fp5_format
.index
;
216 mips32_insn
.r_format
.rd
= 0;
217 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
218 mips32_insn
.r_format
.func
= func
;
223 op
= -1; /* Invalid */
224 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
226 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
229 mips32_insn
.fp0_format
.opcode
= cop1_op
;
230 mips32_insn
.fp0_format
.fmt
=
231 sdps_format
[insn
.mm_fp2_format
.fmt
];
232 mips32_insn
.fp0_format
.ft
=
233 (insn
.mm_fp2_format
.cc
<<2) + op
;
234 mips32_insn
.fp0_format
.fs
=
235 insn
.mm_fp2_format
.fs
;
236 mips32_insn
.fp0_format
.fd
=
237 insn
.mm_fp2_format
.fd
;
238 mips32_insn
.fp0_format
.func
= fmovc_op
;
243 func
= -1; /* Invalid */
244 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
246 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
248 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
250 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
253 mips32_insn
.fp0_format
.opcode
= cop1_op
;
254 mips32_insn
.fp0_format
.fmt
=
255 sdps_format
[insn
.mm_fp0_format
.fmt
];
256 mips32_insn
.fp0_format
.ft
=
257 insn
.mm_fp0_format
.ft
;
258 mips32_insn
.fp0_format
.fs
=
259 insn
.mm_fp0_format
.fs
;
260 mips32_insn
.fp0_format
.fd
=
261 insn
.mm_fp0_format
.fd
;
262 mips32_insn
.fp0_format
.func
= func
;
267 func
= -1; /* Invalid */
268 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
270 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
273 mips32_insn
.fp0_format
.opcode
= cop1_op
;
274 mips32_insn
.fp0_format
.fmt
=
275 sdps_format
[insn
.mm_fp0_format
.fmt
];
276 mips32_insn
.fp0_format
.ft
=
277 insn
.mm_fp0_format
.ft
;
278 mips32_insn
.fp0_format
.fs
=
279 insn
.mm_fp0_format
.fs
;
280 mips32_insn
.fp0_format
.fd
=
281 insn
.mm_fp0_format
.fd
;
282 mips32_insn
.fp0_format
.func
= func
;
286 case mm_32f_73_op
: /* POOL32FXF */
287 switch (insn
.mm_fp1_format
.op
) {
292 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
297 mips32_insn
.r_format
.opcode
= spec_op
;
298 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
299 mips32_insn
.r_format
.rt
=
300 (insn
.mm_fp4_format
.cc
<< 2) + op
;
301 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
302 mips32_insn
.r_format
.re
= 0;
303 mips32_insn
.r_format
.func
= movc_op
;
309 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
312 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
315 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
317 mips32_insn
.fp0_format
.opcode
= cop1_op
;
318 mips32_insn
.fp0_format
.fmt
= fmt
;
319 mips32_insn
.fp0_format
.ft
= 0;
320 mips32_insn
.fp0_format
.fs
=
321 insn
.mm_fp3_format
.fs
;
322 mips32_insn
.fp0_format
.fd
=
323 insn
.mm_fp3_format
.rt
;
324 mips32_insn
.fp0_format
.func
= func
;
332 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
335 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
340 mips32_insn
.fp0_format
.opcode
= cop1_op
;
341 mips32_insn
.fp0_format
.fmt
=
342 sdps_format
[insn
.mm_fp3_format
.fmt
];
343 mips32_insn
.fp0_format
.ft
= 0;
344 mips32_insn
.fp0_format
.fs
=
345 insn
.mm_fp3_format
.fs
;
346 mips32_insn
.fp0_format
.fd
=
347 insn
.mm_fp3_format
.rt
;
348 mips32_insn
.fp0_format
.func
= func
;
360 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
362 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
364 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
366 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
368 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
370 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
372 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
374 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
376 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
380 mips32_insn
.fp0_format
.opcode
= cop1_op
;
381 mips32_insn
.fp0_format
.fmt
=
382 sd_format
[insn
.mm_fp1_format
.fmt
];
383 mips32_insn
.fp0_format
.ft
= 0;
384 mips32_insn
.fp0_format
.fs
=
385 insn
.mm_fp1_format
.fs
;
386 mips32_insn
.fp0_format
.fd
=
387 insn
.mm_fp1_format
.rt
;
388 mips32_insn
.fp0_format
.func
= func
;
393 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
395 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
399 mips32_insn
.fp0_format
.opcode
= cop1_op
;
400 mips32_insn
.fp0_format
.fmt
=
401 sdps_format
[insn
.mm_fp1_format
.fmt
];
402 mips32_insn
.fp0_format
.ft
= 0;
403 mips32_insn
.fp0_format
.fs
=
404 insn
.mm_fp1_format
.fs
;
405 mips32_insn
.fp0_format
.fd
=
406 insn
.mm_fp1_format
.rt
;
407 mips32_insn
.fp0_format
.func
= func
;
415 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
417 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
419 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
421 else if (insn
.mm_fp1_format
.op
== mm_ctc1_op
)
423 else if (insn
.mm_fp1_format
.op
== mm_mfhc1_op
)
427 mips32_insn
.fp1_format
.opcode
= cop1_op
;
428 mips32_insn
.fp1_format
.op
= op
;
429 mips32_insn
.fp1_format
.rt
=
430 insn
.mm_fp1_format
.rt
;
431 mips32_insn
.fp1_format
.fs
=
432 insn
.mm_fp1_format
.fs
;
433 mips32_insn
.fp1_format
.fd
= 0;
434 mips32_insn
.fp1_format
.func
= 0;
440 case mm_32f_74_op
: /* c.cond.fmt */
441 mips32_insn
.fp0_format
.opcode
= cop1_op
;
442 mips32_insn
.fp0_format
.fmt
=
443 sdps_format
[insn
.mm_fp4_format
.fmt
];
444 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
445 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
446 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
447 mips32_insn
.fp0_format
.func
=
448 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
458 *insn_ptr
= mips32_insn
;
462 int mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
463 unsigned long *contpc
)
465 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
473 switch (insn
.mm_i_format
.opcode
) {
475 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
477 switch (insn
.mm_i_format
.simmediate
>>
478 MM_POOL32A_MINOR_SHIFT
) {
483 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
484 regs
->regs
[insn
.mm_i_format
.rt
] =
487 dec_insn
.next_pc_inc
;
488 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
494 switch (insn
.mm_i_format
.rt
) {
497 regs
->regs
[31] = regs
->cp0_epc
+
499 dec_insn
.next_pc_inc
;
502 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
503 *contpc
= regs
->cp0_epc
+
505 (insn
.mm_i_format
.simmediate
<< 1);
507 *contpc
= regs
->cp0_epc
+
509 dec_insn
.next_pc_inc
;
513 regs
->regs
[31] = regs
->cp0_epc
+
515 dec_insn
.next_pc_inc
;
518 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
519 *contpc
= regs
->cp0_epc
+
521 (insn
.mm_i_format
.simmediate
<< 1);
523 *contpc
= regs
->cp0_epc
+
525 dec_insn
.next_pc_inc
;
528 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
529 *contpc
= regs
->cp0_epc
+
531 (insn
.mm_i_format
.simmediate
<< 1);
533 *contpc
= regs
->cp0_epc
+
535 dec_insn
.next_pc_inc
;
538 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
539 *contpc
= regs
->cp0_epc
+
541 (insn
.mm_i_format
.simmediate
<< 1);
543 *contpc
= regs
->cp0_epc
+
545 dec_insn
.next_pc_inc
;
555 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
557 fcr31
= current
->thread
.fpu
.fcr31
;
563 bit
= (insn
.mm_i_format
.rs
>> 2);
566 if (fcr31
& (1 << bit
))
567 *contpc
= regs
->cp0_epc
+
569 (insn
.mm_i_format
.simmediate
<< 1);
571 *contpc
= regs
->cp0_epc
+
572 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
577 switch (insn
.mm_i_format
.rt
) {
580 regs
->regs
[31] = regs
->cp0_epc
+
581 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
584 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
589 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
590 *contpc
= regs
->cp0_epc
+
592 (insn
.mm_b1_format
.simmediate
<< 1);
594 *contpc
= regs
->cp0_epc
+
595 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
598 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
599 *contpc
= regs
->cp0_epc
+
601 (insn
.mm_b1_format
.simmediate
<< 1);
603 *contpc
= regs
->cp0_epc
+
604 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
607 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
608 (insn
.mm_b0_format
.simmediate
<< 1);
611 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
612 regs
->regs
[insn
.mm_i_format
.rt
])
613 *contpc
= regs
->cp0_epc
+
615 (insn
.mm_i_format
.simmediate
<< 1);
617 *contpc
= regs
->cp0_epc
+
619 dec_insn
.next_pc_inc
;
622 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
623 regs
->regs
[insn
.mm_i_format
.rt
])
624 *contpc
= regs
->cp0_epc
+
626 (insn
.mm_i_format
.simmediate
<< 1);
628 *contpc
= regs
->cp0_epc
+
629 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
632 regs
->regs
[31] = regs
->cp0_epc
+
633 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
634 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
637 *contpc
|= (insn
.j_format
.target
<< 2);
641 regs
->regs
[31] = regs
->cp0_epc
+
642 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
645 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
648 *contpc
|= (insn
.j_format
.target
<< 1);
649 set_isa16_mode(*contpc
);
656 * Redundant with logic already in kernel/branch.c,
657 * embedded in compute_return_epc. At some point,
658 * a single subroutine should be used across both
661 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
662 unsigned long *contpc
)
664 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
666 unsigned int bit
= 0;
668 switch (insn
.i_format
.opcode
) {
670 switch (insn
.r_format
.func
) {
672 regs
->regs
[insn
.r_format
.rd
] =
673 regs
->cp0_epc
+ dec_insn
.pc_inc
+
674 dec_insn
.next_pc_inc
;
677 *contpc
= regs
->regs
[insn
.r_format
.rs
];
682 switch (insn
.i_format
.rt
) {
685 regs
->regs
[31] = regs
->cp0_epc
+
687 dec_insn
.next_pc_inc
;
691 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
692 *contpc
= regs
->cp0_epc
+
694 (insn
.i_format
.simmediate
<< 2);
696 *contpc
= regs
->cp0_epc
+
698 dec_insn
.next_pc_inc
;
702 regs
->regs
[31] = regs
->cp0_epc
+
704 dec_insn
.next_pc_inc
;
708 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
709 *contpc
= regs
->cp0_epc
+
711 (insn
.i_format
.simmediate
<< 2);
713 *contpc
= regs
->cp0_epc
+
715 dec_insn
.next_pc_inc
;
722 regs
->regs
[31] = regs
->cp0_epc
+
724 dec_insn
.next_pc_inc
;
727 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
730 *contpc
|= (insn
.j_format
.target
<< 2);
731 /* Set microMIPS mode bit: XOR for jalx. */
736 if (regs
->regs
[insn
.i_format
.rs
] ==
737 regs
->regs
[insn
.i_format
.rt
])
738 *contpc
= regs
->cp0_epc
+
740 (insn
.i_format
.simmediate
<< 2);
742 *contpc
= regs
->cp0_epc
+
744 dec_insn
.next_pc_inc
;
748 if (regs
->regs
[insn
.i_format
.rs
] !=
749 regs
->regs
[insn
.i_format
.rt
])
750 *contpc
= regs
->cp0_epc
+
752 (insn
.i_format
.simmediate
<< 2);
754 *contpc
= regs
->cp0_epc
+
756 dec_insn
.next_pc_inc
;
760 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
761 *contpc
= regs
->cp0_epc
+
763 (insn
.i_format
.simmediate
<< 2);
765 *contpc
= regs
->cp0_epc
+
767 dec_insn
.next_pc_inc
;
771 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
772 *contpc
= regs
->cp0_epc
+
774 (insn
.i_format
.simmediate
<< 2);
776 *contpc
= regs
->cp0_epc
+
778 dec_insn
.next_pc_inc
;
780 #ifdef CONFIG_CPU_CAVIUM_OCTEON
781 case lwc2_op
: /* This is bbit0 on Octeon */
782 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
783 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
785 *contpc
= regs
->cp0_epc
+ 8;
787 case ldc2_op
: /* This is bbit032 on Octeon */
788 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
789 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
791 *contpc
= regs
->cp0_epc
+ 8;
793 case swc2_op
: /* This is bbit1 on Octeon */
794 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
795 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
797 *contpc
= regs
->cp0_epc
+ 8;
799 case sdc2_op
: /* This is bbit132 on Octeon */
800 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
801 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
803 *contpc
= regs
->cp0_epc
+ 8;
810 if (insn
.i_format
.rs
== bc_op
) {
813 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
815 fcr31
= current
->thread
.fpu
.fcr31
;
818 bit
= (insn
.i_format
.rt
>> 2);
821 switch (insn
.i_format
.rt
& 3) {
824 if (~fcr31
& (1 << bit
))
825 *contpc
= regs
->cp0_epc
+
827 (insn
.i_format
.simmediate
<< 2);
829 *contpc
= regs
->cp0_epc
+
831 dec_insn
.next_pc_inc
;
835 if (fcr31
& (1 << bit
))
836 *contpc
= regs
->cp0_epc
+
838 (insn
.i_format
.simmediate
<< 2);
840 *contpc
= regs
->cp0_epc
+
842 dec_insn
.next_pc_inc
;
852 * In the Linux kernel, we support selection of FPR format on the
853 * basis of the Status.FR bit. If an FPU is not present, the FR bit
854 * is hardwired to zero, which would imply a 32-bit FPU even for
855 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
856 * FPU emu is slow and bulky and optimizing this function offers fairly
857 * sizeable benefits so we try to be clever and make this function return
858 * a constant whenever possible, that is on 64-bit kernels without O32
859 * compatibility enabled and on 32-bit without 64-bit FPU support.
861 static inline int cop1_64bit(struct pt_regs
*xcp
)
863 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
865 #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
868 return !test_thread_flag(TIF_32BIT_FPREGS
);
872 #define SIFROMREG(si, x) do { \
873 if (cop1_64bit(xcp)) \
874 (si) = get_fpr32(&ctx->fpr[x], 0); \
876 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
879 #define SITOREG(si, x) do { \
880 if (cop1_64bit(xcp)) { \
882 set_fpr32(&ctx->fpr[x], 0, si); \
883 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
884 set_fpr32(&ctx->fpr[x], i, 0); \
886 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
890 #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
892 #define SITOHREG(si, x) do { \
894 set_fpr32(&ctx->fpr[x], 1, si); \
895 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
896 set_fpr32(&ctx->fpr[x], i, 0); \
899 #define DIFROMREG(di, x) \
900 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
902 #define DITOREG(di, x) do { \
904 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
905 set_fpr64(&ctx->fpr[fpr], 0, di); \
906 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
907 set_fpr64(&ctx->fpr[fpr], i, 0); \
910 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
911 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
912 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
913 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
916 * Emulate the single floating point instruction pointed at by EPC.
917 * Two instructions if the instruction is in a branch delay slot.
920 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
921 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
924 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
928 /* XXX NEC Vr54xx bug workaround */
929 if (delay_slot(xcp
)) {
930 if (dec_insn
.micro_mips_mode
) {
931 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
932 clear_delay_slot(xcp
);
934 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
935 clear_delay_slot(xcp
);
939 if (delay_slot(xcp
)) {
941 * The instruction to be emulated is in a branch delay slot
942 * which means that we have to emulate the branch instruction
943 * BEFORE we do the cop1 instruction.
945 * This branch could be a COP1 branch, but in that case we
946 * would have had a trap for that instruction, and would not
947 * come through this route.
949 * Linux MIPS branch emulator operates on context, updating the
952 ir
= dec_insn
.next_insn
; /* process delay slot instr */
953 pc_inc
= dec_insn
.next_pc_inc
;
955 ir
= dec_insn
.insn
; /* process current instr */
956 pc_inc
= dec_insn
.pc_inc
;
960 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
961 * instructions, we want to convert microMIPS FPU instructions
962 * into MIPS32 instructions so that we could reuse all of the
963 * FPU emulation code.
965 * NOTE: We cannot do this for branch instructions since they
966 * are not a subset. Example: Cannot emulate a 16-bit
967 * aligned target address with a MIPS32 instruction.
969 if (dec_insn
.micro_mips_mode
) {
971 * If next instruction is a 16-bit instruction, then it
972 * it cannot be a FPU instruction. This could happen
973 * since we can be called for non-FPU instructions.
976 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
982 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
983 MIPS_FPU_EMU_INC_STATS(emulated
);
984 switch (MIPSInst_OPCODE(ir
)) {
986 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
990 MIPS_FPU_EMU_INC_STATS(loads
);
992 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
993 MIPS_FPU_EMU_INC_STATS(errors
);
997 if (__get_user(val
, va
)) {
998 MIPS_FPU_EMU_INC_STATS(errors
);
1002 DITOREG(val
, MIPSInst_RT(ir
));
1007 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1011 MIPS_FPU_EMU_INC_STATS(stores
);
1012 DIFROMREG(val
, MIPSInst_RT(ir
));
1013 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1014 MIPS_FPU_EMU_INC_STATS(errors
);
1018 if (__put_user(val
, va
)) {
1019 MIPS_FPU_EMU_INC_STATS(errors
);
1027 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1031 MIPS_FPU_EMU_INC_STATS(loads
);
1032 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1033 MIPS_FPU_EMU_INC_STATS(errors
);
1037 if (__get_user(val
, va
)) {
1038 MIPS_FPU_EMU_INC_STATS(errors
);
1042 SITOREG(val
, MIPSInst_RT(ir
));
1047 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1051 MIPS_FPU_EMU_INC_STATS(stores
);
1052 SIFROMREG(val
, MIPSInst_RT(ir
));
1053 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1054 MIPS_FPU_EMU_INC_STATS(errors
);
1058 if (__put_user(val
, va
)) {
1059 MIPS_FPU_EMU_INC_STATS(errors
);
1067 switch (MIPSInst_RS(ir
)) {
1069 #if defined(__mips64)
1071 /* copregister fs -> gpr[rt] */
1072 if (MIPSInst_RT(ir
) != 0) {
1073 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1079 /* copregister fs <- rt */
1080 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1085 if (!cpu_has_mips_r2
)
1088 /* copregister rd -> gpr[rt] */
1089 if (MIPSInst_RT(ir
) != 0) {
1090 SIFROMHREG(xcp
->regs
[MIPSInst_RT(ir
)],
1096 if (!cpu_has_mips_r2
)
1099 /* copregister rd <- gpr[rt] */
1100 SITOHREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1104 /* copregister rd -> gpr[rt] */
1105 if (MIPSInst_RT(ir
) != 0) {
1106 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1112 /* copregister rd <- rt */
1113 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1117 /* cop control register rd -> gpr[rt] */
1120 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1122 value
= (value
& ~FPU_CSR_RM
) |
1123 mips_rm
[modeindex(value
)];
1125 printk("%p gpr[%d]<-csr=%08x\n",
1126 (void *) (xcp
->cp0_epc
),
1127 MIPSInst_RT(ir
), value
);
1130 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1134 if (MIPSInst_RT(ir
))
1135 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1140 /* copregister rd <- rt */
1143 if (MIPSInst_RT(ir
) == 0)
1146 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1148 /* we only have one writable control reg
1150 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1152 printk("%p gpr[%d]->csr=%08x\n",
1153 (void *) (xcp
->cp0_epc
),
1154 MIPSInst_RT(ir
), value
);
1158 * Don't write reserved bits,
1159 * and convert to ieee library modes
1161 ctx
->fcr31
= (value
&
1162 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1163 ieee_rm
[modeindex(value
)];
1165 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1174 if (delay_slot(xcp
))
1178 cond
= ctx
->fcr31
& fpucondbit
[MIPSInst_RT(ir
) >> 2];
1180 cond
= ctx
->fcr31
& FPU_CSR_COND
;
1182 switch (MIPSInst_RT(ir
) & 3) {
1193 /* thats an illegal instruction */
1197 set_delay_slot(xcp
);
1199 /* branch taken: emulate dslot
1202 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1204 contpc
= MIPSInst_SIMM(ir
);
1205 ir
= dec_insn
.next_insn
;
1206 if (dec_insn
.micro_mips_mode
) {
1207 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1209 /* If 16-bit instruction, not FPU. */
1210 if ((dec_insn
.next_pc_inc
== 2) ||
1211 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1214 * Since this instruction will
1215 * be put on the stack with
1216 * 32-bit words, get around
1217 * this problem by putting a
1218 * NOP16 as the second one.
1220 if (dec_insn
.next_pc_inc
== 2)
1221 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1224 * Single step the non-CP1
1225 * instruction in the dslot.
1227 return mips_dsemul(xcp
, ir
, contpc
);
1230 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1232 switch (MIPSInst_OPCODE(ir
)) {
1235 #if (__mips >= 2 || defined(__mips64))
1240 #if __mips >= 4 && __mips != 32
1243 /* its one of ours */
1247 if (MIPSInst_FUNC(ir
) == movc_op
)
1254 * Single step the non-cp1
1255 * instruction in the dslot
1257 return mips_dsemul(xcp
, ir
, contpc
);
1260 /* branch not taken */
1263 * branch likely nullifies
1264 * dslot if not taken
1266 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1267 contpc
+= dec_insn
.pc_inc
;
1269 * else continue & execute
1270 * dslot as normal insn
1278 if (!(MIPSInst_RS(ir
) & 0x10))
1283 /* a real fpu computation instruction */
1284 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1290 #if __mips >= 4 && __mips != 32
1292 int sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1301 if (MIPSInst_FUNC(ir
) != movc_op
)
1303 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1304 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1305 xcp
->regs
[MIPSInst_RD(ir
)] =
1306 xcp
->regs
[MIPSInst_RS(ir
)];
1316 xcp
->cp0_epc
= contpc
;
1317 clear_delay_slot(xcp
);
1323 * Conversion table from MIPS compare ops 48-63
1324 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1326 static const unsigned char cmptab
[8] = {
1327 0, /* cmp_0 (sig) cmp_sf */
1328 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1329 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1330 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1331 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1332 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1333 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1334 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1338 #if __mips >= 4 && __mips != 32
1341 * Additional MIPS4 instructions
1344 #define DEF3OP(name, p, f1, f2, f3) \
1345 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \
1346 union ieee754##p t) \
1348 struct _ieee754_csr ieee754_csr_save; \
1350 ieee754_csr_save = ieee754_csr; \
1352 ieee754_csr_save.cx |= ieee754_csr.cx; \
1353 ieee754_csr_save.sx |= ieee754_csr.sx; \
1355 ieee754_csr.cx |= ieee754_csr_save.cx; \
1356 ieee754_csr.sx |= ieee754_csr_save.sx; \
1360 static union ieee754dp
fpemu_dp_recip(union ieee754dp d
)
1362 return ieee754dp_div(ieee754dp_one(0), d
);
1365 static union ieee754dp
fpemu_dp_rsqrt(union ieee754dp d
)
1367 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1370 static union ieee754sp
fpemu_sp_recip(union ieee754sp s
)
1372 return ieee754sp_div(ieee754sp_one(0), s
);
1375 static union ieee754sp
fpemu_sp_rsqrt(union ieee754sp s
)
1377 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1380 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1381 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1382 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1383 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1384 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1385 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1386 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1387 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1389 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1390 mips_instruction ir
, void *__user
*fault_addr
)
1392 unsigned rcsr
= 0; /* resulting csr */
1394 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1396 switch (MIPSInst_FMA_FFMT(ir
)) {
1397 case s_fmt
:{ /* 0 */
1399 union ieee754sp(*handler
) (union ieee754sp
, union ieee754sp
, union ieee754sp
);
1400 union ieee754sp fd
, fr
, fs
, ft
;
1404 switch (MIPSInst_FUNC(ir
)) {
1406 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1407 xcp
->regs
[MIPSInst_FT(ir
)]);
1409 MIPS_FPU_EMU_INC_STATS(loads
);
1410 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1411 MIPS_FPU_EMU_INC_STATS(errors
);
1415 if (__get_user(val
, va
)) {
1416 MIPS_FPU_EMU_INC_STATS(errors
);
1420 SITOREG(val
, MIPSInst_FD(ir
));
1424 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1425 xcp
->regs
[MIPSInst_FT(ir
)]);
1427 MIPS_FPU_EMU_INC_STATS(stores
);
1429 SIFROMREG(val
, MIPSInst_FS(ir
));
1430 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1431 MIPS_FPU_EMU_INC_STATS(errors
);
1435 if (put_user(val
, va
)) {
1436 MIPS_FPU_EMU_INC_STATS(errors
);
1443 handler
= fpemu_sp_madd
;
1446 handler
= fpemu_sp_msub
;
1449 handler
= fpemu_sp_nmadd
;
1452 handler
= fpemu_sp_nmsub
;
1456 SPFROMREG(fr
, MIPSInst_FR(ir
));
1457 SPFROMREG(fs
, MIPSInst_FS(ir
));
1458 SPFROMREG(ft
, MIPSInst_FT(ir
));
1459 fd
= (*handler
) (fr
, fs
, ft
);
1460 SPTOREG(fd
, MIPSInst_FD(ir
));
1463 if (ieee754_cxtest(IEEE754_INEXACT
))
1464 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1465 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1466 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1467 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1468 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1469 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1470 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1472 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1473 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1474 /*printk ("SIGFPE: fpu csr = %08x\n",
1487 case d_fmt
:{ /* 1 */
1488 union ieee754dp(*handler
) (union ieee754dp
, union ieee754dp
, union ieee754dp
);
1489 union ieee754dp fd
, fr
, fs
, ft
;
1493 switch (MIPSInst_FUNC(ir
)) {
1495 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1496 xcp
->regs
[MIPSInst_FT(ir
)]);
1498 MIPS_FPU_EMU_INC_STATS(loads
);
1499 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1500 MIPS_FPU_EMU_INC_STATS(errors
);
1504 if (__get_user(val
, va
)) {
1505 MIPS_FPU_EMU_INC_STATS(errors
);
1509 DITOREG(val
, MIPSInst_FD(ir
));
1513 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1514 xcp
->regs
[MIPSInst_FT(ir
)]);
1516 MIPS_FPU_EMU_INC_STATS(stores
);
1517 DIFROMREG(val
, MIPSInst_FS(ir
));
1518 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1519 MIPS_FPU_EMU_INC_STATS(errors
);
1523 if (__put_user(val
, va
)) {
1524 MIPS_FPU_EMU_INC_STATS(errors
);
1531 handler
= fpemu_dp_madd
;
1534 handler
= fpemu_dp_msub
;
1537 handler
= fpemu_dp_nmadd
;
1540 handler
= fpemu_dp_nmsub
;
1544 DPFROMREG(fr
, MIPSInst_FR(ir
));
1545 DPFROMREG(fs
, MIPSInst_FS(ir
));
1546 DPFROMREG(ft
, MIPSInst_FT(ir
));
1547 fd
= (*handler
) (fr
, fs
, ft
);
1548 DPTOREG(fd
, MIPSInst_FD(ir
));
1558 if (MIPSInst_FUNC(ir
) != pfetch_op
)
1561 /* ignore prefx operation */
1575 * Emulate a single COP1 arithmetic instruction.
1577 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1578 mips_instruction ir
)
1580 int rfmt
; /* resulting format */
1581 unsigned rcsr
= 0; /* resulting csr */
1590 } rv
; /* resulting value */
1592 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1593 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1594 case s_fmt
:{ /* 0 */
1596 union ieee754sp(*b
) (union ieee754sp
, union ieee754sp
);
1597 union ieee754sp(*u
) (union ieee754sp
);
1600 switch (MIPSInst_FUNC(ir
)) {
1603 handler
.b
= ieee754sp_add
;
1606 handler
.b
= ieee754sp_sub
;
1609 handler
.b
= ieee754sp_mul
;
1612 handler
.b
= ieee754sp_div
;
1616 #if __mips >= 2 || defined(__mips64)
1618 handler
.u
= ieee754sp_sqrt
;
1621 #if __mips >= 4 && __mips != 32
1623 handler
.u
= fpemu_sp_rsqrt
;
1626 handler
.u
= fpemu_sp_recip
;
1631 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1632 if (((ctx
->fcr31
& cond
) != 0) !=
1633 ((MIPSInst_FT(ir
) & 1) != 0))
1635 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1638 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1640 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1643 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1645 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1649 handler
.u
= ieee754sp_abs
;
1652 handler
.u
= ieee754sp_neg
;
1656 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1659 /* binary op on handler */
1662 union ieee754sp fs
, ft
;
1664 SPFROMREG(fs
, MIPSInst_FS(ir
));
1665 SPFROMREG(ft
, MIPSInst_FT(ir
));
1667 rv
.s
= (*handler
.b
) (fs
, ft
);
1674 SPFROMREG(fs
, MIPSInst_FS(ir
));
1675 rv
.s
= (*handler
.u
) (fs
);
1679 if (ieee754_cxtest(IEEE754_INEXACT
))
1680 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1681 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1682 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1683 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1684 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1685 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
1686 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1687 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1688 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1691 /* unary conv ops */
1693 return SIGILL
; /* not defined */
1697 SPFROMREG(fs
, MIPSInst_FS(ir
));
1698 rv
.d
= ieee754dp_fsp(fs
);
1705 SPFROMREG(fs
, MIPSInst_FS(ir
));
1706 rv
.w
= ieee754sp_tint(fs
);
1711 #if __mips >= 2 || defined(__mips64)
1716 unsigned int oldrm
= ieee754_csr
.rm
;
1719 SPFROMREG(fs
, MIPSInst_FS(ir
));
1720 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1721 rv
.w
= ieee754sp_tint(fs
);
1722 ieee754_csr
.rm
= oldrm
;
1726 #endif /* __mips >= 2 */
1728 #if defined(__mips64)
1732 SPFROMREG(fs
, MIPSInst_FS(ir
));
1733 rv
.l
= ieee754sp_tlong(fs
);
1742 unsigned int oldrm
= ieee754_csr
.rm
;
1745 SPFROMREG(fs
, MIPSInst_FS(ir
));
1746 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1747 rv
.l
= ieee754sp_tlong(fs
);
1748 ieee754_csr
.rm
= oldrm
;
1752 #endif /* defined(__mips64) */
1755 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1756 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1757 union ieee754sp fs
, ft
;
1759 SPFROMREG(fs
, MIPSInst_FS(ir
));
1760 SPFROMREG(ft
, MIPSInst_FT(ir
));
1761 rv
.w
= ieee754sp_cmp(fs
, ft
,
1762 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1764 if ((cmpop
& 0x8) && ieee754_cxtest
1765 (IEEE754_INVALID_OPERATION
))
1766 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1781 union ieee754dp(*b
) (union ieee754dp
, union ieee754dp
);
1782 union ieee754dp(*u
) (union ieee754dp
);
1785 switch (MIPSInst_FUNC(ir
)) {
1788 handler
.b
= ieee754dp_add
;
1791 handler
.b
= ieee754dp_sub
;
1794 handler
.b
= ieee754dp_mul
;
1797 handler
.b
= ieee754dp_div
;
1801 #if __mips >= 2 || defined(__mips64)
1803 handler
.u
= ieee754dp_sqrt
;
1806 #if __mips >= 4 && __mips != 32
1808 handler
.u
= fpemu_dp_rsqrt
;
1811 handler
.u
= fpemu_dp_recip
;
1816 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1817 if (((ctx
->fcr31
& cond
) != 0) !=
1818 ((MIPSInst_FT(ir
) & 1) != 0))
1820 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1823 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1825 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1828 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1830 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1834 handler
.u
= ieee754dp_abs
;
1838 handler
.u
= ieee754dp_neg
;
1843 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1846 /* binary op on handler */
1848 union ieee754dp fs
, ft
;
1850 DPFROMREG(fs
, MIPSInst_FS(ir
));
1851 DPFROMREG(ft
, MIPSInst_FT(ir
));
1853 rv
.d
= (*handler
.b
) (fs
, ft
);
1859 DPFROMREG(fs
, MIPSInst_FS(ir
));
1860 rv
.d
= (*handler
.u
) (fs
);
1864 /* unary conv ops */
1868 DPFROMREG(fs
, MIPSInst_FS(ir
));
1869 rv
.s
= ieee754sp_fdp(fs
);
1874 return SIGILL
; /* not defined */
1879 DPFROMREG(fs
, MIPSInst_FS(ir
));
1880 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1885 #if __mips >= 2 || defined(__mips64)
1890 unsigned int oldrm
= ieee754_csr
.rm
;
1893 DPFROMREG(fs
, MIPSInst_FS(ir
));
1894 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1895 rv
.w
= ieee754dp_tint(fs
);
1896 ieee754_csr
.rm
= oldrm
;
1902 #if defined(__mips64)
1906 DPFROMREG(fs
, MIPSInst_FS(ir
));
1907 rv
.l
= ieee754dp_tlong(fs
);
1916 unsigned int oldrm
= ieee754_csr
.rm
;
1919 DPFROMREG(fs
, MIPSInst_FS(ir
));
1920 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1921 rv
.l
= ieee754dp_tlong(fs
);
1922 ieee754_csr
.rm
= oldrm
;
1926 #endif /* __mips >= 3 */
1929 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1930 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1931 union ieee754dp fs
, ft
;
1933 DPFROMREG(fs
, MIPSInst_FS(ir
));
1934 DPFROMREG(ft
, MIPSInst_FT(ir
));
1935 rv
.w
= ieee754dp_cmp(fs
, ft
,
1936 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1941 (IEEE754_INVALID_OPERATION
))
1942 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1958 switch (MIPSInst_FUNC(ir
)) {
1960 /* convert word to single precision real */
1961 SPFROMREG(fs
, MIPSInst_FS(ir
));
1962 rv
.s
= ieee754sp_fint(fs
.bits
);
1966 /* convert word to double precision real */
1967 SPFROMREG(fs
, MIPSInst_FS(ir
));
1968 rv
.d
= ieee754dp_fint(fs
.bits
);
1977 #if defined(__mips64)
1980 DIFROMREG(bits
, MIPSInst_FS(ir
));
1982 switch (MIPSInst_FUNC(ir
)) {
1984 /* convert long to single precision real */
1985 rv
.s
= ieee754sp_flong(bits
);
1989 /* convert long to double precision real */
1990 rv
.d
= ieee754dp_flong(bits
);
2005 * Update the fpu CSR register for this operation.
2006 * If an exception is required, generate a tidy SIGFPE exception,
2007 * without updating the result register.
2008 * Note: cause exception bits do not accumulate, they are rewritten
2009 * for each op; only the flag/sticky bits accumulate.
2011 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
2012 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
2013 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2018 * Now we can safely write the result back to the register file.
2023 cond
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
2025 cond
= FPU_CSR_COND
;
2030 ctx
->fcr31
&= ~cond
;
2034 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
2037 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
2040 SITOREG(rv
.w
, MIPSInst_FD(ir
));
2042 #if defined(__mips64)
2044 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2054 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2055 int has_fpu
, void *__user
*fault_addr
)
2057 unsigned long oldepc
, prevepc
;
2058 struct mm_decoded_insn dec_insn
;
2063 oldepc
= xcp
->cp0_epc
;
2065 prevepc
= xcp
->cp0_epc
;
2067 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2069 * Get next 2 microMIPS instructions and convert them
2070 * into 32-bit instructions.
2072 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2073 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2074 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2075 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2076 MIPS_FPU_EMU_INC_STATS(errors
);
2081 /* Get first instruction. */
2082 if (mm_insn_16bit(*instr_ptr
)) {
2083 /* Duplicate the half-word. */
2084 dec_insn
.insn
= (*instr_ptr
<< 16) |
2086 /* 16-bit instruction. */
2087 dec_insn
.pc_inc
= 2;
2090 dec_insn
.insn
= (*instr_ptr
<< 16) |
2092 /* 32-bit instruction. */
2093 dec_insn
.pc_inc
= 4;
2096 /* Get second instruction. */
2097 if (mm_insn_16bit(*instr_ptr
)) {
2098 /* Duplicate the half-word. */
2099 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2101 /* 16-bit instruction. */
2102 dec_insn
.next_pc_inc
= 2;
2104 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2106 /* 32-bit instruction. */
2107 dec_insn
.next_pc_inc
= 4;
2109 dec_insn
.micro_mips_mode
= 1;
2111 if ((get_user(dec_insn
.insn
,
2112 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2113 (get_user(dec_insn
.next_insn
,
2114 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2115 MIPS_FPU_EMU_INC_STATS(errors
);
2118 dec_insn
.pc_inc
= 4;
2119 dec_insn
.next_pc_inc
= 4;
2120 dec_insn
.micro_mips_mode
= 0;
2123 if ((dec_insn
.insn
== 0) ||
2124 ((dec_insn
.pc_inc
== 2) &&
2125 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2126 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2129 * The 'ieee754_csr' is an alias of
2130 * ctx->fcr31. No need to copy ctx->fcr31 to
2131 * ieee754_csr. But ieee754_csr.rm is ieee
2132 * library modes. (not mips rounding mode)
2134 /* convert to ieee library modes */
2135 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
2136 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2137 /* revert to mips rounding mode */
2138 ieee754_csr
.rm
= mips_rm
[ieee754_csr
.rm
];
2147 } while (xcp
->cp0_epc
> prevepc
);
2149 /* SIGILL indicates a non-fpu instruction */
2150 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2151 /* but if epc has advanced, then ignore it */