2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
59 static int fpux_emu(struct pt_regs
*,
60 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit
[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
95 union mips_instruction insn
= *insn_ptr
;
96 union mips_instruction mips32_insn
= insn
;
99 switch (insn
.mm_i_format
.opcode
) {
101 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
102 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
103 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
106 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
107 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
108 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
111 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
112 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
113 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
116 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
117 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
118 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
123 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
124 mips32_insn
.fb_format
.opcode
= cop1_op
;
125 mips32_insn
.fb_format
.bc
= bc_op
;
126 mips32_insn
.fb_format
.flag
=
127 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
132 switch (insn
.mm_fp0_format
.func
) {
141 op
= insn
.mm_fp0_format
.func
;
142 if (op
== mm_32f_01_op
)
144 else if (op
== mm_32f_11_op
)
146 else if (op
== mm_32f_02_op
)
148 else if (op
== mm_32f_12_op
)
150 else if (op
== mm_32f_41_op
)
152 else if (op
== mm_32f_51_op
)
154 else if (op
== mm_32f_42_op
)
158 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
159 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
160 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
161 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
162 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
163 mips32_insn
.fp6_format
.func
= func
;
166 func
= -1; /* Invalid */
167 op
= insn
.mm_fp5_format
.op
& 0x7;
168 if (op
== mm_ldxc1_op
)
170 else if (op
== mm_sdxc1_op
)
172 else if (op
== mm_lwxc1_op
)
174 else if (op
== mm_swxc1_op
)
178 mips32_insn
.r_format
.opcode
= cop1x_op
;
179 mips32_insn
.r_format
.rs
=
180 insn
.mm_fp5_format
.base
;
181 mips32_insn
.r_format
.rt
=
182 insn
.mm_fp5_format
.index
;
183 mips32_insn
.r_format
.rd
= 0;
184 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
185 mips32_insn
.r_format
.func
= func
;
190 op
= -1; /* Invalid */
191 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
193 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
196 mips32_insn
.fp0_format
.opcode
= cop1_op
;
197 mips32_insn
.fp0_format
.fmt
=
198 sdps_format
[insn
.mm_fp2_format
.fmt
];
199 mips32_insn
.fp0_format
.ft
=
200 (insn
.mm_fp2_format
.cc
<<2) + op
;
201 mips32_insn
.fp0_format
.fs
=
202 insn
.mm_fp2_format
.fs
;
203 mips32_insn
.fp0_format
.fd
=
204 insn
.mm_fp2_format
.fd
;
205 mips32_insn
.fp0_format
.func
= fmovc_op
;
210 func
= -1; /* Invalid */
211 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
213 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
215 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
217 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
220 mips32_insn
.fp0_format
.opcode
= cop1_op
;
221 mips32_insn
.fp0_format
.fmt
=
222 sdps_format
[insn
.mm_fp0_format
.fmt
];
223 mips32_insn
.fp0_format
.ft
=
224 insn
.mm_fp0_format
.ft
;
225 mips32_insn
.fp0_format
.fs
=
226 insn
.mm_fp0_format
.fs
;
227 mips32_insn
.fp0_format
.fd
=
228 insn
.mm_fp0_format
.fd
;
229 mips32_insn
.fp0_format
.func
= func
;
234 func
= -1; /* Invalid */
235 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
237 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
240 mips32_insn
.fp0_format
.opcode
= cop1_op
;
241 mips32_insn
.fp0_format
.fmt
=
242 sdps_format
[insn
.mm_fp0_format
.fmt
];
243 mips32_insn
.fp0_format
.ft
=
244 insn
.mm_fp0_format
.ft
;
245 mips32_insn
.fp0_format
.fs
=
246 insn
.mm_fp0_format
.fs
;
247 mips32_insn
.fp0_format
.fd
=
248 insn
.mm_fp0_format
.fd
;
249 mips32_insn
.fp0_format
.func
= func
;
253 case mm_32f_73_op
: /* POOL32FXF */
254 switch (insn
.mm_fp1_format
.op
) {
259 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
264 mips32_insn
.r_format
.opcode
= spec_op
;
265 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
266 mips32_insn
.r_format
.rt
=
267 (insn
.mm_fp4_format
.cc
<< 2) + op
;
268 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
269 mips32_insn
.r_format
.re
= 0;
270 mips32_insn
.r_format
.func
= movc_op
;
276 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
279 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
282 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
284 mips32_insn
.fp0_format
.opcode
= cop1_op
;
285 mips32_insn
.fp0_format
.fmt
= fmt
;
286 mips32_insn
.fp0_format
.ft
= 0;
287 mips32_insn
.fp0_format
.fs
=
288 insn
.mm_fp3_format
.fs
;
289 mips32_insn
.fp0_format
.fd
=
290 insn
.mm_fp3_format
.rt
;
291 mips32_insn
.fp0_format
.func
= func
;
299 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
302 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
307 mips32_insn
.fp0_format
.opcode
= cop1_op
;
308 mips32_insn
.fp0_format
.fmt
=
309 sdps_format
[insn
.mm_fp3_format
.fmt
];
310 mips32_insn
.fp0_format
.ft
= 0;
311 mips32_insn
.fp0_format
.fs
=
312 insn
.mm_fp3_format
.fs
;
313 mips32_insn
.fp0_format
.fd
=
314 insn
.mm_fp3_format
.rt
;
315 mips32_insn
.fp0_format
.func
= func
;
327 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
329 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
331 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
333 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
335 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
337 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
339 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
341 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
343 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
347 mips32_insn
.fp0_format
.opcode
= cop1_op
;
348 mips32_insn
.fp0_format
.fmt
=
349 sd_format
[insn
.mm_fp1_format
.fmt
];
350 mips32_insn
.fp0_format
.ft
= 0;
351 mips32_insn
.fp0_format
.fs
=
352 insn
.mm_fp1_format
.fs
;
353 mips32_insn
.fp0_format
.fd
=
354 insn
.mm_fp1_format
.rt
;
355 mips32_insn
.fp0_format
.func
= func
;
360 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
362 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
366 mips32_insn
.fp0_format
.opcode
= cop1_op
;
367 mips32_insn
.fp0_format
.fmt
=
368 sdps_format
[insn
.mm_fp1_format
.fmt
];
369 mips32_insn
.fp0_format
.ft
= 0;
370 mips32_insn
.fp0_format
.fs
=
371 insn
.mm_fp1_format
.fs
;
372 mips32_insn
.fp0_format
.fd
=
373 insn
.mm_fp1_format
.rt
;
374 mips32_insn
.fp0_format
.func
= func
;
382 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
384 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
386 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
388 else if (insn
.mm_fp1_format
.op
== mm_ctc1_op
)
390 else if (insn
.mm_fp1_format
.op
== mm_mfhc1_op
)
394 mips32_insn
.fp1_format
.opcode
= cop1_op
;
395 mips32_insn
.fp1_format
.op
= op
;
396 mips32_insn
.fp1_format
.rt
=
397 insn
.mm_fp1_format
.rt
;
398 mips32_insn
.fp1_format
.fs
=
399 insn
.mm_fp1_format
.fs
;
400 mips32_insn
.fp1_format
.fd
= 0;
401 mips32_insn
.fp1_format
.func
= 0;
407 case mm_32f_74_op
: /* c.cond.fmt */
408 mips32_insn
.fp0_format
.opcode
= cop1_op
;
409 mips32_insn
.fp0_format
.fmt
=
410 sdps_format
[insn
.mm_fp4_format
.fmt
];
411 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
412 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
413 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
414 mips32_insn
.fp0_format
.func
=
415 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
425 *insn_ptr
= mips32_insn
;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
436 unsigned long *contpc
)
438 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
440 unsigned int bit
= 0;
442 switch (insn
.i_format
.opcode
) {
444 switch (insn
.r_format
.func
) {
446 regs
->regs
[insn
.r_format
.rd
] =
447 regs
->cp0_epc
+ dec_insn
.pc_inc
+
448 dec_insn
.next_pc_inc
;
451 /* For R6, JR already emulated in jalr_op */
452 if (NO_R6EMU
&& insn
.r_format
.opcode
== jr_op
)
454 *contpc
= regs
->regs
[insn
.r_format
.rs
];
459 switch (insn
.i_format
.rt
) {
462 if (NO_R6EMU
&& (insn
.i_format
.rs
||
463 insn
.i_format
.rt
== bltzall_op
))
466 regs
->regs
[31] = regs
->cp0_epc
+
468 dec_insn
.next_pc_inc
;
474 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
475 *contpc
= regs
->cp0_epc
+
477 (insn
.i_format
.simmediate
<< 2);
479 *contpc
= regs
->cp0_epc
+
481 dec_insn
.next_pc_inc
;
485 if (NO_R6EMU
&& (insn
.i_format
.rs
||
486 insn
.i_format
.rt
== bgezall_op
))
489 regs
->regs
[31] = regs
->cp0_epc
+
491 dec_insn
.next_pc_inc
;
497 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
498 *contpc
= regs
->cp0_epc
+
500 (insn
.i_format
.simmediate
<< 2);
502 *contpc
= regs
->cp0_epc
+
504 dec_insn
.next_pc_inc
;
511 regs
->regs
[31] = regs
->cp0_epc
+
513 dec_insn
.next_pc_inc
;
516 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
519 *contpc
|= (insn
.j_format
.target
<< 2);
520 /* Set microMIPS mode bit: XOR for jalx. */
527 if (regs
->regs
[insn
.i_format
.rs
] ==
528 regs
->regs
[insn
.i_format
.rt
])
529 *contpc
= regs
->cp0_epc
+
531 (insn
.i_format
.simmediate
<< 2);
533 *contpc
= regs
->cp0_epc
+
535 dec_insn
.next_pc_inc
;
541 if (regs
->regs
[insn
.i_format
.rs
] !=
542 regs
->regs
[insn
.i_format
.rt
])
543 *contpc
= regs
->cp0_epc
+
545 (insn
.i_format
.simmediate
<< 2);
547 *contpc
= regs
->cp0_epc
+
549 dec_insn
.next_pc_inc
;
557 * Compact branches for R6 for the
558 * blez and blezl opcodes.
559 * BLEZ | rs = 0 | rt != 0 == BLEZALC
560 * BLEZ | rs = rt != 0 == BGEZALC
561 * BLEZ | rs != 0 | rt != 0 == BGEUC
562 * BLEZL | rs = 0 | rt != 0 == BLEZC
563 * BLEZL | rs = rt != 0 == BGEZC
564 * BLEZL | rs != 0 | rt != 0 == BGEC
566 * For real BLEZ{,L}, rt is always 0.
568 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
569 if ((insn
.i_format
.opcode
== blez_op
) &&
570 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
571 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
572 regs
->regs
[31] = regs
->cp0_epc
+
574 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
575 dec_insn
.next_pc_inc
;
579 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
580 *contpc
= regs
->cp0_epc
+
582 (insn
.i_format
.simmediate
<< 2);
584 *contpc
= regs
->cp0_epc
+
586 dec_insn
.next_pc_inc
;
593 * Compact branches for R6 for the
594 * bgtz and bgtzl opcodes.
595 * BGTZ | rs = 0 | rt != 0 == BGTZALC
596 * BGTZ | rs = rt != 0 == BLTZALC
597 * BGTZ | rs != 0 | rt != 0 == BLTUC
598 * BGTZL | rs = 0 | rt != 0 == BGTZC
599 * BGTZL | rs = rt != 0 == BLTZC
600 * BGTZL | rs != 0 | rt != 0 == BLTC
602 * *ZALC varint for BGTZ &&& rt != 0
603 * For real GTZ{,L}, rt is always 0.
605 if (cpu_has_mips_r6
&& insn
.i_format
.rt
) {
606 if ((insn
.i_format
.opcode
== blez_op
) &&
607 ((!insn
.i_format
.rs
&& insn
.i_format
.rt
) ||
608 (insn
.i_format
.rs
== insn
.i_format
.rt
)))
609 regs
->regs
[31] = regs
->cp0_epc
+
611 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
612 dec_insn
.next_pc_inc
;
617 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
618 *contpc
= regs
->cp0_epc
+
620 (insn
.i_format
.simmediate
<< 2);
622 *contpc
= regs
->cp0_epc
+
624 dec_insn
.next_pc_inc
;
628 if (!cpu_has_mips_r6
)
630 if (insn
.i_format
.rt
&& !insn
.i_format
.rs
)
631 regs
->regs
[31] = regs
->cp0_epc
+ 4;
632 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
633 dec_insn
.next_pc_inc
;
636 #ifdef CONFIG_CPU_CAVIUM_OCTEON
637 case lwc2_op
: /* This is bbit0 on Octeon */
638 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
)) == 0)
639 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
641 *contpc
= regs
->cp0_epc
+ 8;
643 case ldc2_op
: /* This is bbit032 on Octeon */
644 if ((regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32))) == 0)
645 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
647 *contpc
= regs
->cp0_epc
+ 8;
649 case swc2_op
: /* This is bbit1 on Octeon */
650 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<insn
.i_format
.rt
))
651 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
653 *contpc
= regs
->cp0_epc
+ 8;
655 case sdc2_op
: /* This is bbit132 on Octeon */
656 if (regs
->regs
[insn
.i_format
.rs
] & (1ull<<(insn
.i_format
.rt
+ 32)))
657 *contpc
= regs
->cp0_epc
+ 4 + (insn
.i_format
.simmediate
<< 2);
659 *contpc
= regs
->cp0_epc
+ 8;
664 * Only valid for MIPS R6 but we can still end up
665 * here from a broken userland so just tell emulator
666 * this is not a branch and let it break later on.
668 if (!cpu_has_mips_r6
)
670 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
671 dec_insn
.next_pc_inc
;
675 if (!cpu_has_mips_r6
)
677 regs
->regs
[31] = regs
->cp0_epc
+ 4;
678 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
679 dec_insn
.next_pc_inc
;
683 if (!cpu_has_mips_r6
)
685 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
686 dec_insn
.next_pc_inc
;
692 /* Need to check for R6 bc1nez and bc1eqz branches */
693 if (cpu_has_mips_r6
&&
694 ((insn
.i_format
.rs
== bc1eqz_op
) ||
695 (insn
.i_format
.rs
== bc1nez_op
))) {
697 switch (insn
.i_format
.rs
) {
699 if (get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1)
703 if (!(get_fpr32(¤t
->thread
.fpu
.fpr
[insn
.i_format
.rt
], 0) & 0x1))
708 *contpc
= regs
->cp0_epc
+
710 (insn
.i_format
.simmediate
<< 2);
712 *contpc
= regs
->cp0_epc
+
714 dec_insn
.next_pc_inc
;
718 /* R2/R6 compatible cop1 instruction. Fall through */
721 if (insn
.i_format
.rs
== bc_op
) {
724 fcr31
= read_32bit_cp1_register(CP1_STATUS
);
726 fcr31
= current
->thread
.fpu
.fcr31
;
729 bit
= (insn
.i_format
.rt
>> 2);
732 switch (insn
.i_format
.rt
& 3) {
735 if (~fcr31
& (1 << bit
))
736 *contpc
= regs
->cp0_epc
+
738 (insn
.i_format
.simmediate
<< 2);
740 *contpc
= regs
->cp0_epc
+
742 dec_insn
.next_pc_inc
;
746 if (fcr31
& (1 << bit
))
747 *contpc
= regs
->cp0_epc
+
749 (insn
.i_format
.simmediate
<< 2);
751 *contpc
= regs
->cp0_epc
+
753 dec_insn
.next_pc_inc
;
763 * In the Linux kernel, we support selection of FPR format on the
764 * basis of the Status.FR bit. If an FPU is not present, the FR bit
765 * is hardwired to zero, which would imply a 32-bit FPU even for
766 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
767 * FPU emu is slow and bulky and optimizing this function offers fairly
768 * sizeable benefits so we try to be clever and make this function return
769 * a constant whenever possible, that is on 64-bit kernels without O32
770 * compatibility enabled and on 32-bit without 64-bit FPU support.
772 static inline int cop1_64bit(struct pt_regs
*xcp
)
774 if (config_enabled(CONFIG_64BIT
) && !config_enabled(CONFIG_MIPS32_O32
))
776 else if (config_enabled(CONFIG_32BIT
) &&
777 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT
))
780 return !test_thread_flag(TIF_32BIT_FPREGS
);
783 static inline bool hybrid_fprs(void)
785 return test_thread_flag(TIF_HYBRID_FPREGS
);
788 #define SIFROMREG(si, x) \
790 if (cop1_64bit(xcp) && !hybrid_fprs()) \
791 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
793 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
796 #define SITOREG(si, x) \
798 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
800 set_fpr32(&ctx->fpr[x], 0, si); \
801 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
802 set_fpr32(&ctx->fpr[x], i, 0); \
804 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
808 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
810 #define SITOHREG(si, x) \
813 set_fpr32(&ctx->fpr[x], 1, si); \
814 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
815 set_fpr32(&ctx->fpr[x], i, 0); \
818 #define DIFROMREG(di, x) \
819 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
821 #define DITOREG(di, x) \
824 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
825 set_fpr64(&ctx->fpr[fpr], 0, di); \
826 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
827 set_fpr64(&ctx->fpr[fpr], i, 0); \
830 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
831 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
832 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
833 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
836 * Emulate the single floating point instruction pointed at by EPC.
837 * Two instructions if the instruction is in a branch delay slot.
840 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
841 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
843 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
844 unsigned int cond
, cbit
;
855 * These are giving gcc a gentle hint about what to expect in
856 * dec_inst in order to do better optimization.
858 if (!cpu_has_mmips
&& dec_insn
.micro_mips_mode
)
861 /* XXX NEC Vr54xx bug workaround */
862 if (delay_slot(xcp
)) {
863 if (dec_insn
.micro_mips_mode
) {
864 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
865 clear_delay_slot(xcp
);
867 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
868 clear_delay_slot(xcp
);
872 if (delay_slot(xcp
)) {
874 * The instruction to be emulated is in a branch delay slot
875 * which means that we have to emulate the branch instruction
876 * BEFORE we do the cop1 instruction.
878 * This branch could be a COP1 branch, but in that case we
879 * would have had a trap for that instruction, and would not
880 * come through this route.
882 * Linux MIPS branch emulator operates on context, updating the
885 ir
= dec_insn
.next_insn
; /* process delay slot instr */
886 pc_inc
= dec_insn
.next_pc_inc
;
888 ir
= dec_insn
.insn
; /* process current instr */
889 pc_inc
= dec_insn
.pc_inc
;
893 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
894 * instructions, we want to convert microMIPS FPU instructions
895 * into MIPS32 instructions so that we could reuse all of the
896 * FPU emulation code.
898 * NOTE: We cannot do this for branch instructions since they
899 * are not a subset. Example: Cannot emulate a 16-bit
900 * aligned target address with a MIPS32 instruction.
902 if (dec_insn
.micro_mips_mode
) {
904 * If next instruction is a 16-bit instruction, then it
905 * it cannot be a FPU instruction. This could happen
906 * since we can be called for non-FPU instructions.
909 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
915 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
916 MIPS_FPU_EMU_INC_STATS(emulated
);
917 switch (MIPSInst_OPCODE(ir
)) {
919 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
921 MIPS_FPU_EMU_INC_STATS(loads
);
923 if (!access_ok(VERIFY_READ
, dva
, sizeof(u64
))) {
924 MIPS_FPU_EMU_INC_STATS(errors
);
928 if (__get_user(dval
, dva
)) {
929 MIPS_FPU_EMU_INC_STATS(errors
);
933 DITOREG(dval
, MIPSInst_RT(ir
));
937 dva
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
939 MIPS_FPU_EMU_INC_STATS(stores
);
940 DIFROMREG(dval
, MIPSInst_RT(ir
));
941 if (!access_ok(VERIFY_WRITE
, dva
, sizeof(u64
))) {
942 MIPS_FPU_EMU_INC_STATS(errors
);
946 if (__put_user(dval
, dva
)) {
947 MIPS_FPU_EMU_INC_STATS(errors
);
954 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
956 MIPS_FPU_EMU_INC_STATS(loads
);
957 if (!access_ok(VERIFY_READ
, wva
, sizeof(u32
))) {
958 MIPS_FPU_EMU_INC_STATS(errors
);
962 if (__get_user(wval
, wva
)) {
963 MIPS_FPU_EMU_INC_STATS(errors
);
967 SITOREG(wval
, MIPSInst_RT(ir
));
971 wva
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
973 MIPS_FPU_EMU_INC_STATS(stores
);
974 SIFROMREG(wval
, MIPSInst_RT(ir
));
975 if (!access_ok(VERIFY_WRITE
, wva
, sizeof(u32
))) {
976 MIPS_FPU_EMU_INC_STATS(errors
);
980 if (__put_user(wval
, wva
)) {
981 MIPS_FPU_EMU_INC_STATS(errors
);
988 switch (MIPSInst_RS(ir
)) {
990 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
993 /* copregister fs -> gpr[rt] */
994 if (MIPSInst_RT(ir
) != 0) {
995 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1001 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1004 /* copregister fs <- rt */
1005 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1009 if (!cpu_has_mips_r2
)
1012 /* copregister rd -> gpr[rt] */
1013 if (MIPSInst_RT(ir
) != 0) {
1014 SIFROMHREG(xcp
->regs
[MIPSInst_RT(ir
)],
1020 if (!cpu_has_mips_r2
)
1023 /* copregister rd <- gpr[rt] */
1024 SITOHREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1028 /* copregister rd -> gpr[rt] */
1029 if (MIPSInst_RT(ir
) != 0) {
1030 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1036 /* copregister rd <- rt */
1037 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1041 /* cop control register rd -> gpr[rt] */
1042 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1044 value
= (value
& ~FPU_CSR_RM
) | modeindex(value
);
1045 pr_debug("%p gpr[%d]<-csr=%08x\n",
1046 (void *) (xcp
->cp0_epc
),
1047 MIPSInst_RT(ir
), value
);
1049 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1053 if (MIPSInst_RT(ir
))
1054 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1058 /* copregister rd <- rt */
1059 if (MIPSInst_RT(ir
) == 0)
1062 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1064 /* we only have one writable control reg
1066 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1067 pr_debug("%p gpr[%d]->csr=%08x\n",
1068 (void *) (xcp
->cp0_epc
),
1069 MIPSInst_RT(ir
), value
);
1072 * Don't write reserved bits,
1073 * and convert to ieee library modes
1075 ctx
->fcr31
= (value
& ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1078 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1084 if (delay_slot(xcp
))
1087 if (cpu_has_mips_4_5_r
)
1088 cbit
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1090 cbit
= FPU_CSR_COND
;
1091 cond
= ctx
->fcr31
& cbit
;
1094 switch (MIPSInst_RT(ir
) & 3) {
1105 /* thats an illegal instruction */
1109 set_delay_slot(xcp
);
1112 * Branch taken: emulate dslot instruction
1114 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1116 contpc
= MIPSInst_SIMM(ir
);
1117 ir
= dec_insn
.next_insn
;
1118 if (dec_insn
.micro_mips_mode
) {
1119 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1121 /* If 16-bit instruction, not FPU. */
1122 if ((dec_insn
.next_pc_inc
== 2) ||
1123 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1126 * Since this instruction will
1127 * be put on the stack with
1128 * 32-bit words, get around
1129 * this problem by putting a
1130 * NOP16 as the second one.
1132 if (dec_insn
.next_pc_inc
== 2)
1133 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1136 * Single step the non-CP1
1137 * instruction in the dslot.
1139 return mips_dsemul(xcp
, ir
, contpc
);
1142 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1144 switch (MIPSInst_OPCODE(ir
)) {
1153 if (cpu_has_mips_2_3_4_5
||
1164 if (cpu_has_mips_4_5
|| cpu_has_mips64
|| cpu_has_mips32r2
)
1165 /* its one of ours */
1171 if (!cpu_has_mips_4_5_r
)
1174 if (MIPSInst_FUNC(ir
) == movc_op
)
1180 * Single step the non-cp1
1181 * instruction in the dslot
1183 return mips_dsemul(xcp
, ir
, contpc
);
1184 } else if (likely
) { /* branch not taken */
1186 * branch likely nullifies
1187 * dslot if not taken
1189 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1190 contpc
+= dec_insn
.pc_inc
;
1192 * else continue & execute
1193 * dslot as normal insn
1199 if (!(MIPSInst_RS(ir
) & 0x10))
1202 /* a real fpu computation instruction */
1203 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1209 if (!cpu_has_mips_4_5
&& !cpu_has_mips64
&& !cpu_has_mips32r2
)
1212 sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1218 if (!cpu_has_mips_4_5_r
)
1221 if (MIPSInst_FUNC(ir
) != movc_op
)
1223 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1224 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1225 xcp
->regs
[MIPSInst_RD(ir
)] =
1226 xcp
->regs
[MIPSInst_RS(ir
)];
1234 xcp
->cp0_epc
= contpc
;
1235 clear_delay_slot(xcp
);
1241 * Conversion table from MIPS compare ops 48-63
1242 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1244 static const unsigned char cmptab
[8] = {
1245 0, /* cmp_0 (sig) cmp_sf */
1246 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1247 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1248 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1249 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1250 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1251 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1252 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1257 * Additional MIPS4 instructions
1260 #define DEF3OP(name, p, f1, f2, f3) \
1261 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1262 union ieee754##p s, union ieee754##p t) \
1264 struct _ieee754_csr ieee754_csr_save; \
1266 ieee754_csr_save = ieee754_csr; \
1268 ieee754_csr_save.cx |= ieee754_csr.cx; \
1269 ieee754_csr_save.sx |= ieee754_csr.sx; \
1271 ieee754_csr.cx |= ieee754_csr_save.cx; \
1272 ieee754_csr.sx |= ieee754_csr_save.sx; \
1276 static union ieee754dp
fpemu_dp_recip(union ieee754dp d
)
1278 return ieee754dp_div(ieee754dp_one(0), d
);
1281 static union ieee754dp
fpemu_dp_rsqrt(union ieee754dp d
)
1283 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1286 static union ieee754sp
fpemu_sp_recip(union ieee754sp s
)
1288 return ieee754sp_div(ieee754sp_one(0), s
);
1291 static union ieee754sp
fpemu_sp_rsqrt(union ieee754sp s
)
1293 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1296 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1297 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1298 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1299 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1300 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1301 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1302 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1303 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1305 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1306 mips_instruction ir
, void *__user
*fault_addr
)
1308 unsigned rcsr
= 0; /* resulting csr */
1310 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1312 switch (MIPSInst_FMA_FFMT(ir
)) {
1313 case s_fmt
:{ /* 0 */
1315 union ieee754sp(*handler
) (union ieee754sp
, union ieee754sp
, union ieee754sp
);
1316 union ieee754sp fd
, fr
, fs
, ft
;
1320 switch (MIPSInst_FUNC(ir
)) {
1322 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1323 xcp
->regs
[MIPSInst_FT(ir
)]);
1325 MIPS_FPU_EMU_INC_STATS(loads
);
1326 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1327 MIPS_FPU_EMU_INC_STATS(errors
);
1331 if (__get_user(val
, va
)) {
1332 MIPS_FPU_EMU_INC_STATS(errors
);
1336 SITOREG(val
, MIPSInst_FD(ir
));
1340 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1341 xcp
->regs
[MIPSInst_FT(ir
)]);
1343 MIPS_FPU_EMU_INC_STATS(stores
);
1345 SIFROMREG(val
, MIPSInst_FS(ir
));
1346 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1347 MIPS_FPU_EMU_INC_STATS(errors
);
1351 if (put_user(val
, va
)) {
1352 MIPS_FPU_EMU_INC_STATS(errors
);
1359 handler
= fpemu_sp_madd
;
1362 handler
= fpemu_sp_msub
;
1365 handler
= fpemu_sp_nmadd
;
1368 handler
= fpemu_sp_nmsub
;
1372 SPFROMREG(fr
, MIPSInst_FR(ir
));
1373 SPFROMREG(fs
, MIPSInst_FS(ir
));
1374 SPFROMREG(ft
, MIPSInst_FT(ir
));
1375 fd
= (*handler
) (fr
, fs
, ft
);
1376 SPTOREG(fd
, MIPSInst_FD(ir
));
1379 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1380 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1381 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1383 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1384 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1385 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1387 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1388 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1389 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1391 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1392 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1393 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1396 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1397 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1398 /*printk ("SIGFPE: FPU csr = %08x\n",
1411 case d_fmt
:{ /* 1 */
1412 union ieee754dp(*handler
) (union ieee754dp
, union ieee754dp
, union ieee754dp
);
1413 union ieee754dp fd
, fr
, fs
, ft
;
1417 switch (MIPSInst_FUNC(ir
)) {
1419 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1420 xcp
->regs
[MIPSInst_FT(ir
)]);
1422 MIPS_FPU_EMU_INC_STATS(loads
);
1423 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1424 MIPS_FPU_EMU_INC_STATS(errors
);
1428 if (__get_user(val
, va
)) {
1429 MIPS_FPU_EMU_INC_STATS(errors
);
1433 DITOREG(val
, MIPSInst_FD(ir
));
1437 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1438 xcp
->regs
[MIPSInst_FT(ir
)]);
1440 MIPS_FPU_EMU_INC_STATS(stores
);
1441 DIFROMREG(val
, MIPSInst_FS(ir
));
1442 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1443 MIPS_FPU_EMU_INC_STATS(errors
);
1447 if (__put_user(val
, va
)) {
1448 MIPS_FPU_EMU_INC_STATS(errors
);
1455 handler
= fpemu_dp_madd
;
1458 handler
= fpemu_dp_msub
;
1461 handler
= fpemu_dp_nmadd
;
1464 handler
= fpemu_dp_nmsub
;
1468 DPFROMREG(fr
, MIPSInst_FR(ir
));
1469 DPFROMREG(fs
, MIPSInst_FS(ir
));
1470 DPFROMREG(ft
, MIPSInst_FT(ir
));
1471 fd
= (*handler
) (fr
, fs
, ft
);
1472 DPTOREG(fd
, MIPSInst_FD(ir
));
1482 if (MIPSInst_FUNC(ir
) != pfetch_op
)
1485 /* ignore prefx operation */
1498 * Emulate a single COP1 arithmetic instruction.
1500 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1501 mips_instruction ir
)
1503 int rfmt
; /* resulting format */
1504 unsigned rcsr
= 0; /* resulting csr */
1513 } rv
; /* resulting value */
1516 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1517 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1518 case s_fmt
: { /* 0 */
1520 union ieee754sp(*b
) (union ieee754sp
, union ieee754sp
);
1521 union ieee754sp(*u
) (union ieee754sp
);
1523 union ieee754sp fs
, ft
;
1525 switch (MIPSInst_FUNC(ir
)) {
1528 handler
.b
= ieee754sp_add
;
1531 handler
.b
= ieee754sp_sub
;
1534 handler
.b
= ieee754sp_mul
;
1537 handler
.b
= ieee754sp_div
;
1542 if (!cpu_has_mips_4_5_r
)
1545 handler
.u
= ieee754sp_sqrt
;
1549 * Note that on some MIPS IV implementations such as the
1550 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1551 * achieve full IEEE-754 accuracy - however this emulator does.
1554 if (!cpu_has_mips_4_5_r2
)
1557 handler
.u
= fpemu_sp_rsqrt
;
1561 if (!cpu_has_mips_4_5_r2
)
1564 handler
.u
= fpemu_sp_recip
;
1568 if (!cpu_has_mips_4_5_r
)
1571 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1572 if (((ctx
->fcr31
& cond
) != 0) !=
1573 ((MIPSInst_FT(ir
) & 1) != 0))
1575 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1579 if (!cpu_has_mips_4_5_r
)
1582 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1584 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1588 if (!cpu_has_mips_4_5_r
)
1591 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1593 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1597 handler
.u
= ieee754sp_abs
;
1601 handler
.u
= ieee754sp_neg
;
1606 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1609 /* binary op on handler */
1611 SPFROMREG(fs
, MIPSInst_FS(ir
));
1612 SPFROMREG(ft
, MIPSInst_FT(ir
));
1614 rv
.s
= (*handler
.b
) (fs
, ft
);
1617 SPFROMREG(fs
, MIPSInst_FS(ir
));
1618 rv
.s
= (*handler
.u
) (fs
);
1621 if (ieee754_cxtest(IEEE754_INEXACT
)) {
1622 MIPS_FPU_EMU_INC_STATS(ieee754_inexact
);
1623 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1625 if (ieee754_cxtest(IEEE754_UNDERFLOW
)) {
1626 MIPS_FPU_EMU_INC_STATS(ieee754_underflow
);
1627 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1629 if (ieee754_cxtest(IEEE754_OVERFLOW
)) {
1630 MIPS_FPU_EMU_INC_STATS(ieee754_overflow
);
1631 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1633 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
)) {
1634 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv
);
1635 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1637 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
)) {
1638 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop
);
1639 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1643 /* unary conv ops */
1645 return SIGILL
; /* not defined */
1648 SPFROMREG(fs
, MIPSInst_FS(ir
));
1649 rv
.d
= ieee754dp_fsp(fs
);
1654 SPFROMREG(fs
, MIPSInst_FS(ir
));
1655 rv
.w
= ieee754sp_tint(fs
);
1663 if (!cpu_has_mips_2_3_4_5
&& !cpu_has_mips64
)
1666 oldrm
= ieee754_csr
.rm
;
1667 SPFROMREG(fs
, MIPSInst_FS(ir
));
1668 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1669 rv
.w
= ieee754sp_tint(fs
);
1670 ieee754_csr
.rm
= oldrm
;
1675 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1678 SPFROMREG(fs
, MIPSInst_FS(ir
));
1679 rv
.l
= ieee754sp_tlong(fs
);
1687 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1690 oldrm
= ieee754_csr
.rm
;
1691 SPFROMREG(fs
, MIPSInst_FS(ir
));
1692 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1693 rv
.l
= ieee754sp_tlong(fs
);
1694 ieee754_csr
.rm
= oldrm
;
1699 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1700 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1701 union ieee754sp fs
, ft
;
1703 SPFROMREG(fs
, MIPSInst_FS(ir
));
1704 SPFROMREG(ft
, MIPSInst_FT(ir
));
1705 rv
.w
= ieee754sp_cmp(fs
, ft
,
1706 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1708 if ((cmpop
& 0x8) && ieee754_cxtest
1709 (IEEE754_INVALID_OPERATION
))
1710 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1722 union ieee754dp fs
, ft
;
1724 union ieee754dp(*b
) (union ieee754dp
, union ieee754dp
);
1725 union ieee754dp(*u
) (union ieee754dp
);
1728 switch (MIPSInst_FUNC(ir
)) {
1731 handler
.b
= ieee754dp_add
;
1734 handler
.b
= ieee754dp_sub
;
1737 handler
.b
= ieee754dp_mul
;
1740 handler
.b
= ieee754dp_div
;
1745 if (!cpu_has_mips_2_3_4_5_r
)
1748 handler
.u
= ieee754dp_sqrt
;
1751 * Note that on some MIPS IV implementations such as the
1752 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1753 * achieve full IEEE-754 accuracy - however this emulator does.
1756 if (!cpu_has_mips_4_5_r2
)
1759 handler
.u
= fpemu_dp_rsqrt
;
1762 if (!cpu_has_mips_4_5_r2
)
1765 handler
.u
= fpemu_dp_recip
;
1768 if (!cpu_has_mips_4_5_r
)
1771 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1772 if (((ctx
->fcr31
& cond
) != 0) !=
1773 ((MIPSInst_FT(ir
) & 1) != 0))
1775 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1778 if (!cpu_has_mips_4_5_r
)
1781 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1783 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1786 if (!cpu_has_mips_4_5_r
)
1789 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1791 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1794 handler
.u
= ieee754dp_abs
;
1798 handler
.u
= ieee754dp_neg
;
1803 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1806 /* binary op on handler */
1808 DPFROMREG(fs
, MIPSInst_FS(ir
));
1809 DPFROMREG(ft
, MIPSInst_FT(ir
));
1811 rv
.d
= (*handler
.b
) (fs
, ft
);
1814 DPFROMREG(fs
, MIPSInst_FS(ir
));
1815 rv
.d
= (*handler
.u
) (fs
);
1822 DPFROMREG(fs
, MIPSInst_FS(ir
));
1823 rv
.s
= ieee754sp_fdp(fs
);
1828 return SIGILL
; /* not defined */
1831 DPFROMREG(fs
, MIPSInst_FS(ir
));
1832 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1840 if (!cpu_has_mips_2_3_4_5_r
)
1843 oldrm
= ieee754_csr
.rm
;
1844 DPFROMREG(fs
, MIPSInst_FS(ir
));
1845 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1846 rv
.w
= ieee754dp_tint(fs
);
1847 ieee754_csr
.rm
= oldrm
;
1852 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1855 DPFROMREG(fs
, MIPSInst_FS(ir
));
1856 rv
.l
= ieee754dp_tlong(fs
);
1864 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1867 oldrm
= ieee754_csr
.rm
;
1868 DPFROMREG(fs
, MIPSInst_FS(ir
));
1869 ieee754_csr
.rm
= modeindex(MIPSInst_FUNC(ir
));
1870 rv
.l
= ieee754dp_tlong(fs
);
1871 ieee754_csr
.rm
= oldrm
;
1876 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1877 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1878 union ieee754dp fs
, ft
;
1880 DPFROMREG(fs
, MIPSInst_FS(ir
));
1881 DPFROMREG(ft
, MIPSInst_FT(ir
));
1882 rv
.w
= ieee754dp_cmp(fs
, ft
,
1883 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1888 (IEEE754_INVALID_OPERATION
))
1889 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1902 switch (MIPSInst_FUNC(ir
)) {
1904 /* convert word to single precision real */
1905 SPFROMREG(fs
, MIPSInst_FS(ir
));
1906 rv
.s
= ieee754sp_fint(fs
.bits
);
1910 /* convert word to double precision real */
1911 SPFROMREG(fs
, MIPSInst_FS(ir
));
1912 rv
.d
= ieee754dp_fint(fs
.bits
);
1923 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1926 DIFROMREG(bits
, MIPSInst_FS(ir
));
1928 switch (MIPSInst_FUNC(ir
)) {
1930 /* convert long to single precision real */
1931 rv
.s
= ieee754sp_flong(bits
);
1935 /* convert long to double precision real */
1936 rv
.d
= ieee754dp_flong(bits
);
1949 * Update the fpu CSR register for this operation.
1950 * If an exception is required, generate a tidy SIGFPE exception,
1951 * without updating the result register.
1952 * Note: cause exception bits do not accumulate, they are rewritten
1953 * for each op; only the flag/sticky bits accumulate.
1955 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1956 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1957 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1962 * Now we can safely write the result back to the register file.
1967 if (cpu_has_mips_4_5_r
)
1968 cbit
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
1970 cbit
= FPU_CSR_COND
;
1974 ctx
->fcr31
&= ~cbit
;
1978 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
1981 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
1984 SITOREG(rv
.w
, MIPSInst_FD(ir
));
1987 if (!cpu_has_mips_3_4_5
&& !cpu_has_mips64
)
1990 DITOREG(rv
.l
, MIPSInst_FD(ir
));
1999 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2000 int has_fpu
, void *__user
*fault_addr
)
2002 unsigned long oldepc
, prevepc
;
2003 struct mm_decoded_insn dec_insn
;
2008 oldepc
= xcp
->cp0_epc
;
2010 prevepc
= xcp
->cp0_epc
;
2012 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2014 * Get next 2 microMIPS instructions and convert them
2015 * into 32-bit instructions.
2017 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2018 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2019 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2020 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2021 MIPS_FPU_EMU_INC_STATS(errors
);
2026 /* Get first instruction. */
2027 if (mm_insn_16bit(*instr_ptr
)) {
2028 /* Duplicate the half-word. */
2029 dec_insn
.insn
= (*instr_ptr
<< 16) |
2031 /* 16-bit instruction. */
2032 dec_insn
.pc_inc
= 2;
2035 dec_insn
.insn
= (*instr_ptr
<< 16) |
2037 /* 32-bit instruction. */
2038 dec_insn
.pc_inc
= 4;
2041 /* Get second instruction. */
2042 if (mm_insn_16bit(*instr_ptr
)) {
2043 /* Duplicate the half-word. */
2044 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2046 /* 16-bit instruction. */
2047 dec_insn
.next_pc_inc
= 2;
2049 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2051 /* 32-bit instruction. */
2052 dec_insn
.next_pc_inc
= 4;
2054 dec_insn
.micro_mips_mode
= 1;
2056 if ((get_user(dec_insn
.insn
,
2057 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2058 (get_user(dec_insn
.next_insn
,
2059 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2060 MIPS_FPU_EMU_INC_STATS(errors
);
2063 dec_insn
.pc_inc
= 4;
2064 dec_insn
.next_pc_inc
= 4;
2065 dec_insn
.micro_mips_mode
= 0;
2068 if ((dec_insn
.insn
== 0) ||
2069 ((dec_insn
.pc_inc
== 2) &&
2070 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2071 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2074 * The 'ieee754_csr' is an alias of
2075 * ctx->fcr31. No need to copy ctx->fcr31 to
2076 * ieee754_csr. But ieee754_csr.rm is ieee
2077 * library modes. (not mips rounding mode)
2079 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2088 } while (xcp
->cp0_epc
> prevepc
);
2090 /* SIGILL indicates a non-fpu instruction */
2091 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2092 /* but if EPC has advanced, then ignore it */