arch/mips/math-emu/dsemul.c

   1 #include <linux/compiler.h>
   2 #include <linux/mm.h>
   3 #include <linux/signal.h>
   4 #include <linux/smp.h>
   5 #include <linux/smp_lock.h>
   6
   7 #include <asm/asm.h>
   8 #include <asm/bootinfo.h>
   9 #include <asm/byteorder.h>
  10 #include <asm/cpu.h>
  11 #include <asm/inst.h>
  12 #include <asm/processor.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/branch.h>
  15 #include <asm/mipsregs.h>
  16 #include <asm/system.h>
  17 #include <asm/cacheflush.h>
  18
  19 #include <asm/fpu_emulator.h>
  20
  21 #include "ieee754.h"
  22 #include "dsemul.h"
  23
  24 /* Strap kernel emulator for full MIPS IV emulation */
  25
  26 #ifdef __mips
  27 #undef __mips
  28 #endif
  29 #define __mips 4
  30
  31 /*
  32  * Emulate the arbritrary instruction ir at xcp->cp0_epc.  Required when
  33  * we have to emulate the instruction in a COP1 branch delay slot.  Do
  34  * not change cp0_epc due to the instruction
  35  *
  36  * According to the spec:
  37  * 1) it shouldnt be a branch :-)
  38  * 2) it can be a COP instruction :-(
  39  * 3) if we are tring to run a protected memory space we must take
  40  *    special care on memory access instructions :-(
  41  */
  42
  43 /*
  44  * "Trampoline" return routine to catch exception following
  45  *  execution of delay-slot instruction execution.
  46  */
  47
  48 struct emuframe {
  49         mips_instruction        emul;
  50         mips_instruction        badinst;
  51         mips_instruction        cookie;
  52         unsigned long           epc;
  53 };
  54
  55 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
  56 {
  57         extern asmlinkage void handle_dsemulret(void);
  58         mips_instruction *dsemul_insns;
  59         struct emuframe *fr;
  60         int err;
  61
  62         if (ir == 0) {          /* a nop is easy */
  63                 regs->cp0_epc = cpc;
  64                 regs->cp0_cause &= ~CAUSEF_BD;
  65                 return 0;
  66         }
  67 #ifdef DSEMUL_TRACE
  68         printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
  69
  70 #endif
  71
  72         /*
  73          * The strategy is to push the instruction onto the user stack
  74          * and put a trap after it which we can catch and jump to
  75          * the required address any alternative apart from full
  76          * instruction emulation!!.
  77          *
  78          * Algorithmics used a system call instruction, and
  79          * borrowed that vector.  MIPS/Linux version is a bit
  80          * more heavyweight in the interests of portability and
  81          * multiprocessor support.  For Linux we generate a
  82          * an unaligned access and force an address error exception.
  83          *
  84          * For embedded systems (stand-alone) we prefer to use a
  85          * non-existing CP1 instruction. This prevents us from emulating
  86          * branches, but gives us a cleaner interface to the exception
  87          * handler (single entry point).
  88          */
  89
  90         /* Ensure that the two instructions are in the same cache line */
  91         dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
  92         fr = (struct emuframe *) dsemul_insns;
  93
  94         /* Verify that the stack pointer is not competely insane */
  95         if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
  96                 return SIGBUS;
  97
  98         err = __put_user(ir, &fr->emul);
  99         err |= __put_user((mips_instruction)BADINST, &fr->badinst);
 100         err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
 101         err |= __put_user(cpc, &fr->epc);
 102
 103         if (unlikely(err)) {
 104                 fpuemustats.errors++;
 105                 return SIGBUS;
 106         }
 107
 108         regs->cp0_epc = (unsigned long) &fr->emul;
 109
 110         flush_cache_sigtramp((unsigned long)&fr->badinst);
 111
 112         return SIGILL;          /* force out of emulation loop */
 113 }
 114
 115 int do_dsemulret(struct pt_regs *xcp)
 116 {
 117         struct emuframe *fr;
 118         unsigned long epc;
 119         u32 insn, cookie;
 120         int err = 0;
 121
 122         fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction));
 123
 124         /*
 125          * If we can't even access the area, something is very wrong, but we'll
 126          * leave that to the default handling
 127          */
 128         if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
 129                 return 0;
 130
 131         /*
 132          * Do some sanity checking on the stackframe:
 133          *
 134          *  - Is the instruction pointed to by the EPC an BADINST?
 135          *  - Is the following memory word the BD_COOKIE?
 136          */
 137         err = __get_user(insn, &fr->badinst);
 138         err |= __get_user(cookie, &fr->cookie);
 139
 140         if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
 141                 fpuemustats.errors++;
 142                 return 0;
 143         }
 144
 145         /*
 146          * At this point, we are satisfied that it's a BD emulation trap.  Yes,
 147          * a user might have deliberately put two malformed and useless
 148          * instructions in a row in his program, in which case he's in for a
 149          * nasty surprise - the next instruction will be treated as a
 150          * continuation address!  Alas, this seems to be the only way that we
 151          * can handle signals, recursion, and longjmps() in the context of
 152          * emulating the branch delay instruction.
 153          */
 154
 155 #ifdef DSEMUL_TRACE
 156         printk("dsemulret\n");
 157 #endif
 158         if (__get_user(epc, &fr->epc)) {                /* Saved EPC */
 159                 /* This is not a good situation to be in */
 160                 force_sig(SIGBUS, current);
 161
 162                 return 0;
 163         }
 164
 165         /* Set EPC to return to post-branch instruction */
 166         xcp->cp0_epc = epc;
 167
 168         return 1;
 169 }