arch/mips/math-emu/ieee754dp.c

   1 /* IEEE754 floating point arithmetic
   2  * double precision: common utilities
   3  */
   4 /*
   5  * MIPS floating point support
   6  * Copyright (C) 1994-2000 Algorithmics Ltd.
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, write to the Free Software Foundation, Inc.,
  19  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  20  */
  21
  22 #include <linux/compiler.h>
  23
  24 #include "ieee754dp.h"
  25
  26 int ieee754dp_class(union ieee754dp x)
  27 {
  28         COMPXDP;
  29         EXPLODEXDP;
  30         return xc;
  31 }
  32
  33 int ieee754dp_isnan(union ieee754dp x)
  34 {
  35         return ieee754dp_class(x) >= IEEE754_CLASS_SNAN;
  36 }
  37
  38 static inline int ieee754dp_issnan(union ieee754dp x)
  39 {
  40         assert(ieee754dp_isnan(x));
  41         return (DPMANT(x) & DP_MBIT(DP_FBITS - 1)) == DP_MBIT(DP_FBITS - 1);
  42 }
  43
  44
  45 union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r)
  46 {
  47         assert(ieee754dp_isnan(r));
  48
  49         if (!ieee754dp_issnan(r))       /* QNAN does not cause invalid op !! */
  50                 return r;
  51
  52         /* If not enabled convert to a quiet NaN.  */
  53         if (!ieee754_setandtestcx(IEEE754_INVALID_OPERATION))
  54                 return ieee754dp_indef();
  55
  56         return r;
  57 }
  58
  59 static u64 ieee754dp_get_rounding(int sn, u64 xm)
  60 {
  61         /* inexact must round of 3 bits
  62          */
  63         if (xm & (DP_MBIT(3) - 1)) {
  64                 switch (ieee754_csr.rm) {
  65                 case FPU_CSR_RZ:
  66                         break;
  67                 case FPU_CSR_RN:
  68                         xm += 0x3 + ((xm >> 3) & 1);
  69                         /* xm += (xm&0x8)?0x4:0x3 */
  70                         break;
  71                 case FPU_CSR_RU:        /* toward +Infinity */
  72                         if (!sn)        /* ?? */
  73                                 xm += 0x8;
  74                         break;
  75                 case FPU_CSR_RD:        /* toward -Infinity */
  76                         if (sn) /* ?? */
  77                                 xm += 0x8;
  78                         break;
  79                 }
  80         }
  81         return xm;
  82 }
  83
  84
  85 /* generate a normal/denormal number with over,under handling
  86  * sn is sign
  87  * xe is an unbiased exponent
  88  * xm is 3bit extended precision value.
  89  */
  90 union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
  91 {
  92         assert(xm);             /* we don't gen exact zeros (probably should) */
  93
  94         assert((xm >> (DP_FBITS + 1 + 3)) == 0);        /* no execess */
  95         assert(xm & (DP_HIDDEN_BIT << 3));
  96
  97         if (xe < DP_EMIN) {
  98                 /* strip lower bits */
  99                 int es = DP_EMIN - xe;
 100
 101                 if (ieee754_csr.nod) {
 102                         ieee754_setcx(IEEE754_UNDERFLOW);
 103                         ieee754_setcx(IEEE754_INEXACT);
 104
 105                         switch(ieee754_csr.rm) {
 106                         case FPU_CSR_RN:
 107                         case FPU_CSR_RZ:
 108                                 return ieee754dp_zero(sn);
 109                         case FPU_CSR_RU:    /* toward +Infinity */
 110                                 if (sn == 0)
 111                                         return ieee754dp_min(0);
 112                                 else
 113                                         return ieee754dp_zero(1);
 114                         case FPU_CSR_RD:    /* toward -Infinity */
 115                                 if (sn == 0)
 116                                         return ieee754dp_zero(0);
 117                                 else
 118                                         return ieee754dp_min(1);
 119                         }
 120                 }
 121
 122                 if (xe == DP_EMIN - 1 &&
 123                     ieee754dp_get_rounding(sn, xm) >> (DP_FBITS + 1 + 3))
 124                 {
 125                         /* Not tiny after rounding */
 126                         ieee754_setcx(IEEE754_INEXACT);
 127                         xm = ieee754dp_get_rounding(sn, xm);
 128                         xm >>= 1;
 129                         /* Clear grs bits */
 130                         xm &= ~(DP_MBIT(3) - 1);
 131                         xe++;
 132                 }
 133                 else {
 134                         /* sticky right shift es bits
 135                          */
 136                         xm = XDPSRS(xm, es);
 137                         xe += es;
 138                         assert((xm & (DP_HIDDEN_BIT << 3)) == 0);
 139                         assert(xe == DP_EMIN);
 140                 }
 141         }
 142         if (xm & (DP_MBIT(3) - 1)) {
 143                 ieee754_setcx(IEEE754_INEXACT);
 144                 if ((xm & (DP_HIDDEN_BIT << 3)) == 0) {
 145                         ieee754_setcx(IEEE754_UNDERFLOW);
 146                 }
 147
 148                 /* inexact must round of 3 bits
 149                  */
 150                 xm = ieee754dp_get_rounding(sn, xm);
 151                 /* adjust exponent for rounding add overflowing
 152                  */
 153                 if (xm >> (DP_FBITS + 3 + 1)) {
 154                         /* add causes mantissa overflow */
 155                         xm >>= 1;
 156                         xe++;
 157                 }
 158         }
 159         /* strip grs bits */
 160         xm >>= 3;
 161
 162         assert((xm >> (DP_FBITS + 1)) == 0);    /* no execess */
 163         assert(xe >= DP_EMIN);
 164
 165         if (xe > DP_EMAX) {
 166                 ieee754_setcx(IEEE754_OVERFLOW);
 167                 ieee754_setcx(IEEE754_INEXACT);
 168                 /* -O can be table indexed by (rm,sn) */
 169                 switch (ieee754_csr.rm) {
 170                 case FPU_CSR_RN:
 171                         return ieee754dp_inf(sn);
 172                 case FPU_CSR_RZ:
 173                         return ieee754dp_max(sn);
 174                 case FPU_CSR_RU:        /* toward +Infinity */
 175                         if (sn == 0)
 176                                 return ieee754dp_inf(0);
 177                         else
 178                                 return ieee754dp_max(1);
 179                 case FPU_CSR_RD:        /* toward -Infinity */
 180                         if (sn == 0)
 181                                 return ieee754dp_max(0);
 182                         else
 183                                 return ieee754dp_inf(1);
 184                 }
 185         }
 186         /* gen norm/denorm/zero */
 187
 188         if ((xm & DP_HIDDEN_BIT) == 0) {
 189                 /* we underflow (tiny/zero) */
 190                 assert(xe == DP_EMIN);
 191                 if (ieee754_csr.mx & IEEE754_UNDERFLOW)
 192                         ieee754_setcx(IEEE754_UNDERFLOW);
 193                 return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm);
 194         } else {
 195                 assert((xm >> (DP_FBITS + 1)) == 0);    /* no execess */
 196                 assert(xm & DP_HIDDEN_BIT);
 197
 198                 return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT);
 199         }
 200 }