MIPS: math-emu: Switch to using the MIPS rounding modes.
[deliverable/linux.git] / arch / mips / math-emu / sp_add.c
1 /* IEEE754 floating point arithmetic
2 * single precision
3 */
4 /*
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22 #include "ieee754sp.h"
23
24 union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
25 {
26 int s;
27
28 COMPXSP;
29 COMPYSP;
30
31 EXPLODEXSP;
32 EXPLODEYSP;
33
34 ieee754_clearcx();
35
36 FLUSHXSP;
37 FLUSHYSP;
38
39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
51 ieee754_setcx(IEEE754_INVALID_OPERATION);
52 return ieee754sp_nanxcpt(ieee754sp_indef());
53
54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
56 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
58 return y;
59
60 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
61 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
63 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
64 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
65 return x;
66
67
68 /*
69 * Infinity handling
70 */
71 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
72 if (xs == ys)
73 return x;
74 ieee754_setcx(IEEE754_INVALID_OPERATION);
75 return ieee754sp_indef();
76
77 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
78 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
79 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
80 return y;
81
82 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
83 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
84 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
85 return x;
86
87 /*
88 * Zero handling
89 */
90 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
91 if (xs == ys)
92 return x;
93 else
94 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
95
96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
98 return x;
99
100 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
101 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
102 return y;
103
104 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
105 SPDNORMX;
106
107 /* FALL THROUGH */
108
109 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
110 SPDNORMY;
111 break;
112
113 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
114 SPDNORMX;
115 break;
116
117 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
118 break;
119 }
120 assert(xm & SP_HIDDEN_BIT);
121 assert(ym & SP_HIDDEN_BIT);
122
123 /*
124 * Provide guard, round and stick bit space.
125 */
126 xm <<= 3;
127 ym <<= 3;
128
129 if (xe > ye) {
130 /*
131 * Have to shift y fraction right to align.
132 */
133 s = xe - ye;
134 SPXSRSYn(s);
135 } else if (ye > xe) {
136 /*
137 * Have to shift x fraction right to align.
138 */
139 s = ye - xe;
140 SPXSRSXn(s);
141 }
142 assert(xe == ye);
143 assert(xe <= SP_EMAX);
144
145 if (xs == ys) {
146 /*
147 * Generate 28 bit result of adding two 27 bit numbers
148 * leaving result in xm, xs and xe.
149 */
150 xm = xm + ym;
151 xe = xe;
152 xs = xs;
153
154 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
155 SPXSRSX1();
156 }
157 } else {
158 if (xm >= ym) {
159 xm = xm - ym;
160 xe = xe;
161 xs = xs;
162 } else {
163 xm = ym - xm;
164 xe = xe;
165 xs = ys;
166 }
167 if (xm == 0)
168 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
169
170 /*
171 * Normalize in extended single precision
172 */
173 while ((xm >> (SP_FBITS + 3)) == 0) {
174 xm <<= 1;
175 xe--;
176 }
177 }
178
179 return ieee754sp_format(xs, xe, xm);
180 }
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