arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/i8253.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44
  45 #ifdef CONFIG_MIPS_MALTA
  46 #include <asm/mips-boards/maltaint.h>
  47 #endif
  48 #ifdef CONFIG_MIPS_SEAD
  49 #include <asm/mips-boards/seadint.h>
  50 #endif
  51
  52 unsigned long cpu_khz;
  53
  54 static int mips_cpu_timer_irq;
  55 static int mips_cpu_perf_irq;
  56 extern int cp0_perfcount_irq;
  57
  58 static void mips_timer_dispatch(void)
  59 {
  60         do_IRQ(mips_cpu_timer_irq);
  61 }
  62
  63 static void mips_perf_dispatch(void)
  64 {
  65         do_IRQ(mips_cpu_perf_irq);
  66 }
  67
  68 /*
  69  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  70  */
  71 static unsigned int __init estimate_cpu_frequency(void)
  72 {
  73         unsigned int prid = read_c0_prid() & 0xffff00;
  74         unsigned int count;
  75
  76 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
  77         /*
  78          * The SEAD board doesn't have a real time clock, so we can't
  79          * really calculate the timer frequency
  80          * For now we hardwire the SEAD board frequency to 12MHz.
  81          */
  82
  83         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
  84             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
  85                 count = 12000000;
  86         else
  87                 count = 6000000;
  88 #endif
  89 #ifdef CONFIG_MIPS_MALTA
  90         unsigned long flags;
  91         unsigned int start;
  92
  93         local_irq_save(flags);
  94
  95         /* Start counter exactly on falling edge of update flag */
  96         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  97         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  98
  99         /* Start r4k counter. */
 100         start = read_c0_count();
 101
 102         /* Read counter exactly on falling edge of update flag */
 103         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 104         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 105
 106         count = read_c0_count() - start;
 107
 108         /* restore interrupts */
 109         local_irq_restore(flags);
 110 #endif
 111
 112         mips_hpt_frequency = count;
 113         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 114             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 115                 count *= 2;
 116
 117         count += 5000;    /* round */
 118         count -= count%10000;
 119
 120         return count;
 121 }
 122
 123 unsigned long read_persistent_clock(void)
 124 {
 125         return mc146818_get_cmos_time();
 126 }
 127
 128 static void __init plat_perf_setup(void)
 129 {
 130 #ifdef MSC01E_INT_BASE
 131         if (cpu_has_veic) {
 132                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 133                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 134         } else
 135 #endif
 136         if (cp0_perfcount_irq >= 0) {
 137                 if (cpu_has_vint)
 138                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 139                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 140 #ifdef CONFIG_SMP
 141                 set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
 142 #endif
 143         }
 144 }
 145
 146 unsigned int __cpuinit get_c0_compare_int(void)
 147 {
 148 #ifdef MSC01E_INT_BASE
 149         if (cpu_has_veic) {
 150                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 151                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 152         } else
 153 #endif
 154         {
 155                 if (cpu_has_vint)
 156                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 157                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 158         }
 159
 160         return mips_cpu_timer_irq;
 161 }
 162
 163 void __init plat_time_init(void)
 164 {
 165         unsigned int est_freq;
 166
 167         /* Set Data mode - binary. */
 168         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 169
 170         est_freq = estimate_cpu_frequency();
 171
 172         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 173                (est_freq%1000000)*100/1000000);
 174
 175         cpu_khz = est_freq / 1000;
 176
 177         mips_scroll_message();
 178 #ifdef CONFIG_I8253             /* Only Malta has a PIT */
 179         setup_pit_timer();
 180 #endif
 181
 182         plat_perf_setup();
 183 }