arch/mips/netlogic/common/irq.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/init.h>
  37 #include <linux/linkage.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/mm.h>
  41 #include <linux/slab.h>
  42 #include <linux/irq.h>
  43
  44 #include <asm/errno.h>
  45 #include <asm/signal.h>
  46 #include <asm/system.h>
  47 #include <asm/ptrace.h>
  48 #include <asm/mipsregs.h>
  49 #include <asm/thread_info.h>
  50
  51 #include <asm/netlogic/mips-extns.h>
  52 #include <asm/netlogic/interrupt.h>
  53 #include <asm/netlogic/haldefs.h>
  54 #include <asm/netlogic/common.h>
  55
  56 #if defined(CONFIG_CPU_XLP)
  57 #include <asm/netlogic/xlp-hal/iomap.h>
  58 #include <asm/netlogic/xlp-hal/xlp.h>
  59 #include <asm/netlogic/xlp-hal/pic.h>
  60 #elif defined(CONFIG_CPU_XLR)
  61 #include <asm/netlogic/xlr/iomap.h>
  62 #include <asm/netlogic/xlr/pic.h>
  63 #else
  64 #error "Unknown CPU"
  65 #endif
  66 /*
  67  * These are the routines that handle all the low level interrupt stuff.
  68  * Actions handled here are: initialization of the interrupt map, requesting of
  69  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  70  * for interrupt lines
  71  */
  72
  73 /* Globals */
  74 static uint64_t nlm_irq_mask;
  75 static DEFINE_SPINLOCK(nlm_pic_lock);
  76
  77 static void xlp_pic_enable(struct irq_data *d)
  78 {
  79         unsigned long flags;
  80         int irt;
  81
  82         irt = nlm_irq_to_irt(d->irq);
  83         if (irt == -1)
  84                 return;
  85         spin_lock_irqsave(&nlm_pic_lock, flags);
  86         nlm_pic_enable_irt(nlm_pic_base, irt);
  87         spin_unlock_irqrestore(&nlm_pic_lock, flags);
  88 }
  89
  90 static void xlp_pic_disable(struct irq_data *d)
  91 {
  92         unsigned long flags;
  93         int irt;
  94
  95         irt = nlm_irq_to_irt(d->irq);
  96         if (irt == -1)
  97                 return;
  98         spin_lock_irqsave(&nlm_pic_lock, flags);
  99         nlm_pic_disable_irt(nlm_pic_base, irt);
 100         spin_unlock_irqrestore(&nlm_pic_lock, flags);
 101 }
 102
 103 static void xlp_pic_mask_ack(struct irq_data *d)
 104 {
 105         uint64_t mask = 1ull << d->irq;
 106
 107         write_c0_eirr(mask);            /* ack by writing EIRR */
 108 }
 109
 110 static void xlp_pic_unmask(struct irq_data *d)
 111 {
 112         void *hd = irq_data_get_irq_handler_data(d);
 113         int irt;
 114
 115         irt = nlm_irq_to_irt(d->irq);
 116         if (irt == -1)
 117                 return;
 118
 119         if (hd) {
 120                 void (*extra_ack)(void *) = hd;
 121                 extra_ack(d);
 122         }
 123         /* Ack is a single write, no need to lock */
 124         nlm_pic_ack(nlm_pic_base, irt);
 125 }
 126
 127 static struct irq_chip xlp_pic = {
 128         .name           = "XLP-PIC",
 129         .irq_enable     = xlp_pic_enable,
 130         .irq_disable    = xlp_pic_disable,
 131         .irq_mask_ack   = xlp_pic_mask_ack,
 132         .irq_unmask     = xlp_pic_unmask,
 133 };
 134
 135 static void cpuintr_disable(struct irq_data *d)
 136 {
 137         uint64_t eimr;
 138         uint64_t mask = 1ull << d->irq;
 139
 140         eimr = read_c0_eimr();
 141         write_c0_eimr(eimr & ~mask);
 142 }
 143
 144 static void cpuintr_enable(struct irq_data *d)
 145 {
 146         uint64_t eimr;
 147         uint64_t mask = 1ull << d->irq;
 148
 149         eimr = read_c0_eimr();
 150         write_c0_eimr(eimr | mask);
 151 }
 152
 153 static void cpuintr_ack(struct irq_data *d)
 154 {
 155         uint64_t mask = 1ull << d->irq;
 156
 157         write_c0_eirr(mask);
 158 }
 159
 160 static void cpuintr_nop(struct irq_data *d)
 161 {
 162         WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
 163 }
 164
 165 /*
 166  * Chip definition for CPU originated interrupts(timer, msg) and
 167  * IPIs
 168  */
 169 struct irq_chip nlm_cpu_intr = {
 170         .name           = "XLP-CPU-INTR",
 171         .irq_enable     = cpuintr_enable,
 172         .irq_disable    = cpuintr_disable,
 173         .irq_mask       = cpuintr_nop,
 174         .irq_ack        = cpuintr_nop,
 175         .irq_eoi        = cpuintr_ack,
 176 };
 177
 178 void __init init_nlm_common_irqs(void)
 179 {
 180         int i, irq, irt;
 181
 182         for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
 183                 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
 184
 185         for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
 186                 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
 187
 188 #ifdef CONFIG_SMP
 189         irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
 190                          nlm_smp_function_ipi_handler);
 191         irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
 192                          nlm_smp_resched_ipi_handler);
 193         nlm_irq_mask |=
 194             ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
 195 #endif
 196
 197         for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
 198                 irt = nlm_irq_to_irt(irq);
 199                 if (irt == -1)
 200                         continue;
 201                 nlm_irq_mask |= (1ULL << irq);
 202                 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
 203         }
 204
 205         nlm_irq_mask |= (1ULL << IRQ_TIMER);
 206 }
 207
 208 void __init arch_init_irq(void)
 209 {
 210         /* Initialize the irq descriptors */
 211         init_nlm_common_irqs();
 212
 213         write_c0_eimr(nlm_irq_mask);
 214 }
 215
 216 void __cpuinit nlm_smp_irq_init(void)
 217 {
 218         /* set interrupt mask for non-zero cpus */
 219         write_c0_eimr(nlm_irq_mask);
 220 }
 221
 222 asmlinkage void plat_irq_dispatch(void)
 223 {
 224         uint64_t eirr;
 225         int i;
 226
 227         eirr = read_c0_eirr() & read_c0_eimr();
 228         if (eirr & (1 << IRQ_TIMER)) {
 229                 do_IRQ(IRQ_TIMER);
 230                 return;
 231         }
 232
 233         i = __ilog2_u64(eirr);
 234         if (i == -1)
 235                 return;
 236
 237         do_IRQ(i);
 238 }