arch/mips/netlogic/common/smpboot.S

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <asm/asm.h>
  38 #include <asm/asm-offsets.h>
  39 #include <asm/regdef.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/stackframe.h>
  42 #include <asm/asmmacro.h>
  43 #include <asm/addrspace.h>
  44
  45 #include <asm/netlogic/common.h>
  46
  47 #include <asm/netlogic/xlp-hal/iomap.h>
  48 #include <asm/netlogic/xlp-hal/xlp.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50 #include <asm/netlogic/xlp-hal/cpucontrol.h>
  51
  52 #define CP0_EBASE       $15
  53
  54         .set    noreorder
  55         .set    noat
  56         .set    arch=xlr                /* for mfcr/mtcr, XLR is sufficient */
  57
  58 FEXPORT(xlp_boot_core0_siblings)        /* "Master" cpu starts from here */
  59         dmtc0   sp, $4, 2               /* SP saved in UserLocal */
  60         SAVE_ALL
  61         sync
  62         /* find the location to which nlm_boot_siblings was relocated */
  63         li      t0, CKSEG1ADDR(RESET_VEC_PHYS)
  64         dla     t1, nlm_reset_entry
  65         dla     t2, nlm_boot_siblings
  66         dsubu   t2, t1
  67         daddu   t2, t0
  68         /* call it */
  69         jr      t2
  70         nop
  71         /* not reached */
  72
  73 NESTED(nlm_boot_secondary_cpus, 16, sp)
  74         /* Initialize CP0 Status */
  75         move    t1, zero
  76 #ifdef CONFIG_64BIT
  77         ori     t1, ST0_KX
  78 #endif
  79         mtc0    t1, CP0_STATUS
  80         PTR_LA  t1, nlm_next_sp
  81         PTR_L   sp, 0(t1)
  82         PTR_LA  t1, nlm_next_gp
  83         PTR_L   gp, 0(t1)
  84
  85         /* a0 has the processor id */
  86         mfc0    a0, CP0_EBASE, 1
  87         andi    a0, 0x3ff               /* a0 <- node/core */
  88         PTR_LA  t0, nlm_early_init_secondary
  89         jalr    t0
  90         nop
  91
  92         PTR_LA  t0, smp_bootstrap
  93         jr      t0
  94         nop
  95 END(nlm_boot_secondary_cpus)
  96
  97 /*
  98  * In case of RMIboot bootloader which is used on XLR boards, the CPUs
  99  * be already woken up and waiting in bootloader code.
 100  * This will get them out of the bootloader code and into linux. Needed
 101  *  because the bootloader area will be taken and initialized by linux.
 102  */
 103 NESTED(nlm_rmiboot_preboot, 16, sp)
 104         mfc0    t0, $15, 1      /* read ebase */
 105         andi    t0, 0x1f        /* t0 has the processor_id() */
 106         andi    t2, t0, 0x3     /* thread num */
 107         sll     t0, 2           /* offset in cpu array */
 108
 109         li      t3, CKSEG1ADDR(RESET_DATA_PHYS)
 110         ADDIU   t1, t3, BOOT_CPU_READY
 111         ADDU    t1, t0
 112         li      t3, 1
 113         sw      t3, 0(t1)
 114
 115         bnez    t2, 1f          /* skip thread programming */
 116         nop                     /* for thread id != 0 */
 117
 118         /*
 119          * XLR MMU setup only for first thread in core
 120          */
 121         li      t0, 0x400
 122         mfcr    t1, t0
 123         li      t2, 6           /* XLR thread mode mask */
 124         nor     t3, t2, zero
 125         and     t2, t1, t2      /* t2 - current thread mode */
 126         li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
 127         lw      v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
 128         sll     v1, 1
 129         beq     v1, t2, 1f      /* same as request value */
 130         nop                     /* nothing to do */
 131
 132         and     t2, t1, t3      /* mask out old thread mode */
 133         or      t1, t2, v1      /* put in new value */
 134         mtcr    t1, t0          /* update core control */
 135
 136 1:      wait
 137         b       1b
 138         nop
 139 END(nlm_rmiboot_preboot)