arch/mips/netlogic/xlp/usb-init-xlp2.c

   1 /*
   2  * Copyright (c) 2003-2013 Broadcom Corporation
   3  * All Rights Reserved
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the Broadcom
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/dma-mapping.h>
  36 #include <linux/kernel.h>
  37 #include <linux/delay.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/irq.h>
  42
  43 #include <asm/netlogic/common.h>
  44 #include <asm/netlogic/haldefs.h>
  45 #include <asm/netlogic/xlp-hal/iomap.h>
  46 #include <asm/netlogic/xlp-hal/xlp.h>
  47
  48 #define XLPII_USB3_CTL_0                0xc0
  49 #define XLPII_VAUXRST                   BIT(0)
  50 #define XLPII_VCCRST                    BIT(1)
  51 #define XLPII_NUM2PORT                  9
  52 #define XLPII_NUM3PORT                  13
  53 #define XLPII_RTUNEREQ                  BIT(20)
  54 #define XLPII_MS_CSYSREQ                BIT(21)
  55 #define XLPII_XS_CSYSREQ                BIT(22)
  56 #define XLPII_RETENABLEN                BIT(23)
  57 #define XLPII_TX2RX                     BIT(24)
  58 #define XLPII_XHCIREV                   BIT(25)
  59 #define XLPII_ECCDIS                    BIT(26)
  60
  61 #define XLPII_USB3_INT_REG              0xc2
  62 #define XLPII_USB3_INT_MASK             0xc3
  63
  64 #define XLPII_USB_PHY_TEST              0xc6
  65 #define XLPII_PRESET                    BIT(0)
  66 #define XLPII_ATERESET                  BIT(1)
  67 #define XLPII_LOOPEN                    BIT(2)
  68 #define XLPII_TESTPDHSP                 BIT(3)
  69 #define XLPII_TESTPDSSP                 BIT(4)
  70 #define XLPII_TESTBURNIN                BIT(5)
  71
  72 #define XLPII_USB_PHY_LOS_LV            0xc9
  73 #define XLPII_LOSLEV                    0
  74 #define XLPII_LOSBIAS                   5
  75 #define XLPII_SQRXTX                    8
  76 #define XLPII_TXBOOST                   11
  77 #define XLPII_RSLKSEL                   16
  78 #define XLPII_FSEL                      20
  79
  80 #define XLPII_USB_RFCLK_REG             0xcc
  81 #define XLPII_VVLD                      30
  82
  83 #define nlm_read_usb_reg(b, r)          nlm_read_reg(b, r)
  84 #define nlm_write_usb_reg(b, r, v)      nlm_write_reg(b, r, v)
  85
  86 #define nlm_xlpii_get_usb_pcibase(node, inst)           \
  87         nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst))
  88 #define nlm_xlpii_get_usb_regbase(node, inst)           \
  89         (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
  90
  91 static void xlpii_usb_ack(struct irq_data *data)
  92 {
  93         u64 port_addr;
  94
  95         switch (data->irq) {
  96         case PIC_2XX_XHCI_0_IRQ:
  97                 port_addr = nlm_xlpii_get_usb_regbase(0, 1);
  98                 break;
  99         case PIC_2XX_XHCI_1_IRQ:
 100                 port_addr = nlm_xlpii_get_usb_regbase(0, 2);
 101                 break;
 102         case PIC_2XX_XHCI_2_IRQ:
 103                 port_addr = nlm_xlpii_get_usb_regbase(0, 3);
 104                 break;
 105         default:
 106                 pr_err("No matching USB irq!\n");
 107                 return;
 108         }
 109         nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
 110 }
 111
 112 static void nlm_xlpii_usb_hw_reset(int node, int port)
 113 {
 114         u64 port_addr, xhci_base, pci_base;
 115         void __iomem *corebase;
 116         u32 val;
 117
 118         port_addr = nlm_xlpii_get_usb_regbase(node, port);
 119
 120         /* Set frequency */
 121         val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV);
 122         val &= ~(0x3f << XLPII_FSEL);
 123         val |= (0x27 << XLPII_FSEL);
 124         nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val);
 125
 126         val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG);
 127         val |= (1 << XLPII_VVLD);
 128         nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val);
 129
 130         /* PHY reset */
 131         val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST);
 132         val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP
 133                 | XLPII_TESTPDSSP | XLPII_TESTBURNIN);
 134         nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val);
 135
 136         /* Setup control register */
 137         val =  XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT)
 138                 | (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ
 139                 | XLPII_RETENABLEN | XLPII_XHCIREV;
 140         nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val);
 141
 142         /* Enable interrupts */
 143         nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001);
 144
 145         /* Clear all interrupts */
 146         nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
 147
 148         udelay(2000);
 149
 150         /* XHCI configuration at PCI mem */
 151         pci_base = nlm_xlpii_get_usb_pcibase(node, port);
 152         xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf;
 153         corebase = ioremap(xhci_base, 0x10000);
 154         if (!corebase)
 155                 return;
 156
 157         writel(0x240002, corebase + 0xc2c0);
 158         /* GCTL 0xc110 */
 159         val = readl(corebase + 0xc110);
 160         val &= ~(0x3 << 12);
 161         val |= (1 << 12);
 162         writel(val, corebase + 0xc110);
 163         udelay(100);
 164
 165         /* PHYCFG 0xc200 */
 166         val = readl(corebase + 0xc200);
 167         val &= ~(1 << 6);
 168         writel(val, corebase + 0xc200);
 169         udelay(100);
 170
 171         /* PIPECTL 0xc2c0 */
 172         val = readl(corebase + 0xc2c0);
 173         val &= ~(1 << 17);
 174         writel(val, corebase + 0xc2c0);
 175
 176         iounmap(corebase);
 177 }
 178
 179 static int __init nlm_platform_xlpii_usb_init(void)
 180 {
 181         if (!cpu_is_xlpii())
 182                 return 0;
 183
 184         pr_info("Initializing 2XX USB Interface\n");
 185         nlm_xlpii_usb_hw_reset(0, 1);
 186         nlm_xlpii_usb_hw_reset(0, 2);
 187         nlm_xlpii_usb_hw_reset(0, 3);
 188         nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack);
 189         nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack);
 190         nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack);
 191
 192         return 0;
 193 }
 194
 195 arch_initcall(nlm_platform_xlpii_usb_init);
 196
 197 static u64 xlp_usb_dmamask = ~(u32)0;
 198
 199 /* Fixup IRQ for USB devices on XLP the SoC PCIe bus */
 200 static void nlm_usb_fixup_final(struct pci_dev *dev)
 201 {
 202         dev->dev.dma_mask               = &xlp_usb_dmamask;
 203         dev->dev.coherent_dma_mask      = DMA_BIT_MASK(32);
 204         switch (dev->devfn) {
 205         case 0x21:
 206                 dev->irq = PIC_2XX_XHCI_0_IRQ;
 207                 break;
 208         case 0x22:
 209                 dev->irq = PIC_2XX_XHCI_1_IRQ;
 210                 break;
 211         case 0x23:
 212                 dev->irq = PIC_2XX_XHCI_2_IRQ;
 213                 break;
 214         }
 215 }
 216
 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
 218                 nlm_usb_fixup_final);