2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2009 Cavium Networks
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/time.h>
13 #include <linux/delay.h>
14 #include <linux/swiotlb.h>
18 #include <asm/octeon/octeon.h>
19 #include <asm/octeon/cvmx-npi-defs.h>
20 #include <asm/octeon/cvmx-pci-defs.h>
21 #include <asm/octeon/pci-octeon.h>
23 #include <dma-coherence.h>
25 #define USE_OCTEON_INTERNAL_ARBITER
28 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
29 * addresses. Use PCI endian swapping 1 so no address swapping is
30 * necessary. The Linux io routines will endian swap the data.
32 #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
33 #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
35 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
36 #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
38 u64 octeon_bar1_pci_phys
;
41 * This is the bit decoding used for the Octeon PCI controller addresses
43 union octeon_pci_address
{
52 uint64_t endian_swap
:2;
53 uint64_t reserved3
:10;
61 int __initdata (*octeon_pcibios_map_irq
)(const struct pci_dev
*dev
,
63 enum octeon_dma_bar_type octeon_dma_bar_type
= OCTEON_DMA_BAR_TYPE_INVALID
;
66 * Map a PCI device to the appropriate interrupt line
68 * @dev: The Linux PCI device structure for the device to map
69 * @slot: The slot number for this device on __BUS 0__. Linux
70 * enumerates through all the bridges and figures out the
71 * slot on Bus 0 where this device eventually hooks to.
72 * @pin: The PCI interrupt pin read from the device, then swizzled
73 * as it goes through each bridge.
74 * Returns Interrupt number for the device
76 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
78 if (octeon_pcibios_map_irq
)
79 return octeon_pcibios_map_irq(dev
, slot
, pin
);
81 panic("octeon_pcibios_map_irq not set.");
86 * Called to perform platform specific PCI setup
88 int pcibios_plat_dev_init(struct pci_dev
*dev
)
94 * Force the Cache line setting to 64 bytes. The standard
95 * Linux bus scan doesn't seem to set it. Octeon really has
96 * 128 byte lines, but Intel bridges get really upset if you
97 * try and set values above 64 bytes. Value is specified in
100 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, 64 / 4);
101 /* Set latency timers for all devices */
102 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
104 /* Enable reporting System errors and parity errors on all devices */
105 /* Enable parity checking and error reporting */
106 pci_read_config_word(dev
, PCI_COMMAND
, &config
);
107 config
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
108 pci_write_config_word(dev
, PCI_COMMAND
, config
);
110 if (dev
->subordinate
) {
111 /* Set latency timers on sub bridges */
112 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
, 64);
113 /* More bridge error detection */
114 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &config
);
115 config
|= PCI_BRIDGE_CTL_PARITY
| PCI_BRIDGE_CTL_SERR
;
116 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, config
);
119 /* Enable the PCIe normal error reporting */
120 config
= PCI_EXP_DEVCTL_CERE
; /* Correctable Error Reporting */
121 config
|= PCI_EXP_DEVCTL_NFERE
; /* Non-Fatal Error Reporting */
122 config
|= PCI_EXP_DEVCTL_FERE
; /* Fatal Error Reporting */
123 config
|= PCI_EXP_DEVCTL_URRE
; /* Unsupported Request */
124 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, config
);
126 /* Find the Advanced Error Reporting capability */
127 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
129 /* Clear Uncorrectable Error Status */
130 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
,
132 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
,
134 /* Enable reporting of all uncorrectable errors */
135 /* Uncorrectable Error Mask - turned on bits disable errors */
136 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, 0);
138 * Leave severity at HW default. This only controls if
139 * errors are reported as uncorrectable or
140 * correctable, not if the error is reported.
142 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
143 /* Clear Correctable Error Status */
144 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, &dconfig
);
145 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, dconfig
);
146 /* Enable reporting of all correctable errors */
147 /* Correctable Error Mask - turned on bits disable errors */
148 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, 0);
149 /* Advanced Error Capabilities */
150 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, &dconfig
);
151 /* ECRC Generation Enable */
152 if (config
& PCI_ERR_CAP_ECRC_GENC
)
153 config
|= PCI_ERR_CAP_ECRC_GENE
;
154 /* ECRC Check Enable */
155 if (config
& PCI_ERR_CAP_ECRC_CHKC
)
156 config
|= PCI_ERR_CAP_ECRC_CHKE
;
157 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, dconfig
);
158 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
159 /* Report all errors to the root complex */
160 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
,
161 PCI_ERR_ROOT_CMD_COR_EN
|
162 PCI_ERR_ROOT_CMD_NONFATAL_EN
|
163 PCI_ERR_ROOT_CMD_FATAL_EN
);
164 /* Clear the Root status register */
165 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, &dconfig
);
166 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, dconfig
);
169 dev
->dev
.archdata
.dma_ops
= octeon_pci_dma_map_ops
;
175 * Return the mapping of PCI device number to IRQ line. Each
176 * character in the return string represents the interrupt
177 * line for the device at that position. Device 1 maps to the
178 * first character, etc. The characters A-D are used for PCI
181 * Returns PCI interrupt mapping
183 const char *octeon_get_pci_interrupts(void)
186 * Returning an empty string causes the interrupts to be
187 * routed based on the PCI specification. From the PCI spec:
189 * INTA# of Device Number 0 is connected to IRQW on the system
190 * board. (Device Number has no significance regarding being
191 * located on the system board or in a connector.) INTA# of
192 * Device Number 1 is connected to IRQX on the system
193 * board. INTA# of Device Number 2 is connected to IRQY on the
194 * system board. INTA# of Device Number 3 is connected to IRQZ
195 * on the system board. The table below describes how each
196 * agent's INTx# lines are connected to the system board
197 * interrupt lines. The following equation can be used to
198 * determine to which INTx# signal on the system board a given
199 * device's INTx# line(s) is connected.
201 * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
202 * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
203 * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
206 switch (octeon_bootinfo
->board_type
) {
207 case CVMX_BOARD_TYPE_NAO38
:
208 /* This is really the NAC38 */
209 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
210 case CVMX_BOARD_TYPE_EBH3100
:
211 case CVMX_BOARD_TYPE_CN3010_EVB_HS5
:
212 case CVMX_BOARD_TYPE_CN3005_EVB_HS5
:
213 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
214 case CVMX_BOARD_TYPE_BBGW_REF
:
216 case CVMX_BOARD_TYPE_THUNDER
:
217 case CVMX_BOARD_TYPE_EBH3000
:
224 * Map a PCI device to the appropriate interrupt line
226 * @dev: The Linux PCI device structure for the device to map
227 * @slot: The slot number for this device on __BUS 0__. Linux
228 * enumerates through all the bridges and figures out the
229 * slot on Bus 0 where this device eventually hooks to.
230 * @pin: The PCI interrupt pin read from the device, then swizzled
231 * as it goes through each bridge.
232 * Returns Interrupt number for the device
234 int __init
octeon_pci_pcibios_map_irq(const struct pci_dev
*dev
,
238 const char *interrupts
;
241 /* Get the board specific interrupt mapping */
242 interrupts
= octeon_get_pci_interrupts();
244 dev_num
= dev
->devfn
>> 3;
245 if (dev_num
< strlen(interrupts
))
246 irq_num
= ((interrupts
[dev_num
] - 'A' + pin
- 1) & 3) +
249 irq_num
= ((slot
+ pin
- 3) & 3) + OCTEON_IRQ_PCI_INT0
;
255 * Read a value from configuration space
257 static int octeon_read_config(struct pci_bus
*bus
, unsigned int devfn
,
258 int reg
, int size
, u32
*val
)
260 union octeon_pci_address pci_addr
;
263 pci_addr
.s
.upper
= 2;
266 pci_addr
.s
.subdid
= 1;
267 pci_addr
.s
.endian_swap
= 1;
268 pci_addr
.s
.bus
= bus
->number
;
269 pci_addr
.s
.dev
= devfn
>> 3;
270 pci_addr
.s
.func
= devfn
& 0x7;
271 pci_addr
.s
.reg
= reg
;
273 #if PCI_CONFIG_SPACE_DELAY
274 udelay(PCI_CONFIG_SPACE_DELAY
);
278 *val
= le32_to_cpu(cvmx_read64_uint32(pci_addr
.u64
));
279 return PCIBIOS_SUCCESSFUL
;
281 *val
= le16_to_cpu(cvmx_read64_uint16(pci_addr
.u64
));
282 return PCIBIOS_SUCCESSFUL
;
284 *val
= cvmx_read64_uint8(pci_addr
.u64
);
285 return PCIBIOS_SUCCESSFUL
;
287 return PCIBIOS_FUNC_NOT_SUPPORTED
;
292 * Write a value to PCI configuration space
294 static int octeon_write_config(struct pci_bus
*bus
, unsigned int devfn
,
295 int reg
, int size
, u32 val
)
297 union octeon_pci_address pci_addr
;
300 pci_addr
.s
.upper
= 2;
303 pci_addr
.s
.subdid
= 1;
304 pci_addr
.s
.endian_swap
= 1;
305 pci_addr
.s
.bus
= bus
->number
;
306 pci_addr
.s
.dev
= devfn
>> 3;
307 pci_addr
.s
.func
= devfn
& 0x7;
308 pci_addr
.s
.reg
= reg
;
310 #if PCI_CONFIG_SPACE_DELAY
311 udelay(PCI_CONFIG_SPACE_DELAY
);
315 cvmx_write64_uint32(pci_addr
.u64
, cpu_to_le32(val
));
316 return PCIBIOS_SUCCESSFUL
;
318 cvmx_write64_uint16(pci_addr
.u64
, cpu_to_le16(val
));
319 return PCIBIOS_SUCCESSFUL
;
321 cvmx_write64_uint8(pci_addr
.u64
, val
);
322 return PCIBIOS_SUCCESSFUL
;
324 return PCIBIOS_FUNC_NOT_SUPPORTED
;
328 static struct pci_ops octeon_pci_ops
= {
333 static struct resource octeon_pci_mem_resource
= {
336 .name
= "Octeon PCI MEM",
337 .flags
= IORESOURCE_MEM
,
341 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
344 static struct resource octeon_pci_io_resource
= {
346 .end
= OCTEON_PCI_IOSPACE_SIZE
- 1,
347 .name
= "Octeon PCI IO",
348 .flags
= IORESOURCE_IO
,
351 static struct pci_controller octeon_pci_controller
= {
352 .pci_ops
= &octeon_pci_ops
,
353 .mem_resource
= &octeon_pci_mem_resource
,
354 .mem_offset
= OCTEON_PCI_MEMSPACE_OFFSET
,
355 .io_resource
= &octeon_pci_io_resource
,
357 .io_map_base
= OCTEON_PCI_IOSPACE_BASE
,
362 * Low level initialize the Octeon PCI controller
364 static void octeon_pci_initialize(void)
366 union cvmx_pci_cfg01 cfg01
;
367 union cvmx_npi_ctl_status ctl_status
;
368 union cvmx_pci_ctl_status_2 ctl_status_2
;
369 union cvmx_pci_cfg19 cfg19
;
370 union cvmx_pci_cfg16 cfg16
;
371 union cvmx_pci_cfg22 cfg22
;
372 union cvmx_pci_cfg56 cfg56
;
374 /* Reset the PCI Bus */
375 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, 0x1);
376 cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
378 udelay(2000); /* Hold PCI reset for 2 ms */
380 ctl_status
.u64
= 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
381 ctl_status
.s
.max_word
= 1;
382 ctl_status
.s
.timer
= 1;
383 cvmx_write_csr(CVMX_NPI_CTL_STATUS
, ctl_status
.u64
);
385 /* Deassert PCI reset and advertize PCX Host Mode Device Capability
387 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, 0x4);
388 cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
390 udelay(2000); /* Wait 2 ms after deasserting PCI reset */
392 ctl_status_2
.u32
= 0;
393 ctl_status_2
.s
.tsr_hwm
= 1; /* Initializes to 0. Must be set
394 before any PCI reads. */
395 ctl_status_2
.s
.bar2pres
= 1; /* Enable BAR2 */
396 ctl_status_2
.s
.bar2_enb
= 1;
397 ctl_status_2
.s
.bar2_cax
= 1; /* Don't use L2 */
398 ctl_status_2
.s
.bar2_esx
= 1;
399 ctl_status_2
.s
.pmo_amod
= 1; /* Round robin priority */
400 if (octeon_dma_bar_type
== OCTEON_DMA_BAR_TYPE_BIG
) {
402 ctl_status_2
.s
.bb1_hole
= OCTEON_PCI_BAR1_HOLE_BITS
;
403 ctl_status_2
.s
.bb1_siz
= 1; /* BAR1 is 2GB */
404 ctl_status_2
.s
.bb_ca
= 1; /* Don't use L2 with big bars */
405 ctl_status_2
.s
.bb_es
= 1; /* Big bar in byte swap mode */
406 ctl_status_2
.s
.bb1
= 1; /* BAR1 is big */
407 ctl_status_2
.s
.bb0
= 1; /* BAR0 is big */
410 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2
, ctl_status_2
.u32
);
411 udelay(2000); /* Wait 2 ms before doing PCI reads */
413 ctl_status_2
.u32
= octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2
);
414 pr_notice("PCI Status: %s %s-bit\n",
415 ctl_status_2
.s
.ap_pcix
? "PCI-X" : "PCI",
416 ctl_status_2
.s
.ap_64ad
? "64" : "32");
418 if (OCTEON_IS_MODEL(OCTEON_CN58XX
) || OCTEON_IS_MODEL(OCTEON_CN50XX
)) {
419 union cvmx_pci_cnt_reg cnt_reg_start
;
420 union cvmx_pci_cnt_reg cnt_reg_end
;
421 unsigned long cycles
, pci_clock
;
423 cnt_reg_start
.u64
= cvmx_read_csr(CVMX_NPI_PCI_CNT_REG
);
424 cycles
= read_c0_cvmcount();
426 cnt_reg_end
.u64
= cvmx_read_csr(CVMX_NPI_PCI_CNT_REG
);
427 cycles
= read_c0_cvmcount() - cycles
;
428 pci_clock
= (cnt_reg_end
.s
.pcicnt
- cnt_reg_start
.s
.pcicnt
) /
429 (cycles
/ (mips_hpt_frequency
/ 1000000));
430 pr_notice("PCI Clock: %lu MHz\n", pci_clock
);
434 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
435 * in PCI-X mode to allow four outstanding splits. Otherwise,
436 * should not change from its reset value. Don't write PCI_CFG19
437 * in PCI mode (0x82000001 reset value), write it to 0x82000004
438 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
439 * MRBCM -> must be one.
441 if (ctl_status_2
.s
.ap_pcix
) {
444 * Target Delayed/Split request outstanding maximum
445 * count. [1..31] and 0=32. NOTE: If the user
446 * programs these bits beyond the Designed Maximum
447 * outstanding count, then the designed maximum table
448 * depth will be used instead. No additional
449 * Deferred/Split transactions will be accepted if
450 * this outstanding maximum count is
451 * reached. Furthermore, no additional deferred/split
452 * transactions will be accepted if the I/O delay/ I/O
453 * Split Request outstanding maximum is reached.
457 * Master Deferred Read Request Outstanding Max Count
458 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
459 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
460 * 5 2 110 6 3 111 7 3 For example, if these bits are
461 * programmed to 100, the core can support 2 DAC
462 * cycles, 4 SAC cycles or a combination of 1 DAC and
463 * 2 SAC cycles. NOTE: For the PCI-X maximum
464 * outstanding split transactions, refer to
469 * Master Request (Memory Read) Byte Count/Byte Enable
470 * select. 0 = Byte Enables valid. In PCI mode, a
471 * burst transaction cannot be performed using Memory
472 * Read command=4?h6. 1 = DWORD Byte Count valid
473 * (default). In PCI Mode, the memory read byte
474 * enables are automatically generated by the
475 * core. Note: N3 Master Request transaction sizes are
476 * always determined through the
477 * am_attr[<35:32>|<7:0>] field.
480 octeon_npi_write32(CVMX_NPI_PCI_CFG19
, cfg19
.u32
);
485 cfg01
.s
.msae
= 1; /* Memory Space Access Enable */
486 cfg01
.s
.me
= 1; /* Master Enable */
487 cfg01
.s
.pee
= 1; /* PERR# Enable */
488 cfg01
.s
.see
= 1; /* System Error Enable */
489 cfg01
.s
.fbbe
= 1; /* Fast Back to Back Transaction Enable */
491 octeon_npi_write32(CVMX_NPI_PCI_CFG01
, cfg01
.u32
);
493 #ifdef USE_OCTEON_INTERNAL_ARBITER
495 * When OCTEON is a PCI host, most systems will use OCTEON's
496 * internal arbiter, so must enable it before any PCI/PCI-X
500 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg
;
502 pci_int_arb_cfg
.u64
= 0;
503 pci_int_arb_cfg
.s
.en
= 1; /* Internal arbiter enable */
504 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG
, pci_int_arb_cfg
.u64
);
506 #endif /* USE_OCTEON_INTERNAL_ARBITER */
509 * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
510 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
514 cfg16
.s
.mltd
= 1; /* Master Latency Timer Disable */
515 octeon_npi_write32(CVMX_NPI_PCI_CFG16
, cfg16
.u32
);
518 * Should be written to 0x4ff00. MTTV -> must be zero.
519 * FLUSH -> must be 1. MRV -> should be 0xFF.
522 /* Master Retry Value [1..255] and 0=infinite */
525 * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
529 octeon_npi_write32(CVMX_NPI_PCI_CFG22
, cfg22
.u32
);
532 * MOST Indicates the maximum number of outstanding splits (in -1
533 * notation) when OCTEON is in PCI-X mode. PCI-X performance is
534 * affected by the MOST selection. Should generally be written
535 * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
536 * depending on the desired MOST of 3, 2, 1, or 0, respectively.
539 cfg56
.s
.pxcid
= 7; /* RO - PCI-X Capability ID */
540 cfg56
.s
.ncp
= 0xe8; /* RO - Next Capability Pointer */
541 cfg56
.s
.dpere
= 1; /* Data Parity Error Recovery Enable */
542 cfg56
.s
.roe
= 1; /* Relaxed Ordering Enable */
543 cfg56
.s
.mmbc
= 1; /* Maximum Memory Byte Count
544 [0=512B,1=1024B,2=2048B,3=4096B] */
545 cfg56
.s
.most
= 3; /* Maximum outstanding Split transactions [0=1
548 octeon_npi_write32(CVMX_NPI_PCI_CFG56
, cfg56
.u32
);
551 * Affects PCI performance when OCTEON services reads to its
552 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
553 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
554 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
555 * these values need to be changed so they won't possibly prefetch off
556 * of the end of memory if PCI is DMAing a buffer at the end of
557 * memory. Note that these values differ from their reset values.
559 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6
, 0x21);
560 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C
, 0x31);
561 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E
, 0x31);
566 * Initialize the Octeon PCI controller
568 static int __init
octeon_pci_setup(void)
570 union cvmx_npi_mem_access_subidx mem_access
;
573 /* Only these chips have PCI */
574 if (octeon_has_feature(OCTEON_FEATURE_PCIE
))
577 /* Point pcibios_map_irq() to the PCI version of it */
578 octeon_pcibios_map_irq
= octeon_pci_pcibios_map_irq
;
580 /* Only use the big bars on chips that support it */
581 if (OCTEON_IS_MODEL(OCTEON_CN31XX
) ||
582 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2
) ||
583 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1
))
584 octeon_dma_bar_type
= OCTEON_DMA_BAR_TYPE_SMALL
;
586 octeon_dma_bar_type
= OCTEON_DMA_BAR_TYPE_BIG
;
588 /* PCI I/O and PCI MEM values */
589 set_io_port_base(OCTEON_PCI_IOSPACE_BASE
);
590 ioport_resource
.start
= 0;
591 ioport_resource
.end
= OCTEON_PCI_IOSPACE_SIZE
- 1;
592 if (!octeon_is_pci_host()) {
593 pr_notice("Not in host mode, PCI Controller not initialized\n");
597 pr_notice("%s Octeon big bar support\n",
598 (octeon_dma_bar_type
==
599 OCTEON_DMA_BAR_TYPE_BIG
) ? "Enabling" : "Disabling");
601 octeon_pci_initialize();
604 mem_access
.s
.esr
= 1; /* Endian-Swap on read. */
605 mem_access
.s
.esw
= 1; /* Endian-Swap on write. */
606 mem_access
.s
.nsr
= 0; /* No-Snoop on read. */
607 mem_access
.s
.nsw
= 0; /* No-Snoop on write. */
608 mem_access
.s
.ror
= 0; /* Relax Read on read. */
609 mem_access
.s
.row
= 0; /* Relax Order on write. */
610 mem_access
.s
.ba
= 0; /* PCI Address bits [63:36]. */
611 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3
, mem_access
.u64
);
614 * Remap the Octeon BAR 2 above all 32 bit devices
615 * (0x8000000000ul). This is done here so it is remapped
616 * before the readl()'s below. We don't want BAR2 overlapping
617 * with BAR0/BAR1 during these reads.
619 octeon_npi_write32(CVMX_NPI_PCI_CFG08
,
620 (u32
)(OCTEON_BAR2_PCI_ADDRESS
& 0xffffffffull
));
621 octeon_npi_write32(CVMX_NPI_PCI_CFG09
,
622 (u32
)(OCTEON_BAR2_PCI_ADDRESS
>> 32));
624 if (octeon_dma_bar_type
== OCTEON_DMA_BAR_TYPE_BIG
) {
625 /* Remap the Octeon BAR 0 to 0-2GB */
626 octeon_npi_write32(CVMX_NPI_PCI_CFG04
, 0);
627 octeon_npi_write32(CVMX_NPI_PCI_CFG05
, 0);
630 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
633 octeon_npi_write32(CVMX_NPI_PCI_CFG06
, 2ul << 30);
634 octeon_npi_write32(CVMX_NPI_PCI_CFG07
, 0);
636 /* BAR1 movable mappings set for identity mapping */
637 octeon_bar1_pci_phys
= 0x80000000ull
;
638 for (index
= 0; index
< 32; index
++) {
639 union cvmx_pci_bar1_indexx bar1_index
;
642 /* Address bits[35:22] sent to L2C */
643 bar1_index
.s
.addr_idx
=
644 (octeon_bar1_pci_phys
>> 22) + index
;
645 /* Don't put PCI accesses in L2. */
647 /* Endian Swap Mode */
648 bar1_index
.s
.end_swp
= 1;
649 /* Set '1' when the selected address range is valid. */
650 bar1_index
.s
.addr_v
= 1;
651 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index
),
655 /* Devices go after BAR1 */
656 octeon_pci_mem_resource
.start
=
657 OCTEON_PCI_MEMSPACE_OFFSET
+ (4ul << 30) -
658 (OCTEON_PCI_BAR1_HOLE_SIZE
<< 20);
659 octeon_pci_mem_resource
.end
=
660 octeon_pci_mem_resource
.start
+ (1ul << 30);
662 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
663 octeon_npi_write32(CVMX_NPI_PCI_CFG04
, 128ul << 20);
664 octeon_npi_write32(CVMX_NPI_PCI_CFG05
, 0);
666 /* Remap the Octeon BAR 1 to map 0-128MB */
667 octeon_npi_write32(CVMX_NPI_PCI_CFG06
, 0);
668 octeon_npi_write32(CVMX_NPI_PCI_CFG07
, 0);
670 /* BAR1 movable regions contiguous to cover the swiotlb */
671 octeon_bar1_pci_phys
=
672 virt_to_phys(octeon_swiotlb
) & ~((1ull << 22) - 1);
674 for (index
= 0; index
< 32; index
++) {
675 union cvmx_pci_bar1_indexx bar1_index
;
678 /* Address bits[35:22] sent to L2C */
679 bar1_index
.s
.addr_idx
=
680 (octeon_bar1_pci_phys
>> 22) + index
;
681 /* Don't put PCI accesses in L2. */
683 /* Endian Swap Mode */
684 bar1_index
.s
.end_swp
= 1;
685 /* Set '1' when the selected address range is valid. */
686 bar1_index
.s
.addr_v
= 1;
687 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index
),
691 /* Devices go after BAR0 */
692 octeon_pci_mem_resource
.start
=
693 OCTEON_PCI_MEMSPACE_OFFSET
+ (128ul << 20) +
695 octeon_pci_mem_resource
.end
=
696 octeon_pci_mem_resource
.start
+ (1ul << 30);
699 register_pci_controller(&octeon_pci_controller
);
702 * Clear any errors that might be pending from before the bus
703 * was setup properly.
705 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2
, -1);
707 octeon_pci_dma_init();
712 arch_initcall(octeon_pci_setup
);